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14#include "hw_atl_llh.h"
15#include "hw_atl_llh_internal.h"
16#include "../aq_hw_utils.h"
17
18
19void reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, u32 semaphore)
20{
21 aq_hw_write_reg(aq_hw, glb_cpu_sem_adr(semaphore), glb_cpu_sem);
22}
23
24u32 reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
25{
26 return aq_hw_read_reg(aq_hw, glb_cpu_sem_adr(semaphore));
27}
28
29void glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
30{
31 aq_hw_write_reg_bit(aq_hw, glb_reg_res_dis_adr,
32 glb_reg_res_dis_msk,
33 glb_reg_res_dis_shift,
34 glb_reg_res_dis);
35}
36
37void glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
38{
39 aq_hw_write_reg_bit(aq_hw, glb_soft_res_adr, glb_soft_res_msk,
40 glb_soft_res_shift, soft_res);
41}
42
43u32 glb_soft_res_get(struct aq_hw_s *aq_hw)
44{
45 return aq_hw_read_reg_bit(aq_hw, glb_soft_res_adr,
46 glb_soft_res_msk,
47 glb_soft_res_shift);
48}
49
50u32 reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw)
51{
52 return aq_hw_read_reg(aq_hw, rx_dma_stat_counter7_adr);
53}
54
55u32 reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
56{
57 return aq_hw_read_reg(aq_hw, glb_mif_id_adr);
58}
59
60
61u32 rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
62{
63 return aq_hw_read_reg(aq_hw, rpb_rx_dma_drop_pkt_cnt_adr);
64}
65
66u32 stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
67{
68 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_octet_counterlsw__adr);
69}
70
71u32 stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
72{
73 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_pkt_counterlsw__adr);
74}
75
76u32 stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
77{
78 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_octet_counterlsw__adr);
79}
80
81u32 stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
82{
83 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_pkt_counterlsw__adr);
84}
85
86u32 stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
87{
88 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_octet_countermsw__adr);
89}
90
91u32 stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
92{
93 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_pkt_countermsw__adr);
94}
95
96u32 stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
97{
98 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_octet_countermsw__adr);
99}
100
101u32 stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
102{
103 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_pkt_countermsw__adr);
104}
105
106
107void itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, u32 irq_auto_masklsw)
108{
109 aq_hw_write_reg(aq_hw, itr_iamrlsw_adr, irq_auto_masklsw);
110}
111
112void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx)
113{
114
115 static u32 itr_imr_rxren_adr[32] = {
116 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
117 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU,
118 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
119 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU,
120 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
121 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU,
122 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
123 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU
124 };
125
126
127 static u32 itr_imr_rxren_msk[32] = {
128 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
129 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
130 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
131 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
132 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
133 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
134 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
135 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U
136 };
137
138
139 static u32 itr_imr_rxren_shift[32] = {
140 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
141 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
142 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
143 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U
144 };
145
146 aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx],
147 itr_imr_rxren_msk[rx],
148 itr_imr_rxren_shift[rx],
149 irq_map_en_rx);
150}
151
152void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx)
153{
154
155 static u32 itr_imr_txten_adr[32] = {
156 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
157 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU,
158 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
159 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU,
160 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
161 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU,
162 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
163 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU
164 };
165
166
167 static u32 itr_imr_txten_msk[32] = {
168 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
169 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
170 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
171 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
172 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
173 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
174 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
175 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U
176 };
177
178
179 static u32 itr_imr_txten_shift[32] = {
180 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
181 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
182 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
183 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U
184 };
185
186 aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx],
187 itr_imr_txten_msk[tx],
188 itr_imr_txten_shift[tx],
189 irq_map_en_tx);
190}
191
192void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
193{
194
195 static u32 itr_imr_rxr_adr[32] = {
196 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
197 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU,
198 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
199 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU,
200 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
201 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU,
202 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
203 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU
204 };
205
206
207 static u32 itr_imr_rxr_msk[32] = {
208 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
209 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
210 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
211 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
212 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
213 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
214 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
215 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU
216 };
217
218
219 static u32 itr_imr_rxr_shift[32] = {
220 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
221 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
222 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
223 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U
224 };
225
226 aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx],
227 itr_imr_rxr_msk[rx],
228 itr_imr_rxr_shift[rx],
229 irq_map_rx);
230}
231
232void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
233{
234
235 static u32 itr_imr_txt_adr[32] = {
236 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
237 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU,
238 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
239 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU,
240 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
241 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU,
242 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
243 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU
244 };
245
246
247 static u32 itr_imr_txt_msk[32] = {
248 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
249 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
250 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
251 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
252 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
253 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
254 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
255 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U
256 };
257
258
259 static u32 itr_imr_txt_shift[32] = {
260 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
261 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
262 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
263 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U
264 };
265
266 aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx],
267 itr_imr_txt_msk[tx],
268 itr_imr_txt_shift[tx],
269 irq_map_tx);
270}
271
272void itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_clearlsw)
273{
274 aq_hw_write_reg(aq_hw, itr_imcrlsw_adr, irq_msk_clearlsw);
275}
276
277void itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
278{
279 aq_hw_write_reg(aq_hw, itr_imsrlsw_adr, irq_msk_setlsw);
280}
281
282void itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
283{
284 aq_hw_write_reg_bit(aq_hw, itr_reg_res_dsbl_adr,
285 itr_reg_res_dsbl_msk,
286 itr_reg_res_dsbl_shift, irq_reg_res_dis);
287}
288
289void itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
290 u32 irq_status_clearlsw)
291{
292 aq_hw_write_reg(aq_hw, itr_iscrlsw_adr, irq_status_clearlsw);
293}
294
295u32 itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
296{
297 return aq_hw_read_reg(aq_hw, itr_isrlsw_adr);
298}
299
300u32 itr_res_irq_get(struct aq_hw_s *aq_hw)
301{
302 return aq_hw_read_reg_bit(aq_hw, itr_res_adr, itr_res_msk,
303 itr_res_shift);
304}
305
306void itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
307{
308 aq_hw_write_reg_bit(aq_hw, itr_res_adr, itr_res_msk,
309 itr_res_shift, res_irq);
310}
311
312
313void rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
314{
315 aq_hw_write_reg_bit(aq_hw, rdm_dcadcpuid_adr(dca),
316 rdm_dcadcpuid_msk,
317 rdm_dcadcpuid_shift, cpuid);
318}
319
320void rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
321{
322 aq_hw_write_reg_bit(aq_hw, rdm_dca_en_adr, rdm_dca_en_msk,
323 rdm_dca_en_shift, rx_dca_en);
324}
325
326void rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
327{
328 aq_hw_write_reg_bit(aq_hw, rdm_dca_mode_adr, rdm_dca_mode_msk,
329 rdm_dca_mode_shift, rx_dca_mode);
330}
331
332void rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
333 u32 rx_desc_data_buff_size, u32 descriptor)
334{
335 aq_hw_write_reg_bit(aq_hw, rdm_descddata_size_adr(descriptor),
336 rdm_descddata_size_msk,
337 rdm_descddata_size_shift,
338 rx_desc_data_buff_size);
339}
340
341void rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, u32 dca)
342{
343 aq_hw_write_reg_bit(aq_hw, rdm_dcaddesc_en_adr(dca),
344 rdm_dcaddesc_en_msk,
345 rdm_dcaddesc_en_shift,
346 rx_desc_dca_en);
347}
348
349void rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, u32 descriptor)
350{
351 aq_hw_write_reg_bit(aq_hw, rdm_descden_adr(descriptor),
352 rdm_descden_msk,
353 rdm_descden_shift,
354 rx_desc_en);
355}
356
357void rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
358 u32 rx_desc_head_buff_size, u32 descriptor)
359{
360 aq_hw_write_reg_bit(aq_hw, rdm_descdhdr_size_adr(descriptor),
361 rdm_descdhdr_size_msk,
362 rdm_descdhdr_size_shift,
363 rx_desc_head_buff_size);
364}
365
366void rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
367 u32 rx_desc_head_splitting, u32 descriptor)
368{
369 aq_hw_write_reg_bit(aq_hw, rdm_descdhdr_split_adr(descriptor),
370 rdm_descdhdr_split_msk,
371 rdm_descdhdr_split_shift,
372 rx_desc_head_splitting);
373}
374
375u32 rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
376{
377 return aq_hw_read_reg_bit(aq_hw, rdm_descdhd_adr(descriptor),
378 rdm_descdhd_msk, rdm_descdhd_shift);
379}
380
381void rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, u32 descriptor)
382{
383 aq_hw_write_reg_bit(aq_hw, rdm_descdlen_adr(descriptor),
384 rdm_descdlen_msk, rdm_descdlen_shift,
385 rx_desc_len);
386}
387
388void rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, u32 descriptor)
389{
390 aq_hw_write_reg_bit(aq_hw, rdm_descdreset_adr(descriptor),
391 rdm_descdreset_msk, rdm_descdreset_shift,
392 rx_desc_res);
393}
394
395void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
396 u32 rx_desc_wr_wb_irq_en)
397{
398 aq_hw_write_reg_bit(aq_hw, rdm_int_desc_wrb_en_adr,
399 rdm_int_desc_wrb_en_msk,
400 rdm_int_desc_wrb_en_shift,
401 rx_desc_wr_wb_irq_en);
402}
403
404void rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, u32 dca)
405{
406 aq_hw_write_reg_bit(aq_hw, rdm_dcadhdr_en_adr(dca),
407 rdm_dcadhdr_en_msk,
408 rdm_dcadhdr_en_shift,
409 rx_head_dca_en);
410}
411
412void rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, u32 dca)
413{
414 aq_hw_write_reg_bit(aq_hw, rdm_dcadpay_en_adr(dca),
415 rdm_dcadpay_en_msk, rdm_dcadpay_en_shift,
416 rx_pld_dca_en);
417}
418
419void rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 rdm_intr_moder_en)
420{
421 aq_hw_write_reg_bit(aq_hw, rdm_int_rim_en_adr,
422 rdm_int_rim_en_msk,
423 rdm_int_rim_en_shift,
424 rdm_intr_moder_en);
425}
426
427
428void reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, u32 regidx)
429{
430 aq_hw_write_reg(aq_hw, gen_intr_map_adr(regidx), gen_intr_map);
431}
432
433u32 reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
434{
435 return aq_hw_read_reg(aq_hw, gen_intr_stat_adr);
436}
437
438void reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
439{
440 aq_hw_write_reg(aq_hw, intr_glb_ctl_adr, intr_glb_ctl);
441}
442
443void reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
444{
445 aq_hw_write_reg(aq_hw, intr_thr_adr(throttle), intr_thr);
446}
447
448void reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
449 u32 rx_dma_desc_base_addrlsw,
450 u32 descriptor)
451{
452 aq_hw_write_reg(aq_hw, rx_dma_desc_base_addrlsw_adr(descriptor),
453 rx_dma_desc_base_addrlsw);
454}
455
456void reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
457 u32 rx_dma_desc_base_addrmsw,
458 u32 descriptor)
459{
460 aq_hw_write_reg(aq_hw, rx_dma_desc_base_addrmsw_adr(descriptor),
461 rx_dma_desc_base_addrmsw);
462}
463
464u32 reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
465{
466 return aq_hw_read_reg(aq_hw, rx_dma_desc_stat_adr(descriptor));
467}
468
469void reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
470 u32 rx_dma_desc_tail_ptr, u32 descriptor)
471{
472 aq_hw_write_reg(aq_hw, rx_dma_desc_tail_ptr_adr(descriptor),
473 rx_dma_desc_tail_ptr);
474}
475
476void reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr_msk)
477{
478 aq_hw_write_reg(aq_hw, rx_flr_mcst_flr_msk_adr, rx_flr_mcst_flr_msk);
479}
480
481void reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
482 u32 filter)
483{
484 aq_hw_write_reg(aq_hw, rx_flr_mcst_flr_adr(filter), rx_flr_mcst_flr);
485}
486
487void reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, u32 rx_flr_rss_control1)
488{
489 aq_hw_write_reg(aq_hw, rx_flr_rss_control1_adr, rx_flr_rss_control1);
490}
491
492void reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_filter_control2)
493{
494 aq_hw_write_reg(aq_hw, rx_flr_control2_adr, rx_filter_control2);
495}
496
497void reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
498 u32 rx_intr_moderation_ctl,
499 u32 queue)
500{
501 aq_hw_write_reg(aq_hw, rx_intr_moderation_ctl_adr(queue),
502 rx_intr_moderation_ctl);
503}
504
505void reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, u32 tx_dma_debug_ctl)
506{
507 aq_hw_write_reg(aq_hw, tx_dma_debug_ctl_adr, tx_dma_debug_ctl);
508}
509
510void reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
511 u32 tx_dma_desc_base_addrlsw,
512 u32 descriptor)
513{
514 aq_hw_write_reg(aq_hw, tx_dma_desc_base_addrlsw_adr(descriptor),
515 tx_dma_desc_base_addrlsw);
516}
517
518void reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
519 u32 tx_dma_desc_base_addrmsw,
520 u32 descriptor)
521{
522 aq_hw_write_reg(aq_hw, tx_dma_desc_base_addrmsw_adr(descriptor),
523 tx_dma_desc_base_addrmsw);
524}
525
526void reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
527 u32 tx_dma_desc_tail_ptr, u32 descriptor)
528{
529 aq_hw_write_reg(aq_hw, tx_dma_desc_tail_ptr_adr(descriptor),
530 tx_dma_desc_tail_ptr);
531}
532
533void reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
534 u32 tx_intr_moderation_ctl,
535 u32 queue)
536{
537 aq_hw_write_reg(aq_hw, tx_intr_moderation_ctl_adr(queue),
538 tx_intr_moderation_ctl);
539}
540
541
542void rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
543{
544 aq_hw_write_reg_bit(aq_hw, rpb_dma_sys_lbk_adr,
545 rpb_dma_sys_lbk_msk,
546 rpb_dma_sys_lbk_shift, dma_sys_lbk);
547}
548
549void rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
550 u32 rx_traf_class_mode)
551{
552 aq_hw_write_reg_bit(aq_hw, rpb_rpf_rx_tc_mode_adr,
553 rpb_rpf_rx_tc_mode_msk,
554 rpb_rpf_rx_tc_mode_shift,
555 rx_traf_class_mode);
556}
557
558void rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
559{
560 aq_hw_write_reg_bit(aq_hw, rpb_rx_buf_en_adr, rpb_rx_buf_en_msk,
561 rpb_rx_buf_en_shift, rx_buff_en);
562}
563
564void rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
565 u32 rx_buff_hi_threshold_per_tc,
566 u32 buffer)
567{
568 aq_hw_write_reg_bit(aq_hw, rpb_rxbhi_thresh_adr(buffer),
569 rpb_rxbhi_thresh_msk, rpb_rxbhi_thresh_shift,
570 rx_buff_hi_threshold_per_tc);
571}
572
573void rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
574 u32 rx_buff_lo_threshold_per_tc,
575 u32 buffer)
576{
577 aq_hw_write_reg_bit(aq_hw, rpb_rxblo_thresh_adr(buffer),
578 rpb_rxblo_thresh_msk,
579 rpb_rxblo_thresh_shift,
580 rx_buff_lo_threshold_per_tc);
581}
582
583void rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
584{
585 aq_hw_write_reg_bit(aq_hw, rpb_rx_fc_mode_adr,
586 rpb_rx_fc_mode_msk,
587 rpb_rx_fc_mode_shift, rx_flow_ctl_mode);
588}
589
590void rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
591 u32 rx_pkt_buff_size_per_tc, u32 buffer)
592{
593 aq_hw_write_reg_bit(aq_hw, rpb_rxbbuf_size_adr(buffer),
594 rpb_rxbbuf_size_msk, rpb_rxbbuf_size_shift,
595 rx_pkt_buff_size_per_tc);
596}
597
598void rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
599 u32 buffer)
600{
601 aq_hw_write_reg_bit(aq_hw, rpb_rxbxoff_en_adr(buffer),
602 rpb_rxbxoff_en_msk, rpb_rxbxoff_en_shift,
603 rx_xoff_en_per_tc);
604}
605
606
607
608void rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
609 u32 l2broadcast_count_threshold)
610{
611 aq_hw_write_reg_bit(aq_hw, rpfl2bc_thresh_adr,
612 rpfl2bc_thresh_msk,
613 rpfl2bc_thresh_shift,
614 l2broadcast_count_threshold);
615}
616
617void rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
618{
619 aq_hw_write_reg_bit(aq_hw, rpfl2bc_en_adr, rpfl2bc_en_msk,
620 rpfl2bc_en_shift, l2broadcast_en);
621}
622
623void rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2broadcast_flr_act)
624{
625 aq_hw_write_reg_bit(aq_hw, rpfl2bc_act_adr, rpfl2bc_act_msk,
626 rpfl2bc_act_shift, l2broadcast_flr_act);
627}
628
629void rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, u32 l2multicast_flr_en,
630 u32 filter)
631{
632 aq_hw_write_reg_bit(aq_hw, rpfl2mc_enf_adr(filter),
633 rpfl2mc_enf_msk,
634 rpfl2mc_enf_shift, l2multicast_flr_en);
635}
636
637void rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
638 u32 l2promiscuous_mode_en)
639{
640 aq_hw_write_reg_bit(aq_hw, rpfl2promis_mode_adr,
641 rpfl2promis_mode_msk,
642 rpfl2promis_mode_shift,
643 l2promiscuous_mode_en);
644}
645
646void rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_act,
647 u32 filter)
648{
649 aq_hw_write_reg_bit(aq_hw, rpfl2uc_actf_adr(filter),
650 rpfl2uc_actf_msk, rpfl2uc_actf_shift,
651 l2unicast_flr_act);
652}
653
654void rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
655 u32 filter)
656{
657 aq_hw_write_reg_bit(aq_hw, rpfl2uc_enf_adr(filter),
658 rpfl2uc_enf_msk,
659 rpfl2uc_enf_shift, l2unicast_flr_en);
660}
661
662void rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
663 u32 l2unicast_dest_addresslsw,
664 u32 filter)
665{
666 aq_hw_write_reg(aq_hw, rpfl2uc_daflsw_adr(filter),
667 l2unicast_dest_addresslsw);
668}
669
670void rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
671 u32 l2unicast_dest_addressmsw,
672 u32 filter)
673{
674 aq_hw_write_reg_bit(aq_hw, rpfl2uc_dafmsw_adr(filter),
675 rpfl2uc_dafmsw_msk, rpfl2uc_dafmsw_shift,
676 l2unicast_dest_addressmsw);
677}
678
679void rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
680 u32 l2_accept_all_mc_packets)
681{
682 aq_hw_write_reg_bit(aq_hw, rpfl2mc_accept_all_adr,
683 rpfl2mc_accept_all_msk,
684 rpfl2mc_accept_all_shift,
685 l2_accept_all_mc_packets);
686}
687
688void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
689 u32 user_priority_tc_map, u32 tc)
690{
691
692 static u32 rpf_rpb_rx_tc_upt_adr[8] = {
693 0x000054c4U, 0x000054c4U, 0x000054c4U, 0x000054c4U,
694 0x000054c4U, 0x000054c4U, 0x000054c4U, 0x000054c4U
695 };
696
697
698 static u32 rpf_rpb_rx_tc_upt_msk[8] = {
699 0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U,
700 0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U
701 };
702
703
704 static u32 rpf_rpb_rx_tc_upt_shft[8] = {
705 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
706 };
707
708 aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc],
709 rpf_rpb_rx_tc_upt_msk[tc],
710 rpf_rpb_rx_tc_upt_shft[tc],
711 user_priority_tc_map);
712}
713
714void rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
715{
716 aq_hw_write_reg_bit(aq_hw, rpf_rss_key_addr_adr,
717 rpf_rss_key_addr_msk,
718 rpf_rss_key_addr_shift,
719 rss_key_addr);
720}
721
722void rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
723{
724 aq_hw_write_reg(aq_hw, rpf_rss_key_wr_data_adr,
725 rss_key_wr_data);
726}
727
728u32 rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
729{
730 return aq_hw_read_reg_bit(aq_hw, rpf_rss_key_wr_eni_adr,
731 rpf_rss_key_wr_eni_msk,
732 rpf_rss_key_wr_eni_shift);
733}
734
735void rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
736{
737 aq_hw_write_reg_bit(aq_hw, rpf_rss_key_wr_eni_adr,
738 rpf_rss_key_wr_eni_msk,
739 rpf_rss_key_wr_eni_shift,
740 rss_key_wr_en);
741}
742
743void rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, u32 rss_redir_tbl_addr)
744{
745 aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_addr_adr,
746 rpf_rss_redir_addr_msk,
747 rpf_rss_redir_addr_shift, rss_redir_tbl_addr);
748}
749
750void rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
751 u32 rss_redir_tbl_wr_data)
752{
753 aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_wr_data_adr,
754 rpf_rss_redir_wr_data_msk,
755 rpf_rss_redir_wr_data_shift,
756 rss_redir_tbl_wr_data);
757}
758
759u32 rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
760{
761 return aq_hw_read_reg_bit(aq_hw, rpf_rss_redir_wr_eni_adr,
762 rpf_rss_redir_wr_eni_msk,
763 rpf_rss_redir_wr_eni_shift);
764}
765
766void rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
767{
768 aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_wr_eni_adr,
769 rpf_rss_redir_wr_eni_msk,
770 rpf_rss_redir_wr_eni_shift, rss_redir_wr_en);
771}
772
773void rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, u32 tpo_to_rpf_sys_lbk)
774{
775 aq_hw_write_reg_bit(aq_hw, rpf_tpo_rpf_sys_lbk_adr,
776 rpf_tpo_rpf_sys_lbk_msk,
777 rpf_tpo_rpf_sys_lbk_shift,
778 tpo_to_rpf_sys_lbk);
779}
780
781void rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
782{
783 aq_hw_write_reg_bit(aq_hw, rpf_vl_inner_tpid_adr,
784 rpf_vl_inner_tpid_msk,
785 rpf_vl_inner_tpid_shift,
786 vlan_inner_etht);
787}
788
789void rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
790{
791 aq_hw_write_reg_bit(aq_hw, rpf_vl_outer_tpid_adr,
792 rpf_vl_outer_tpid_msk,
793 rpf_vl_outer_tpid_shift,
794 vlan_outer_etht);
795}
796
797void rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, u32 vlan_prom_mode_en)
798{
799 aq_hw_write_reg_bit(aq_hw, rpf_vl_promis_mode_adr,
800 rpf_vl_promis_mode_msk,
801 rpf_vl_promis_mode_shift,
802 vlan_prom_mode_en);
803}
804
805void rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
806 u32 vlan_accept_untagged_packets)
807{
808 aq_hw_write_reg_bit(aq_hw, rpf_vl_accept_untagged_mode_adr,
809 rpf_vl_accept_untagged_mode_msk,
810 rpf_vl_accept_untagged_mode_shift,
811 vlan_accept_untagged_packets);
812}
813
814void rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, u32 vlan_untagged_act)
815{
816 aq_hw_write_reg_bit(aq_hw, rpf_vl_untagged_act_adr,
817 rpf_vl_untagged_act_msk,
818 rpf_vl_untagged_act_shift,
819 vlan_untagged_act);
820}
821
822void rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, u32 filter)
823{
824 aq_hw_write_reg_bit(aq_hw, rpf_vl_en_f_adr(filter),
825 rpf_vl_en_f_msk,
826 rpf_vl_en_f_shift,
827 vlan_flr_en);
828}
829
830void rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act, u32 filter)
831{
832 aq_hw_write_reg_bit(aq_hw, rpf_vl_act_f_adr(filter),
833 rpf_vl_act_f_msk,
834 rpf_vl_act_f_shift,
835 vlan_flr_act);
836}
837
838void rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, u32 filter)
839{
840 aq_hw_write_reg_bit(aq_hw, rpf_vl_id_f_adr(filter),
841 rpf_vl_id_f_msk,
842 rpf_vl_id_f_shift,
843 vlan_id_flr);
844}
845
846void rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, u32 filter)
847{
848 aq_hw_write_reg_bit(aq_hw, rpf_et_enf_adr(filter),
849 rpf_et_enf_msk,
850 rpf_et_enf_shift, etht_flr_en);
851}
852
853void rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
854 u32 etht_user_priority_en, u32 filter)
855{
856 aq_hw_write_reg_bit(aq_hw, rpf_et_upfen_adr(filter),
857 rpf_et_upfen_msk, rpf_et_upfen_shift,
858 etht_user_priority_en);
859}
860
861void rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue_en,
862 u32 filter)
863{
864 aq_hw_write_reg_bit(aq_hw, rpf_et_rxqfen_adr(filter),
865 rpf_et_rxqfen_msk, rpf_et_rxqfen_shift,
866 etht_rx_queue_en);
867}
868
869void rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, u32 etht_user_priority,
870 u32 filter)
871{
872 aq_hw_write_reg_bit(aq_hw, rpf_et_upf_adr(filter),
873 rpf_et_upf_msk,
874 rpf_et_upf_shift, etht_user_priority);
875}
876
877void rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
878 u32 filter)
879{
880 aq_hw_write_reg_bit(aq_hw, rpf_et_rxqf_adr(filter),
881 rpf_et_rxqf_msk,
882 rpf_et_rxqf_shift, etht_rx_queue);
883}
884
885void rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
886 u32 filter)
887{
888 aq_hw_write_reg_bit(aq_hw, rpf_et_mng_rxqf_adr(filter),
889 rpf_et_mng_rxqf_msk, rpf_et_mng_rxqf_shift,
890 etht_mgt_queue);
891}
892
893void rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, u32 filter)
894{
895 aq_hw_write_reg_bit(aq_hw, rpf_et_actf_adr(filter),
896 rpf_et_actf_msk,
897 rpf_et_actf_shift, etht_flr_act);
898}
899
900void rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
901{
902 aq_hw_write_reg_bit(aq_hw, rpf_et_valf_adr(filter),
903 rpf_et_valf_msk,
904 rpf_et_valf_shift, etht_flr);
905}
906
907
908void rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
909 u32 ipv4header_crc_offload_en)
910{
911 aq_hw_write_reg_bit(aq_hw, rpo_ipv4chk_en_adr,
912 rpo_ipv4chk_en_msk,
913 rpo_ipv4chk_en_shift,
914 ipv4header_crc_offload_en);
915}
916
917void rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
918 u32 rx_desc_vlan_stripping, u32 descriptor)
919{
920 aq_hw_write_reg_bit(aq_hw, rpo_descdvl_strip_adr(descriptor),
921 rpo_descdvl_strip_msk,
922 rpo_descdvl_strip_shift,
923 rx_desc_vlan_stripping);
924}
925
926void rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
927 u32 tcp_udp_crc_offload_en)
928{
929 aq_hw_write_reg_bit(aq_hw, rpol4chk_en_adr, rpol4chk_en_msk,
930 rpol4chk_en_shift, tcp_udp_crc_offload_en);
931}
932
933void rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
934{
935 aq_hw_write_reg(aq_hw, rpo_lro_en_adr, lro_en);
936}
937
938void rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
939 u32 lro_patch_optimization_en)
940{
941 aq_hw_write_reg_bit(aq_hw, rpo_lro_ptopt_en_adr,
942 rpo_lro_ptopt_en_msk,
943 rpo_lro_ptopt_en_shift,
944 lro_patch_optimization_en);
945}
946
947void rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
948 u32 lro_qsessions_lim)
949{
950 aq_hw_write_reg_bit(aq_hw, rpo_lro_qses_lmt_adr,
951 rpo_lro_qses_lmt_msk,
952 rpo_lro_qses_lmt_shift,
953 lro_qsessions_lim);
954}
955
956void rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, u32 lro_total_desc_lim)
957{
958 aq_hw_write_reg_bit(aq_hw, rpo_lro_tot_dsc_lmt_adr,
959 rpo_lro_tot_dsc_lmt_msk,
960 rpo_lro_tot_dsc_lmt_shift,
961 lro_total_desc_lim);
962}
963
964void rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
965 u32 lro_min_pld_of_first_pkt)
966{
967 aq_hw_write_reg_bit(aq_hw, rpo_lro_pkt_min_adr,
968 rpo_lro_pkt_min_msk,
969 rpo_lro_pkt_min_shift,
970 lro_min_pld_of_first_pkt);
971}
972
973void rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
974{
975 aq_hw_write_reg(aq_hw, rpo_lro_rsc_max_adr, lro_pkt_lim);
976}
977
978void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
979 u32 lro_max_number_of_descriptors,
980 u32 lro)
981{
982
983 static u32 rpo_lro_ldes_max_adr[32] = {
984 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
985 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
986 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
987 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
988 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
989 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
990 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU,
991 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU
992 };
993
994
995 static u32 rpo_lro_ldes_max_msk[32] = {
996 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
997 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
998 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
999 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1000 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1001 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1002 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1003 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U
1004 };
1005
1006
1007 static u32 rpo_lro_ldes_max_shift[32] = {
1008 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1009 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1010 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1011 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
1012 };
1013
1014 aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro],
1015 rpo_lro_ldes_max_msk[lro],
1016 rpo_lro_ldes_max_shift[lro],
1017 lro_max_number_of_descriptors);
1018}
1019
1020void rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
1021 u32 lro_time_base_divider)
1022{
1023 aq_hw_write_reg_bit(aq_hw, rpo_lro_tb_div_adr,
1024 rpo_lro_tb_div_msk,
1025 rpo_lro_tb_div_shift,
1026 lro_time_base_divider);
1027}
1028
1029void rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
1030 u32 lro_inactive_interval)
1031{
1032 aq_hw_write_reg_bit(aq_hw, rpo_lro_ina_ival_adr,
1033 rpo_lro_ina_ival_msk,
1034 rpo_lro_ina_ival_shift,
1035 lro_inactive_interval);
1036}
1037
1038void rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
1039 u32 lro_max_coalescing_interval)
1040{
1041 aq_hw_write_reg_bit(aq_hw, rpo_lro_max_ival_adr,
1042 rpo_lro_max_ival_msk,
1043 rpo_lro_max_ival_shift,
1044 lro_max_coalescing_interval);
1045}
1046
1047
1048void rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
1049{
1050 aq_hw_write_reg_bit(aq_hw, rx_reg_res_dsbl_adr,
1051 rx_reg_res_dsbl_msk,
1052 rx_reg_res_dsbl_shift,
1053 rx_reg_res_dis);
1054}
1055
1056
1057void tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
1058{
1059 aq_hw_write_reg_bit(aq_hw, tdm_dcadcpuid_adr(dca),
1060 tdm_dcadcpuid_msk,
1061 tdm_dcadcpuid_shift, cpuid);
1062}
1063
1064void tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
1065 u32 large_send_offload_en)
1066{
1067 aq_hw_write_reg(aq_hw, tdm_lso_en_adr, large_send_offload_en);
1068}
1069
1070void tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
1071{
1072 aq_hw_write_reg_bit(aq_hw, tdm_dca_en_adr, tdm_dca_en_msk,
1073 tdm_dca_en_shift, tx_dca_en);
1074}
1075
1076void tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
1077{
1078 aq_hw_write_reg_bit(aq_hw, tdm_dca_mode_adr, tdm_dca_mode_msk,
1079 tdm_dca_mode_shift, tx_dca_mode);
1080}
1081
1082void tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, u32 dca)
1083{
1084 aq_hw_write_reg_bit(aq_hw, tdm_dcaddesc_en_adr(dca),
1085 tdm_dcaddesc_en_msk, tdm_dcaddesc_en_shift,
1086 tx_desc_dca_en);
1087}
1088
1089void tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, u32 descriptor)
1090{
1091 aq_hw_write_reg_bit(aq_hw, tdm_descden_adr(descriptor),
1092 tdm_descden_msk,
1093 tdm_descden_shift,
1094 tx_desc_en);
1095}
1096
1097u32 tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
1098{
1099 return aq_hw_read_reg_bit(aq_hw, tdm_descdhd_adr(descriptor),
1100 tdm_descdhd_msk, tdm_descdhd_shift);
1101}
1102
1103void tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
1104 u32 descriptor)
1105{
1106 aq_hw_write_reg_bit(aq_hw, tdm_descdlen_adr(descriptor),
1107 tdm_descdlen_msk,
1108 tdm_descdlen_shift,
1109 tx_desc_len);
1110}
1111
1112void tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
1113 u32 tx_desc_wr_wb_irq_en)
1114{
1115 aq_hw_write_reg_bit(aq_hw, tdm_int_desc_wrb_en_adr,
1116 tdm_int_desc_wrb_en_msk,
1117 tdm_int_desc_wrb_en_shift,
1118 tx_desc_wr_wb_irq_en);
1119}
1120
1121void tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
1122 u32 tx_desc_wr_wb_threshold,
1123 u32 descriptor)
1124{
1125 aq_hw_write_reg_bit(aq_hw, tdm_descdwrb_thresh_adr(descriptor),
1126 tdm_descdwrb_thresh_msk,
1127 tdm_descdwrb_thresh_shift,
1128 tx_desc_wr_wb_threshold);
1129}
1130
1131void tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
1132 u32 tdm_irq_moderation_en)
1133{
1134 aq_hw_write_reg_bit(aq_hw, tdm_int_mod_en_adr,
1135 tdm_int_mod_en_msk,
1136 tdm_int_mod_en_shift,
1137 tdm_irq_moderation_en);
1138}
1139
1140
1141void thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
1142 u32 lso_tcp_flag_of_first_pkt)
1143{
1144 aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_first_adr,
1145 thm_lso_tcp_flag_first_msk,
1146 thm_lso_tcp_flag_first_shift,
1147 lso_tcp_flag_of_first_pkt);
1148}
1149
1150void thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
1151 u32 lso_tcp_flag_of_last_pkt)
1152{
1153 aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_last_adr,
1154 thm_lso_tcp_flag_last_msk,
1155 thm_lso_tcp_flag_last_shift,
1156 lso_tcp_flag_of_last_pkt);
1157}
1158
1159void thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
1160 u32 lso_tcp_flag_of_middle_pkt)
1161{
1162 aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_mid_adr,
1163 thm_lso_tcp_flag_mid_msk,
1164 thm_lso_tcp_flag_mid_shift,
1165 lso_tcp_flag_of_middle_pkt);
1166}
1167
1168
1169void tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
1170{
1171 aq_hw_write_reg_bit(aq_hw, tpb_tx_buf_en_adr, tpb_tx_buf_en_msk,
1172 tpb_tx_buf_en_shift, tx_buff_en);
1173}
1174
1175void tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1176 u32 tx_buff_hi_threshold_per_tc,
1177 u32 buffer)
1178{
1179 aq_hw_write_reg_bit(aq_hw, tpb_txbhi_thresh_adr(buffer),
1180 tpb_txbhi_thresh_msk, tpb_txbhi_thresh_shift,
1181 tx_buff_hi_threshold_per_tc);
1182}
1183
1184void tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1185 u32 tx_buff_lo_threshold_per_tc,
1186 u32 buffer)
1187{
1188 aq_hw_write_reg_bit(aq_hw, tpb_txblo_thresh_adr(buffer),
1189 tpb_txblo_thresh_msk, tpb_txblo_thresh_shift,
1190 tx_buff_lo_threshold_per_tc);
1191}
1192
1193void tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
1194{
1195 aq_hw_write_reg_bit(aq_hw, tpb_dma_sys_lbk_adr,
1196 tpb_dma_sys_lbk_msk,
1197 tpb_dma_sys_lbk_shift,
1198 tx_dma_sys_lbk_en);
1199}
1200
1201void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1202 u32 tx_pkt_buff_size_per_tc, u32 buffer)
1203{
1204 aq_hw_write_reg_bit(aq_hw, tpb_txbbuf_size_adr(buffer),
1205 tpb_txbbuf_size_msk,
1206 tpb_txbbuf_size_shift,
1207 tx_pkt_buff_size_per_tc);
1208}
1209
1210void tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
1211{
1212 aq_hw_write_reg_bit(aq_hw, tpb_tx_scp_ins_en_adr,
1213 tpb_tx_scp_ins_en_msk,
1214 tpb_tx_scp_ins_en_shift,
1215 tx_path_scp_ins_en);
1216}
1217
1218
1219void tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1220 u32 ipv4header_crc_offload_en)
1221{
1222 aq_hw_write_reg_bit(aq_hw, tpo_ipv4chk_en_adr,
1223 tpo_ipv4chk_en_msk,
1224 tpo_ipv4chk_en_shift,
1225 ipv4header_crc_offload_en);
1226}
1227
1228void tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1229 u32 tcp_udp_crc_offload_en)
1230{
1231 aq_hw_write_reg_bit(aq_hw, tpol4chk_en_adr,
1232 tpol4chk_en_msk,
1233 tpol4chk_en_shift,
1234 tcp_udp_crc_offload_en);
1235}
1236
1237void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_pkt_sys_lbk_en)
1238{
1239 aq_hw_write_reg_bit(aq_hw, tpo_pkt_sys_lbk_adr,
1240 tpo_pkt_sys_lbk_msk,
1241 tpo_pkt_sys_lbk_shift,
1242 tx_pkt_sys_lbk_en);
1243}
1244
1245
1246void tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
1247 u32 tx_pkt_shed_data_arb_mode)
1248{
1249 aq_hw_write_reg_bit(aq_hw, tps_data_tc_arb_mode_adr,
1250 tps_data_tc_arb_mode_msk,
1251 tps_data_tc_arb_mode_shift,
1252 tx_pkt_shed_data_arb_mode);
1253}
1254
1255void tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
1256 u32 curr_time_res)
1257{
1258 aq_hw_write_reg_bit(aq_hw, tps_desc_rate_ta_rst_adr,
1259 tps_desc_rate_ta_rst_msk,
1260 tps_desc_rate_ta_rst_shift,
1261 curr_time_res);
1262}
1263
1264void tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
1265 u32 tx_pkt_shed_desc_rate_lim)
1266{
1267 aq_hw_write_reg_bit(aq_hw, tps_desc_rate_lim_adr,
1268 tps_desc_rate_lim_msk,
1269 tps_desc_rate_lim_shift,
1270 tx_pkt_shed_desc_rate_lim);
1271}
1272
1273void tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
1274 u32 tx_pkt_shed_desc_tc_arb_mode)
1275{
1276 aq_hw_write_reg_bit(aq_hw, tps_desc_tc_arb_mode_adr,
1277 tps_desc_tc_arb_mode_msk,
1278 tps_desc_tc_arb_mode_shift,
1279 tx_pkt_shed_desc_tc_arb_mode);
1280}
1281
1282void tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1283 u32 tx_pkt_shed_desc_tc_max_credit,
1284 u32 tc)
1285{
1286 aq_hw_write_reg_bit(aq_hw, tps_desc_tctcredit_max_adr(tc),
1287 tps_desc_tctcredit_max_msk,
1288 tps_desc_tctcredit_max_shift,
1289 tx_pkt_shed_desc_tc_max_credit);
1290}
1291
1292void tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1293 u32 tx_pkt_shed_desc_tc_weight, u32 tc)
1294{
1295 aq_hw_write_reg_bit(aq_hw, tps_desc_tctweight_adr(tc),
1296 tps_desc_tctweight_msk,
1297 tps_desc_tctweight_shift,
1298 tx_pkt_shed_desc_tc_weight);
1299}
1300
1301void tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
1302 u32 tx_pkt_shed_desc_vm_arb_mode)
1303{
1304 aq_hw_write_reg_bit(aq_hw, tps_desc_vm_arb_mode_adr,
1305 tps_desc_vm_arb_mode_msk,
1306 tps_desc_vm_arb_mode_shift,
1307 tx_pkt_shed_desc_vm_arb_mode);
1308}
1309
1310void tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1311 u32 tx_pkt_shed_tc_data_max_credit,
1312 u32 tc)
1313{
1314 aq_hw_write_reg_bit(aq_hw, tps_data_tctcredit_max_adr(tc),
1315 tps_data_tctcredit_max_msk,
1316 tps_data_tctcredit_max_shift,
1317 tx_pkt_shed_tc_data_max_credit);
1318}
1319
1320void tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1321 u32 tx_pkt_shed_tc_data_weight, u32 tc)
1322{
1323 aq_hw_write_reg_bit(aq_hw, tps_data_tctweight_adr(tc),
1324 tps_data_tctweight_msk,
1325 tps_data_tctweight_shift,
1326 tx_pkt_shed_tc_data_weight);
1327}
1328
1329
1330void tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
1331{
1332 aq_hw_write_reg_bit(aq_hw, tx_reg_res_dsbl_adr,
1333 tx_reg_res_dsbl_msk,
1334 tx_reg_res_dsbl_shift, tx_reg_res_dis);
1335}
1336
1337
1338u32 msm_reg_access_status_get(struct aq_hw_s *aq_hw)
1339{
1340 return aq_hw_read_reg_bit(aq_hw, msm_reg_access_busy_adr,
1341 msm_reg_access_busy_msk,
1342 msm_reg_access_busy_shift);
1343}
1344
1345void msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
1346 u32 reg_addr_for_indirect_addr)
1347{
1348 aq_hw_write_reg_bit(aq_hw, msm_reg_addr_adr,
1349 msm_reg_addr_msk,
1350 msm_reg_addr_shift,
1351 reg_addr_for_indirect_addr);
1352}
1353
1354void msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
1355{
1356 aq_hw_write_reg_bit(aq_hw, msm_reg_rd_strobe_adr,
1357 msm_reg_rd_strobe_msk,
1358 msm_reg_rd_strobe_shift,
1359 reg_rd_strobe);
1360}
1361
1362u32 msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
1363{
1364 return aq_hw_read_reg(aq_hw, msm_reg_rd_data_adr);
1365}
1366
1367void msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
1368{
1369 aq_hw_write_reg(aq_hw, msm_reg_wr_data_adr, reg_wr_data);
1370}
1371
1372void msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
1373{
1374 aq_hw_write_reg_bit(aq_hw, msm_reg_wr_strobe_adr,
1375 msm_reg_wr_strobe_msk,
1376 msm_reg_wr_strobe_shift,
1377 reg_wr_strobe);
1378}
1379
1380
1381void pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
1382{
1383 aq_hw_write_reg_bit(aq_hw, pci_reg_res_dsbl_adr,
1384 pci_reg_res_dsbl_msk,
1385 pci_reg_res_dsbl_shift,
1386 pci_reg_res_dis);
1387}
1388
1389void reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, u32 glb_cpu_scratch_scp,
1390 u32 scratch_scp)
1391{
1392 aq_hw_write_reg(aq_hw, glb_cpu_scratch_scp_adr(scratch_scp),
1393 glb_cpu_scratch_scp);
1394}
1395