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10#ifndef __HCLGE_MAIN_H
11#define __HCLGE_MAIN_H
12#include <linux/fs.h>
13#include <linux/types.h>
14#include <linux/phy.h>
15#include "hclge_cmd.h"
16#include "hnae3.h"
17
18#define HCLGE_MOD_VERSION "v1.0"
19#define HCLGE_DRIVER_NAME "hclge"
20
21#define HCLGE_INVALID_VPORT 0xffff
22
23#define HCLGE_ROCE_VECTOR_OFFSET 96
24
25#define HCLGE_PF_CFG_BLOCK_SIZE 32
26#define HCLGE_PF_CFG_DESC_NUM \
27 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
28
29#define HCLGE_VECTOR_REG_BASE 0x20000
30#define HCLGE_MISC_VECTOR_REG_BASE 0x20400
31
32#define HCLGE_VECTOR_REG_OFFSET 0x4
33#define HCLGE_VECTOR_VF_OFFSET 0x100000
34
35#define HCLGE_RSS_IND_TBL_SIZE 512
36#define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
37#define HCLGE_RSS_KEY_SIZE 40
38#define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0
39#define HCLGE_RSS_HASH_ALGO_SIMPLE 1
40#define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2
41#define HCLGE_RSS_HASH_ALGO_MASK 0xf
42#define HCLGE_RSS_CFG_TBL_NUM \
43 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
44
45#define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
46#define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
47#define HCLGE_D_PORT_BIT BIT(0)
48#define HCLGE_S_PORT_BIT BIT(1)
49#define HCLGE_D_IP_BIT BIT(2)
50#define HCLGE_S_IP_BIT BIT(3)
51#define HCLGE_V_TAG_BIT BIT(4)
52
53#define HCLGE_RSS_TC_SIZE_0 1
54#define HCLGE_RSS_TC_SIZE_1 2
55#define HCLGE_RSS_TC_SIZE_2 4
56#define HCLGE_RSS_TC_SIZE_3 8
57#define HCLGE_RSS_TC_SIZE_4 16
58#define HCLGE_RSS_TC_SIZE_5 32
59#define HCLGE_RSS_TC_SIZE_6 64
60#define HCLGE_RSS_TC_SIZE_7 128
61
62#define HCLGE_TQP_RESET_TRY_TIMES 10
63
64#define HCLGE_PHY_PAGE_MDIX 0
65#define HCLGE_PHY_PAGE_COPPER 0
66
67
68#define HCLGE_PHY_PAGE_REG 22
69
70
71#define HCLGE_PHY_CSC_REG 16
72
73
74#define HCLGE_PHY_CSS_REG 17
75
76#define HCLGE_PHY_MDIX_CTRL_S (5)
77#define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
78
79#define HCLGE_PHY_MDIX_STATUS_B (6)
80#define HCLGE_PHY_SPEED_DUP_RESOLVE_B (11)
81
82
83#define HCLGE_MISC_RESET_STS_REG 0x20700
84#define HCLGE_GLOBAL_RESET_REG 0x20A00
85#define HCLGE_GLOBAL_RESET_BIT 0x0
86#define HCLGE_CORE_RESET_BIT 0x1
87#define HCLGE_FUN_RST_ING 0x20C00
88#define HCLGE_FUN_RST_ING_B 0
89
90
91#define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
92#define HCLGE_VECTOR0_CORERESET_INT_B 6
93#define HCLGE_VECTOR0_IMPRESET_INT_B 7
94
95enum HCLGE_DEV_STATE {
96 HCLGE_STATE_REINITING,
97 HCLGE_STATE_DOWN,
98 HCLGE_STATE_DISABLED,
99 HCLGE_STATE_REMOVING,
100 HCLGE_STATE_SERVICE_INITED,
101 HCLGE_STATE_SERVICE_SCHED,
102 HCLGE_STATE_MBX_HANDLING,
103 HCLGE_STATE_MBX_IRQ,
104 HCLGE_STATE_RESET_INT,
105 HCLGE_STATE_MAX
106};
107
108#define HCLGE_MPF_ENBALE 1
109struct hclge_caps {
110 u16 num_tqp;
111 u16 num_buffer_cell;
112 u32 flag;
113 u16 vmdq;
114};
115
116enum HCLGE_MAC_SPEED {
117 HCLGE_MAC_SPEED_10M = 10,
118 HCLGE_MAC_SPEED_100M = 100,
119 HCLGE_MAC_SPEED_1G = 1000,
120 HCLGE_MAC_SPEED_10G = 10000,
121 HCLGE_MAC_SPEED_25G = 25000,
122 HCLGE_MAC_SPEED_40G = 40000,
123 HCLGE_MAC_SPEED_50G = 50000,
124 HCLGE_MAC_SPEED_100G = 100000
125};
126
127enum HCLGE_MAC_DUPLEX {
128 HCLGE_MAC_HALF,
129 HCLGE_MAC_FULL
130};
131
132enum hclge_mta_dmac_sel_type {
133 HCLGE_MAC_ADDR_47_36,
134 HCLGE_MAC_ADDR_46_35,
135 HCLGE_MAC_ADDR_45_34,
136 HCLGE_MAC_ADDR_44_33,
137};
138
139struct hclge_mac {
140 u8 phy_addr;
141 u8 flag;
142 u8 media_type;
143 u8 mac_addr[ETH_ALEN];
144 u8 autoneg;
145 u8 duplex;
146 u32 speed;
147 int link;
148 struct phy_device *phydev;
149 struct mii_bus *mdio_bus;
150 phy_interface_t phy_if;
151};
152
153struct hclge_hw {
154 void __iomem *io_base;
155 struct hclge_mac mac;
156 int num_vec;
157 struct hclge_cmq cmq;
158 struct hclge_caps caps;
159 void *back;
160};
161
162
163struct hlcge_tqp_stats {
164
165 u64 rcb_tx_ring_pktnum_rcd;
166
167 u64 rcb_rx_ring_pktnum_rcd;
168};
169
170struct hclge_tqp {
171 struct device *dev;
172 struct hnae3_queue q;
173 struct hlcge_tqp_stats tqp_stats;
174 u16 index;
175
176 bool alloced;
177};
178
179enum hclge_fc_mode {
180 HCLGE_FC_NONE,
181 HCLGE_FC_RX_PAUSE,
182 HCLGE_FC_TX_PAUSE,
183 HCLGE_FC_FULL,
184 HCLGE_FC_PFC,
185 HCLGE_FC_DEFAULT
186};
187
188#define HCLGE_PG_NUM 4
189#define HCLGE_SCH_MODE_SP 0
190#define HCLGE_SCH_MODE_DWRR 1
191struct hclge_pg_info {
192 u8 pg_id;
193 u8 pg_sch_mode;
194 u8 tc_bit_map;
195 u32 bw_limit;
196 u8 tc_dwrr[HNAE3_MAX_TC];
197};
198
199struct hclge_tc_info {
200 u8 tc_id;
201 u8 tc_sch_mode;
202 u8 pgid;
203 u32 bw_limit;
204};
205
206struct hclge_cfg {
207 u8 vmdq_vport_num;
208 u8 tc_num;
209 u16 tqp_desc_num;
210 u16 rx_buf_len;
211 u8 phy_addr;
212 u8 media_type;
213 u8 mac_addr[ETH_ALEN];
214 u8 default_speed;
215 u32 numa_node_map;
216};
217
218struct hclge_tm_info {
219 u8 num_tc;
220 u8 num_pg;
221 u8 pg_dwrr[HCLGE_PG_NUM];
222 u8 prio_tc[HNAE3_MAX_USER_PRIO];
223 struct hclge_pg_info pg_info[HCLGE_PG_NUM];
224 struct hclge_tc_info tc_info[HNAE3_MAX_TC];
225 enum hclge_fc_mode fc_mode;
226 u8 hw_pfc_map;
227};
228
229struct hclge_comm_stats_str {
230 char desc[ETH_GSTRING_LEN];
231 unsigned long offset;
232};
233
234
235struct hclge_64_bit_stats {
236
237 u64 igu_rx_oversize_pkt;
238 u64 igu_rx_undersize_pkt;
239 u64 igu_rx_out_all_pkt;
240 u64 igu_rx_uni_pkt;
241 u64 igu_rx_multi_pkt;
242 u64 igu_rx_broad_pkt;
243 u64 rsv0;
244
245
246 u64 egu_tx_out_all_pkt;
247 u64 egu_tx_uni_pkt;
248 u64 egu_tx_multi_pkt;
249 u64 egu_tx_broad_pkt;
250
251
252 u64 ssu_ppp_mac_key_num;
253 u64 ssu_ppp_host_key_num;
254 u64 ppp_ssu_mac_rlt_num;
255 u64 ppp_ssu_host_rlt_num;
256
257
258 u64 ssu_tx_in_num;
259 u64 ssu_tx_out_num;
260
261 u64 ssu_rx_in_num;
262 u64 ssu_rx_out_num;
263};
264
265
266struct hclge_32_bit_stats {
267 u64 igu_rx_err_pkt;
268 u64 igu_rx_no_eof_pkt;
269 u64 igu_rx_no_sof_pkt;
270 u64 egu_tx_1588_pkt;
271 u64 egu_tx_err_pkt;
272 u64 ssu_full_drop_num;
273 u64 ssu_part_drop_num;
274 u64 ppp_key_drop_num;
275 u64 ppp_rlt_drop_num;
276 u64 ssu_key_drop_num;
277 u64 pkt_curr_buf_cnt;
278 u64 qcn_fb_rcv_cnt;
279 u64 qcn_fb_drop_cnt;
280 u64 qcn_fb_invaild_cnt;
281 u64 rsv0;
282 u64 rx_packet_tc0_in_cnt;
283 u64 rx_packet_tc1_in_cnt;
284 u64 rx_packet_tc2_in_cnt;
285 u64 rx_packet_tc3_in_cnt;
286 u64 rx_packet_tc4_in_cnt;
287 u64 rx_packet_tc5_in_cnt;
288 u64 rx_packet_tc6_in_cnt;
289 u64 rx_packet_tc7_in_cnt;
290 u64 rx_packet_tc0_out_cnt;
291 u64 rx_packet_tc1_out_cnt;
292 u64 rx_packet_tc2_out_cnt;
293 u64 rx_packet_tc3_out_cnt;
294 u64 rx_packet_tc4_out_cnt;
295 u64 rx_packet_tc5_out_cnt;
296 u64 rx_packet_tc6_out_cnt;
297 u64 rx_packet_tc7_out_cnt;
298
299
300 u64 tx_packet_tc0_in_cnt;
301 u64 tx_packet_tc1_in_cnt;
302 u64 tx_packet_tc2_in_cnt;
303 u64 tx_packet_tc3_in_cnt;
304 u64 tx_packet_tc4_in_cnt;
305 u64 tx_packet_tc5_in_cnt;
306 u64 tx_packet_tc6_in_cnt;
307 u64 tx_packet_tc7_in_cnt;
308 u64 tx_packet_tc0_out_cnt;
309 u64 tx_packet_tc1_out_cnt;
310 u64 tx_packet_tc2_out_cnt;
311 u64 tx_packet_tc3_out_cnt;
312 u64 tx_packet_tc4_out_cnt;
313 u64 tx_packet_tc5_out_cnt;
314 u64 tx_packet_tc6_out_cnt;
315 u64 tx_packet_tc7_out_cnt;
316
317
318 u64 pkt_curr_buf_tc0_cnt;
319 u64 pkt_curr_buf_tc1_cnt;
320 u64 pkt_curr_buf_tc2_cnt;
321 u64 pkt_curr_buf_tc3_cnt;
322 u64 pkt_curr_buf_tc4_cnt;
323 u64 pkt_curr_buf_tc5_cnt;
324 u64 pkt_curr_buf_tc6_cnt;
325 u64 pkt_curr_buf_tc7_cnt;
326
327 u64 mb_uncopy_num;
328 u64 lo_pri_unicast_rlt_drop_num;
329 u64 hi_pri_multicast_rlt_drop_num;
330 u64 lo_pri_multicast_rlt_drop_num;
331 u64 rx_oq_drop_pkt_cnt;
332 u64 tx_oq_drop_pkt_cnt;
333 u64 nic_l2_err_drop_pkt_cnt;
334 u64 roc_l2_err_drop_pkt_cnt;
335};
336
337
338struct hclge_mac_stats {
339 u64 mac_tx_mac_pause_num;
340 u64 mac_rx_mac_pause_num;
341 u64 mac_tx_pfc_pri0_pkt_num;
342 u64 mac_tx_pfc_pri1_pkt_num;
343 u64 mac_tx_pfc_pri2_pkt_num;
344 u64 mac_tx_pfc_pri3_pkt_num;
345 u64 mac_tx_pfc_pri4_pkt_num;
346 u64 mac_tx_pfc_pri5_pkt_num;
347 u64 mac_tx_pfc_pri6_pkt_num;
348 u64 mac_tx_pfc_pri7_pkt_num;
349 u64 mac_rx_pfc_pri0_pkt_num;
350 u64 mac_rx_pfc_pri1_pkt_num;
351 u64 mac_rx_pfc_pri2_pkt_num;
352 u64 mac_rx_pfc_pri3_pkt_num;
353 u64 mac_rx_pfc_pri4_pkt_num;
354 u64 mac_rx_pfc_pri5_pkt_num;
355 u64 mac_rx_pfc_pri6_pkt_num;
356 u64 mac_rx_pfc_pri7_pkt_num;
357 u64 mac_tx_total_pkt_num;
358 u64 mac_tx_total_oct_num;
359 u64 mac_tx_good_pkt_num;
360 u64 mac_tx_bad_pkt_num;
361 u64 mac_tx_good_oct_num;
362 u64 mac_tx_bad_oct_num;
363 u64 mac_tx_uni_pkt_num;
364 u64 mac_tx_multi_pkt_num;
365 u64 mac_tx_broad_pkt_num;
366 u64 mac_tx_undersize_pkt_num;
367 u64 mac_tx_overrsize_pkt_num;
368 u64 mac_tx_64_oct_pkt_num;
369 u64 mac_tx_65_127_oct_pkt_num;
370 u64 mac_tx_128_255_oct_pkt_num;
371 u64 mac_tx_256_511_oct_pkt_num;
372 u64 mac_tx_512_1023_oct_pkt_num;
373 u64 mac_tx_1024_1518_oct_pkt_num;
374 u64 mac_tx_1519_max_oct_pkt_num;
375 u64 mac_rx_total_pkt_num;
376 u64 mac_rx_total_oct_num;
377 u64 mac_rx_good_pkt_num;
378 u64 mac_rx_bad_pkt_num;
379 u64 mac_rx_good_oct_num;
380 u64 mac_rx_bad_oct_num;
381 u64 mac_rx_uni_pkt_num;
382 u64 mac_rx_multi_pkt_num;
383 u64 mac_rx_broad_pkt_num;
384 u64 mac_rx_undersize_pkt_num;
385 u64 mac_rx_overrsize_pkt_num;
386 u64 mac_rx_64_oct_pkt_num;
387 u64 mac_rx_65_127_oct_pkt_num;
388 u64 mac_rx_128_255_oct_pkt_num;
389 u64 mac_rx_256_511_oct_pkt_num;
390 u64 mac_rx_512_1023_oct_pkt_num;
391 u64 mac_rx_1024_1518_oct_pkt_num;
392 u64 mac_rx_1519_max_oct_pkt_num;
393
394 u64 mac_trans_fragment_pkt_num;
395 u64 mac_trans_undermin_pkt_num;
396 u64 mac_trans_jabber_pkt_num;
397 u64 mac_trans_err_all_pkt_num;
398 u64 mac_trans_from_app_good_pkt_num;
399 u64 mac_trans_from_app_bad_pkt_num;
400 u64 mac_rcv_fragment_pkt_num;
401 u64 mac_rcv_undermin_pkt_num;
402 u64 mac_rcv_jabber_pkt_num;
403 u64 mac_rcv_fcs_err_pkt_num;
404 u64 mac_rcv_send_app_good_pkt_num;
405 u64 mac_rcv_send_app_bad_pkt_num;
406};
407
408struct hclge_hw_stats {
409 struct hclge_mac_stats mac_stats;
410 struct hclge_64_bit_stats all_64_bit_stats;
411 struct hclge_32_bit_stats all_32_bit_stats;
412};
413
414struct hclge_dev {
415 struct pci_dev *pdev;
416 struct hnae3_ae_dev *ae_dev;
417 struct hclge_hw hw;
418 struct hclge_misc_vector misc_vector;
419 struct hclge_hw_stats hw_stats;
420 unsigned long state;
421
422 enum hnae3_reset_type reset_type;
423 u32 fw_version;
424 u16 num_vmdq_vport;
425 u16 num_tqps;
426 u16 num_req_vfs;
427
428
429 u16 base_tqp_pid;
430 u16 alloc_rss_size;
431 u16 rss_size_max;
432
433
434 u16 fdir_pf_filter_count;
435 u16 num_alloc_vport;
436 u32 numa_node_mask;
437 u16 rx_buf_len;
438 u16 num_desc;
439 u8 hw_tc_map;
440 u8 tc_num_last_time;
441 enum hclge_fc_mode fc_mode_last_time;
442
443#define HCLGE_FLAG_TC_BASE_SCH_MODE 1
444#define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
445 u8 tx_sch_mode;
446 u8 tc_max;
447 u8 pfc_max;
448
449 u8 default_up;
450 u8 dcbx_cap;
451 struct hclge_tm_info tm_info;
452
453 u16 num_msi;
454 u16 num_msi_left;
455 u16 num_msi_used;
456 u32 base_msi_vector;
457 u16 *vector_status;
458 int *vector_irq;
459 u16 num_roce_msi;
460 int roce_base_vector;
461
462 u16 pending_udp_bitmap;
463
464 u16 rx_itr_default;
465 u16 tx_itr_default;
466
467 u16 adminq_work_limit;
468 unsigned long service_timer_period;
469 unsigned long service_timer_previous;
470 struct timer_list service_timer;
471 struct work_struct service_task;
472
473 bool cur_promisc;
474 int num_alloc_vfs;
475
476 struct hclge_tqp *htqp;
477 struct hclge_vport *vport;
478
479 struct dentry *hclge_dbgfs;
480
481 struct hnae3_client *nic_client;
482 struct hnae3_client *roce_client;
483
484#define HCLGE_FLAG_MAIN BIT(0)
485#define HCLGE_FLAG_DCB_CAPABLE BIT(1)
486#define HCLGE_FLAG_DCB_ENABLE BIT(2)
487#define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
488 u32 flag;
489
490 u32 pkt_buf_size;
491 u32 mps;
492
493 enum hclge_mta_dmac_sel_type mta_mac_sel_type;
494 bool enable_mta;
495 bool accept_mta_mc;
496};
497
498struct hclge_vport {
499 u16 alloc_tqps;
500
501 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE];
502
503 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
504 u16 alloc_rss_size;
505
506 u16 qs_offset;
507 u16 bw_limit;
508 u8 dwrr;
509
510 int vport_id;
511 struct hclge_dev *back;
512 struct hnae3_handle nic;
513 struct hnae3_handle roce;
514};
515
516void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
517 bool en_mc, bool en_bc, int vport_id);
518
519int hclge_add_uc_addr_common(struct hclge_vport *vport,
520 const unsigned char *addr);
521int hclge_rm_uc_addr_common(struct hclge_vport *vport,
522 const unsigned char *addr);
523int hclge_add_mc_addr_common(struct hclge_vport *vport,
524 const unsigned char *addr);
525int hclge_rm_mc_addr_common(struct hclge_vport *vport,
526 const unsigned char *addr);
527
528int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
529 u8 func_id,
530 bool enable);
531struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
532int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector,
533 struct hnae3_ring_chain_node *ring_chain);
534static inline int hclge_get_queue_id(struct hnae3_queue *queue)
535{
536 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
537
538 return tqp->index;
539}
540
541int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
542int hclge_set_vf_vlan_common(struct hclge_dev *vport, int vfid,
543 bool is_kill, u16 vlan, u8 qos, __be16 proto);
544
545int hclge_buffer_alloc(struct hclge_dev *hdev);
546int hclge_rss_init_hw(struct hclge_dev *hdev);
547#endif
548
