1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22#include "e1000.h"
23
24
25
26
27
28
29
30
31static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
32{
33 *eecd = *eecd | E1000_EECD_SK;
34 ew32(EECD, *eecd);
35 e1e_flush();
36 udelay(hw->nvm.delay_usec);
37}
38
39
40
41
42
43
44
45
46static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
47{
48 *eecd = *eecd & ~E1000_EECD_SK;
49 ew32(EECD, *eecd);
50 e1e_flush();
51 udelay(hw->nvm.delay_usec);
52}
53
54
55
56
57
58
59
60
61
62
63
64static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
65{
66 struct e1000_nvm_info *nvm = &hw->nvm;
67 u32 eecd = er32(EECD);
68 u32 mask;
69
70 mask = BIT(count - 1);
71 if (nvm->type == e1000_nvm_eeprom_spi)
72 eecd |= E1000_EECD_DO;
73
74 do {
75 eecd &= ~E1000_EECD_DI;
76
77 if (data & mask)
78 eecd |= E1000_EECD_DI;
79
80 ew32(EECD, eecd);
81 e1e_flush();
82
83 udelay(nvm->delay_usec);
84
85 e1000_raise_eec_clk(hw, &eecd);
86 e1000_lower_eec_clk(hw, &eecd);
87
88 mask >>= 1;
89 } while (mask);
90
91 eecd &= ~E1000_EECD_DI;
92 ew32(EECD, eecd);
93}
94
95
96
97
98
99
100
101
102
103
104
105
106static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
107{
108 u32 eecd;
109 u32 i;
110 u16 data;
111
112 eecd = er32(EECD);
113 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
114 data = 0;
115
116 for (i = 0; i < count; i++) {
117 data <<= 1;
118 e1000_raise_eec_clk(hw, &eecd);
119
120 eecd = er32(EECD);
121
122 eecd &= ~E1000_EECD_DI;
123 if (eecd & E1000_EECD_DO)
124 data |= 1;
125
126 e1000_lower_eec_clk(hw, &eecd);
127 }
128
129 return data;
130}
131
132
133
134
135
136
137
138
139
140s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
141{
142 u32 attempts = 100000;
143 u32 i, reg = 0;
144
145 for (i = 0; i < attempts; i++) {
146 if (ee_reg == E1000_NVM_POLL_READ)
147 reg = er32(EERD);
148 else
149 reg = er32(EEWR);
150
151 if (reg & E1000_NVM_RW_REG_DONE)
152 return 0;
153
154 udelay(5);
155 }
156
157 return -E1000_ERR_NVM;
158}
159
160
161
162
163
164
165
166
167
168s32 e1000e_acquire_nvm(struct e1000_hw *hw)
169{
170 u32 eecd = er32(EECD);
171 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
172
173 ew32(EECD, eecd | E1000_EECD_REQ);
174 eecd = er32(EECD);
175
176 while (timeout) {
177 if (eecd & E1000_EECD_GNT)
178 break;
179 udelay(5);
180 eecd = er32(EECD);
181 timeout--;
182 }
183
184 if (!timeout) {
185 eecd &= ~E1000_EECD_REQ;
186 ew32(EECD, eecd);
187 e_dbg("Could not acquire NVM grant\n");
188 return -E1000_ERR_NVM;
189 }
190
191 return 0;
192}
193
194
195
196
197
198
199
200static void e1000_standby_nvm(struct e1000_hw *hw)
201{
202 struct e1000_nvm_info *nvm = &hw->nvm;
203 u32 eecd = er32(EECD);
204
205 if (nvm->type == e1000_nvm_eeprom_spi) {
206
207 eecd |= E1000_EECD_CS;
208 ew32(EECD, eecd);
209 e1e_flush();
210 udelay(nvm->delay_usec);
211 eecd &= ~E1000_EECD_CS;
212 ew32(EECD, eecd);
213 e1e_flush();
214 udelay(nvm->delay_usec);
215 }
216}
217
218
219
220
221
222
223
224static void e1000_stop_nvm(struct e1000_hw *hw)
225{
226 u32 eecd;
227
228 eecd = er32(EECD);
229 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
230
231 eecd |= E1000_EECD_CS;
232 e1000_lower_eec_clk(hw, &eecd);
233 }
234}
235
236
237
238
239
240
241
242void e1000e_release_nvm(struct e1000_hw *hw)
243{
244 u32 eecd;
245
246 e1000_stop_nvm(hw);
247
248 eecd = er32(EECD);
249 eecd &= ~E1000_EECD_REQ;
250 ew32(EECD, eecd);
251}
252
253
254
255
256
257
258
259static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
260{
261 struct e1000_nvm_info *nvm = &hw->nvm;
262 u32 eecd = er32(EECD);
263 u8 spi_stat_reg;
264
265 if (nvm->type == e1000_nvm_eeprom_spi) {
266 u16 timeout = NVM_MAX_RETRY_SPI;
267
268
269 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
270 ew32(EECD, eecd);
271 e1e_flush();
272 udelay(1);
273
274
275
276
277
278
279 while (timeout) {
280 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
281 hw->nvm.opcode_bits);
282 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
283 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
284 break;
285
286 udelay(5);
287 e1000_standby_nvm(hw);
288 timeout--;
289 }
290
291 if (!timeout) {
292 e_dbg("SPI NVM Status error\n");
293 return -E1000_ERR_NVM;
294 }
295 }
296
297 return 0;
298}
299
300
301
302
303
304
305
306
307
308
309s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
310{
311 struct e1000_nvm_info *nvm = &hw->nvm;
312 u32 i, eerd = 0;
313 s32 ret_val = 0;
314
315
316
317
318 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
319 (words == 0)) {
320 e_dbg("nvm parameter(s) out of bounds\n");
321 return -E1000_ERR_NVM;
322 }
323
324 for (i = 0; i < words; i++) {
325 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) +
326 E1000_NVM_RW_REG_START;
327
328 ew32(EERD, eerd);
329 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
330 if (ret_val) {
331 e_dbg("NVM read error: %d\n", ret_val);
332 break;
333 }
334
335 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
336 }
337
338 return ret_val;
339}
340
341
342
343
344
345
346
347
348
349
350
351
352
353s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
354{
355 struct e1000_nvm_info *nvm = &hw->nvm;
356 s32 ret_val = -E1000_ERR_NVM;
357 u16 widx = 0;
358
359
360
361
362 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
363 (words == 0)) {
364 e_dbg("nvm parameter(s) out of bounds\n");
365 return -E1000_ERR_NVM;
366 }
367
368 while (widx < words) {
369 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
370
371 ret_val = nvm->ops.acquire(hw);
372 if (ret_val)
373 return ret_val;
374
375 ret_val = e1000_ready_nvm_eeprom(hw);
376 if (ret_val) {
377 nvm->ops.release(hw);
378 return ret_val;
379 }
380
381 e1000_standby_nvm(hw);
382
383
384 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
385 nvm->opcode_bits);
386
387 e1000_standby_nvm(hw);
388
389
390
391
392 if ((nvm->address_bits == 8) && (offset >= 128))
393 write_opcode |= NVM_A8_OPCODE_SPI;
394
395
396 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
397 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
398 nvm->address_bits);
399
400
401 while (widx < words) {
402 u16 word_out = data[widx];
403
404 word_out = (word_out >> 8) | (word_out << 8);
405 e1000_shift_out_eec_bits(hw, word_out, 16);
406 widx++;
407
408 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
409 e1000_standby_nvm(hw);
410 break;
411 }
412 }
413 usleep_range(10000, 20000);
414 nvm->ops.release(hw);
415 }
416
417 return ret_val;
418}
419
420
421
422
423
424
425
426
427
428
429s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
430 u32 pba_num_size)
431{
432 s32 ret_val;
433 u16 nvm_data;
434 u16 pba_ptr;
435 u16 offset;
436 u16 length;
437
438 if (pba_num == NULL) {
439 e_dbg("PBA string buffer was null\n");
440 return -E1000_ERR_INVALID_ARGUMENT;
441 }
442
443 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
444 if (ret_val) {
445 e_dbg("NVM Read Error\n");
446 return ret_val;
447 }
448
449 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
450 if (ret_val) {
451 e_dbg("NVM Read Error\n");
452 return ret_val;
453 }
454
455
456
457
458
459 if (nvm_data != NVM_PBA_PTR_GUARD) {
460 e_dbg("NVM PBA number is not stored as string\n");
461
462
463 if (pba_num_size < E1000_PBANUM_LENGTH) {
464 e_dbg("PBA string buffer too small\n");
465 return E1000_ERR_NO_SPACE;
466 }
467
468
469 pba_num[0] = (nvm_data >> 12) & 0xF;
470 pba_num[1] = (nvm_data >> 8) & 0xF;
471 pba_num[2] = (nvm_data >> 4) & 0xF;
472 pba_num[3] = nvm_data & 0xF;
473 pba_num[4] = (pba_ptr >> 12) & 0xF;
474 pba_num[5] = (pba_ptr >> 8) & 0xF;
475 pba_num[6] = '-';
476 pba_num[7] = 0;
477 pba_num[8] = (pba_ptr >> 4) & 0xF;
478 pba_num[9] = pba_ptr & 0xF;
479
480
481 pba_num[10] = '\0';
482
483
484 for (offset = 0; offset < 10; offset++) {
485 if (pba_num[offset] < 0xA)
486 pba_num[offset] += '0';
487 else if (pba_num[offset] < 0x10)
488 pba_num[offset] += 'A' - 0xA;
489 }
490
491 return 0;
492 }
493
494 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
495 if (ret_val) {
496 e_dbg("NVM Read Error\n");
497 return ret_val;
498 }
499
500 if (length == 0xFFFF || length == 0) {
501 e_dbg("NVM PBA number section invalid length\n");
502 return -E1000_ERR_NVM_PBA_SECTION;
503 }
504
505 if (pba_num_size < (((u32)length * 2) - 1)) {
506 e_dbg("PBA string buffer too small\n");
507 return -E1000_ERR_NO_SPACE;
508 }
509
510
511 pba_ptr++;
512 length--;
513
514 for (offset = 0; offset < length; offset++) {
515 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
516 if (ret_val) {
517 e_dbg("NVM Read Error\n");
518 return ret_val;
519 }
520 pba_num[offset * 2] = (u8)(nvm_data >> 8);
521 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
522 }
523 pba_num[offset * 2] = '\0';
524
525 return 0;
526}
527
528
529
530
531
532
533
534
535
536s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
537{
538 u32 rar_high;
539 u32 rar_low;
540 u16 i;
541
542 rar_high = er32(RAH(0));
543 rar_low = er32(RAL(0));
544
545 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
546 hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8));
547
548 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
549 hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8));
550
551 for (i = 0; i < ETH_ALEN; i++)
552 hw->mac.addr[i] = hw->mac.perm_addr[i];
553
554 return 0;
555}
556
557
558
559
560
561
562
563
564s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
565{
566 s32 ret_val;
567 u16 checksum = 0;
568 u16 i, nvm_data;
569
570 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
571 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
572 if (ret_val) {
573 e_dbg("NVM Read Error\n");
574 return ret_val;
575 }
576 checksum += nvm_data;
577 }
578
579 if (checksum != (u16)NVM_SUM) {
580 e_dbg("NVM Checksum Invalid\n");
581 return -E1000_ERR_NVM;
582 }
583
584 return 0;
585}
586
587
588
589
590
591
592
593
594
595s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
596{
597 s32 ret_val;
598 u16 checksum = 0;
599 u16 i, nvm_data;
600
601 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
602 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
603 if (ret_val) {
604 e_dbg("NVM Read Error while updating checksum.\n");
605 return ret_val;
606 }
607 checksum += nvm_data;
608 }
609 checksum = (u16)NVM_SUM - checksum;
610 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
611 if (ret_val)
612 e_dbg("NVM Write Error while updating checksum.\n");
613
614 return ret_val;
615}
616
617
618
619
620
621
622
623
624void e1000e_reload_nvm_generic(struct e1000_hw *hw)
625{
626 u32 ctrl_ext;
627
628 usleep_range(10, 20);
629 ctrl_ext = er32(CTRL_EXT);
630 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
631 ew32(CTRL_EXT, ctrl_ext);
632 e1e_flush();
633}
634