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28#include "ixgbe.h"
29#include <linux/ptp_classify.h>
30#include <linux/clocksource.h>
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86
87#define IXGBE_INCVAL_10GB 0x66666666
88#define IXGBE_INCVAL_1GB 0x40000000
89#define IXGBE_INCVAL_100 0x50000000
90
91#define IXGBE_INCVAL_SHIFT_10GB 28
92#define IXGBE_INCVAL_SHIFT_1GB 24
93#define IXGBE_INCVAL_SHIFT_100 21
94
95#define IXGBE_INCVAL_SHIFT_82599 7
96#define IXGBE_INCPER_SHIFT_82599 24
97
98#define IXGBE_OVERFLOW_PERIOD (HZ * 30)
99#define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
100
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104
105#define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL
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162#define IXGBE_X550_BASE_PERIOD 0xC80000000ULL
163#define INCVALUE_MASK 0x7FFFFFFF
164#define ISGN 0x80000000
165#define MAX_TIMADJ 0x7FFFFFFF
166
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178
179static void ixgbe_ptp_setup_sdp_x540(struct ixgbe_adapter *adapter)
180{
181 struct ixgbe_hw *hw = &adapter->hw;
182 int shift = adapter->hw_cc.shift;
183 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
184 u64 ns = 0, clock_edge = 0;
185
186
187 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
188 IXGBE_WRITE_FLUSH(hw);
189
190 if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
191 return;
192
193 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
194
195
196
197
198 esdp |= IXGBE_ESDP_SDP0_DIR |
199 IXGBE_ESDP_SDP0_NATIVE;
200
201
202
203
204 tsauxc = IXGBE_TSAUXC_EN_CLK |
205 IXGBE_TSAUXC_SYNCLK |
206 IXGBE_TSAUXC_SDP0_INT;
207
208
209 clktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift);
210 clktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32);
211
212
213
214
215
216 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
217 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
218 ns = timecounter_cyc2time(&adapter->hw_tc, clock_edge);
219
220 div_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem);
221 clock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift);
222
223
224 trgttiml = (u32)clock_edge;
225 trgttimh = (u32)(clock_edge >> 32);
226
227 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
228 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
229 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
230 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
231
232 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
233 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
234
235 IXGBE_WRITE_FLUSH(hw);
236}
237
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246
247
248static u64 ixgbe_ptp_read_X550(const struct cyclecounter *hw_cc)
249{
250 struct ixgbe_adapter *adapter =
251 container_of(hw_cc, struct ixgbe_adapter, hw_cc);
252 struct ixgbe_hw *hw = &adapter->hw;
253 struct timespec64 ts;
254
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270 IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
271 ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
272 ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
273
274 return (u64)timespec64_to_ns(&ts);
275}
276
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282
283
284
285static u64 ixgbe_ptp_read_82599(const struct cyclecounter *cc)
286{
287 struct ixgbe_adapter *adapter =
288 container_of(cc, struct ixgbe_adapter, hw_cc);
289 struct ixgbe_hw *hw = &adapter->hw;
290 u64 stamp = 0;
291
292 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
293 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
294
295 return stamp;
296}
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314
315static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter,
316 struct skb_shared_hwtstamps *hwtstamp,
317 u64 timestamp)
318{
319 unsigned long flags;
320 struct timespec64 systime;
321 u64 ns;
322
323 memset(hwtstamp, 0, sizeof(*hwtstamp));
324
325 switch (adapter->hw.mac.type) {
326
327
328
329
330
331
332
333
334 case ixgbe_mac_X550:
335 case ixgbe_mac_X550EM_x:
336 case ixgbe_mac_x550em_a:
337
338
339
340
341
342 systime.tv_sec = timestamp >> 32;
343 systime.tv_nsec = timestamp & 0xFFFFFFFF;
344
345 timestamp = timespec64_to_ns(&systime);
346 break;
347 default:
348 break;
349 }
350
351 spin_lock_irqsave(&adapter->tmreg_lock, flags);
352 ns = timecounter_cyc2time(&adapter->hw_tc, timestamp);
353 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
354
355 hwtstamp->hwtstamp = ns_to_ktime(ns);
356}
357
358
359
360
361
362
363
364
365
366static int ixgbe_ptp_adjfreq_82599(struct ptp_clock_info *ptp, s32 ppb)
367{
368 struct ixgbe_adapter *adapter =
369 container_of(ptp, struct ixgbe_adapter, ptp_caps);
370 struct ixgbe_hw *hw = &adapter->hw;
371 u64 freq, incval;
372 u32 diff;
373 int neg_adj = 0;
374
375 if (ppb < 0) {
376 neg_adj = 1;
377 ppb = -ppb;
378 }
379
380 smp_mb();
381 incval = READ_ONCE(adapter->base_incval);
382
383 freq = incval;
384 freq *= ppb;
385 diff = div_u64(freq, 1000000000ULL);
386
387 incval = neg_adj ? (incval - diff) : (incval + diff);
388
389 switch (hw->mac.type) {
390 case ixgbe_mac_X540:
391 if (incval > 0xFFFFFFFFULL)
392 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
393 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, (u32)incval);
394 break;
395 case ixgbe_mac_82599EB:
396 if (incval > 0x00FFFFFFULL)
397 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
398 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
399 BIT(IXGBE_INCPER_SHIFT_82599) |
400 ((u32)incval & 0x00FFFFFFUL));
401 break;
402 default:
403 break;
404 }
405
406 return 0;
407}
408
409
410
411
412
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414
415
416
417static int ixgbe_ptp_adjfreq_X550(struct ptp_clock_info *ptp, s32 ppb)
418{
419 struct ixgbe_adapter *adapter =
420 container_of(ptp, struct ixgbe_adapter, ptp_caps);
421 struct ixgbe_hw *hw = &adapter->hw;
422 int neg_adj = 0;
423 u64 rate = IXGBE_X550_BASE_PERIOD;
424 u32 inca;
425
426 if (ppb < 0) {
427 neg_adj = 1;
428 ppb = -ppb;
429 }
430 rate *= ppb;
431 rate = div_u64(rate, 1000000000ULL);
432
433
434 if (rate >= INCVALUE_MASK)
435 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
436
437 inca = rate & INCVALUE_MASK;
438 if (neg_adj)
439 inca |= ISGN;
440
441 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, inca);
442
443 return 0;
444}
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451
452
453static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
454{
455 struct ixgbe_adapter *adapter =
456 container_of(ptp, struct ixgbe_adapter, ptp_caps);
457 unsigned long flags;
458
459 spin_lock_irqsave(&adapter->tmreg_lock, flags);
460 timecounter_adjtime(&adapter->hw_tc, delta);
461 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
462
463 if (adapter->ptp_setup_sdp)
464 adapter->ptp_setup_sdp(adapter);
465
466 return 0;
467}
468
469
470
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475
476
477static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
478{
479 struct ixgbe_adapter *adapter =
480 container_of(ptp, struct ixgbe_adapter, ptp_caps);
481 unsigned long flags;
482 u64 ns;
483
484 spin_lock_irqsave(&adapter->tmreg_lock, flags);
485 ns = timecounter_read(&adapter->hw_tc);
486 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
487
488 *ts = ns_to_timespec64(ns);
489
490 return 0;
491}
492
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497
498
499
500
501static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
502 const struct timespec64 *ts)
503{
504 struct ixgbe_adapter *adapter =
505 container_of(ptp, struct ixgbe_adapter, ptp_caps);
506 unsigned long flags;
507 u64 ns = timespec64_to_ns(ts);
508
509
510 spin_lock_irqsave(&adapter->tmreg_lock, flags);
511 timecounter_init(&adapter->hw_tc, &adapter->hw_cc, ns);
512 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
513
514 if (adapter->ptp_setup_sdp)
515 adapter->ptp_setup_sdp(adapter);
516 return 0;
517}
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527
528static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
529 struct ptp_clock_request *rq, int on)
530{
531 struct ixgbe_adapter *adapter =
532 container_of(ptp, struct ixgbe_adapter, ptp_caps);
533
534
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537
538
539
540 if (rq->type != PTP_CLK_REQ_PPS || !adapter->ptp_setup_sdp)
541 return -ENOTSUPP;
542
543 if (on)
544 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
545 else
546 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
547
548 adapter->ptp_setup_sdp(adapter);
549 return 0;
550}
551
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557
558
559void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter)
560{
561 struct ixgbe_hw *hw = &adapter->hw;
562 struct ptp_clock_event event;
563
564 event.type = PTP_CLOCK_PPS;
565
566
567
568
569
570 if (!adapter->ptp_clock)
571 return;
572
573 switch (hw->mac.type) {
574 case ixgbe_mac_X540:
575 ptp_clock_event(adapter->ptp_clock, &event);
576 break;
577 default:
578 break;
579 }
580}
581
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588
589
590void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
591{
592 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
593 IXGBE_OVERFLOW_PERIOD);
594 struct timespec64 ts;
595
596 if (timeout) {
597 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
598 adapter->last_overflow_check = jiffies;
599 }
600}
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610
611void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
612{
613 struct ixgbe_hw *hw = &adapter->hw;
614 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
615 struct ixgbe_ring *rx_ring;
616 unsigned long rx_event;
617 int n;
618
619
620
621
622 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
623 adapter->last_rx_ptp_check = jiffies;
624 return;
625 }
626
627
628 rx_event = adapter->last_rx_ptp_check;
629 for (n = 0; n < adapter->num_rx_queues; n++) {
630 rx_ring = adapter->rx_ring[n];
631 if (time_after(rx_ring->last_rx_timestamp, rx_event))
632 rx_event = rx_ring->last_rx_timestamp;
633 }
634
635
636 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
637 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
638 adapter->last_rx_ptp_check = jiffies;
639
640 adapter->rx_hwtstamp_cleared++;
641 e_warn(drv, "clearing RX Timestamp hang\n");
642 }
643}
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651
652
653static void ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter *adapter)
654{
655 struct ixgbe_hw *hw = &adapter->hw;
656
657 IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
658 if (adapter->ptp_tx_skb) {
659 dev_kfree_skb_any(adapter->ptp_tx_skb);
660 adapter->ptp_tx_skb = NULL;
661 }
662 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
663}
664
665
666
667
668
669void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter)
670{
671 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
672 IXGBE_PTP_TX_TIMEOUT);
673
674 if (!adapter->ptp_tx_skb)
675 return;
676
677 if (!test_bit(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state))
678 return;
679
680
681
682
683
684 if (timeout) {
685 cancel_work_sync(&adapter->ptp_tx_work);
686 ixgbe_ptp_clear_tx_timestamp(adapter);
687 adapter->tx_hwtstamp_timeouts++;
688 e_warn(drv, "clearing Tx timestamp hang\n");
689 }
690}
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694
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697
698
699
700static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
701{
702 struct sk_buff *skb = adapter->ptp_tx_skb;
703 struct ixgbe_hw *hw = &adapter->hw;
704 struct skb_shared_hwtstamps shhwtstamps;
705 u64 regval = 0;
706
707 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
708 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
709 ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval);
710
711
712
713
714
715
716 adapter->ptp_tx_skb = NULL;
717 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
718
719
720 skb_tstamp_tx(skb, &shhwtstamps);
721 dev_kfree_skb_any(skb);
722}
723
724
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730
731
732static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
733{
734 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
735 ptp_tx_work);
736 struct ixgbe_hw *hw = &adapter->hw;
737 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
738 IXGBE_PTP_TX_TIMEOUT);
739 u32 tsynctxctl;
740
741
742 if (!adapter->ptp_tx_skb) {
743 ixgbe_ptp_clear_tx_timestamp(adapter);
744 return;
745 }
746
747
748 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
749 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) {
750 ixgbe_ptp_tx_hwtstamp(adapter);
751 return;
752 }
753
754 if (timeout) {
755 ixgbe_ptp_clear_tx_timestamp(adapter);
756 adapter->tx_hwtstamp_timeouts++;
757 e_warn(drv, "clearing Tx Timestamp hang\n");
758 } else {
759
760 schedule_work(&adapter->ptp_tx_work);
761 }
762}
763
764
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766
767
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769
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771
772
773void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *q_vector,
774 struct sk_buff *skb)
775{
776 __le64 regval;
777
778
779 skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, ®val,
780 IXGBE_TS_HDR_LEN);
781 __pskb_trim(skb, skb->len - IXGBE_TS_HDR_LEN);
782
783
784
785
786
787
788
789 ixgbe_ptp_convert_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
790 le64_to_cpu(regval));
791}
792
793
794
795
796
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799
800
801
802void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *q_vector,
803 struct sk_buff *skb)
804{
805 struct ixgbe_adapter *adapter;
806 struct ixgbe_hw *hw;
807 u64 regval = 0;
808 u32 tsyncrxctl;
809
810
811 if (!q_vector || !q_vector->adapter)
812 return;
813
814 adapter = q_vector->adapter;
815 hw = &adapter->hw;
816
817
818
819
820
821 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
822 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
823 return;
824
825 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
826 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
827
828 ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
829}
830
831int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
832{
833 struct hwtstamp_config *config = &adapter->tstamp_config;
834
835 return copy_to_user(ifr->ifr_data, config,
836 sizeof(*config)) ? -EFAULT : 0;
837}
838
839
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844
845
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849
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863
864static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
865 struct hwtstamp_config *config)
866{
867 struct ixgbe_hw *hw = &adapter->hw;
868 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
869 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
870 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
871 bool is_l2 = false;
872 u32 regval;
873
874
875 if (config->flags)
876 return -EINVAL;
877
878 switch (config->tx_type) {
879 case HWTSTAMP_TX_OFF:
880 tsync_tx_ctl = 0;
881 case HWTSTAMP_TX_ON:
882 break;
883 default:
884 return -ERANGE;
885 }
886
887 switch (config->rx_filter) {
888 case HWTSTAMP_FILTER_NONE:
889 tsync_rx_ctl = 0;
890 tsync_rx_mtrl = 0;
891 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
892 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
893 break;
894 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
895 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
896 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
897 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
898 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
899 break;
900 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
901 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
902 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
903 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
904 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
905 break;
906 case HWTSTAMP_FILTER_PTP_V2_EVENT:
907 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
908 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
909 case HWTSTAMP_FILTER_PTP_V2_SYNC:
910 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
911 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
912 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
913 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
914 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
915 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
916 is_l2 = true;
917 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
918 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
919 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
920 break;
921 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
922 case HWTSTAMP_FILTER_NTP_ALL:
923 case HWTSTAMP_FILTER_ALL:
924
925
926
927 if (hw->mac.type >= ixgbe_mac_X550) {
928 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL;
929 config->rx_filter = HWTSTAMP_FILTER_ALL;
930 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
931 break;
932 }
933
934 default:
935
936
937
938
939
940
941 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
942 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
943 config->rx_filter = HWTSTAMP_FILTER_NONE;
944 return -ERANGE;
945 }
946
947 if (hw->mac.type == ixgbe_mac_82598EB) {
948 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
949 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
950 if (tsync_rx_ctl | tsync_tx_ctl)
951 return -ERANGE;
952 return 0;
953 }
954
955
956
957
958
959 switch (hw->mac.type) {
960 case ixgbe_mac_X550:
961 case ixgbe_mac_X550EM_x:
962 case ixgbe_mac_x550em_a:
963
964
965
966
967 if (config->rx_filter == HWTSTAMP_FILTER_NONE)
968 break;
969
970 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED |
971 IXGBE_TSYNCRXCTL_TYPE_ALL |
972 IXGBE_TSYNCRXCTL_TSIP_UT_EN;
973 config->rx_filter = HWTSTAMP_FILTER_ALL;
974 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
975 adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER;
976 is_l2 = true;
977 break;
978 default:
979 break;
980 }
981
982
983 if (is_l2)
984 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
985 (IXGBE_ETQF_FILTER_EN |
986 IXGBE_ETQF_1588 |
987 ETH_P_1588));
988 else
989 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
990
991
992 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
993 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
994 regval |= tsync_tx_ctl;
995 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
996
997
998 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
999 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
1000 regval |= tsync_rx_ctl;
1001 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
1002
1003
1004 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
1005
1006 IXGBE_WRITE_FLUSH(hw);
1007
1008
1009 ixgbe_ptp_clear_tx_timestamp(adapter);
1010 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
1011
1012 return 0;
1013}
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
1024{
1025 struct hwtstamp_config config;
1026 int err;
1027
1028 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1029 return -EFAULT;
1030
1031 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
1032 if (err)
1033 return err;
1034
1035
1036 memcpy(&adapter->tstamp_config, &config,
1037 sizeof(adapter->tstamp_config));
1038
1039 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1040 -EFAULT : 0;
1041}
1042
1043static void ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter *adapter,
1044 u32 *shift, u32 *incval)
1045{
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060 switch (adapter->link_speed) {
1061 case IXGBE_LINK_SPEED_100_FULL:
1062 *shift = IXGBE_INCVAL_SHIFT_100;
1063 *incval = IXGBE_INCVAL_100;
1064 break;
1065 case IXGBE_LINK_SPEED_1GB_FULL:
1066 *shift = IXGBE_INCVAL_SHIFT_1GB;
1067 *incval = IXGBE_INCVAL_1GB;
1068 break;
1069 case IXGBE_LINK_SPEED_10GB_FULL:
1070 default:
1071 *shift = IXGBE_INCVAL_SHIFT_10GB;
1072 *incval = IXGBE_INCVAL_10GB;
1073 break;
1074 }
1075}
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
1088{
1089 struct ixgbe_hw *hw = &adapter->hw;
1090 struct cyclecounter cc;
1091 unsigned long flags;
1092 u32 incval = 0;
1093 u32 tsauxc = 0;
1094 u32 fuse0 = 0;
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107 cc.mask = CLOCKSOURCE_MASK(64);
1108 cc.mult = 1;
1109 cc.shift = 0;
1110
1111 switch (hw->mac.type) {
1112 case ixgbe_mac_X550EM_x:
1113
1114
1115
1116
1117
1118
1119 fuse0 = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
1120 if (!(fuse0 & IXGBE_FUSES0_300MHZ)) {
1121 cc.mult = 3;
1122 cc.shift = 2;
1123 }
1124
1125 case ixgbe_mac_x550em_a:
1126 case ixgbe_mac_X550:
1127 cc.read = ixgbe_ptp_read_X550;
1128
1129
1130 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMR, 0);
1131 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1132 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1133 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
1134 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC,
1135 tsauxc & ~IXGBE_TSAUXC_DISABLE_SYSTIME);
1136 IXGBE_WRITE_REG(hw, IXGBE_TSIM, IXGBE_TSIM_TXTS);
1137 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_TIMESYNC);
1138
1139 IXGBE_WRITE_FLUSH(hw);
1140 break;
1141 case ixgbe_mac_X540:
1142 cc.read = ixgbe_ptp_read_82599;
1143
1144 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1145 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
1146 break;
1147 case ixgbe_mac_82599EB:
1148 cc.read = ixgbe_ptp_read_82599;
1149
1150 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1151 incval >>= IXGBE_INCVAL_SHIFT_82599;
1152 cc.shift -= IXGBE_INCVAL_SHIFT_82599;
1153 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
1154 BIT(IXGBE_INCPER_SHIFT_82599) | incval);
1155 break;
1156 default:
1157
1158 return;
1159 }
1160
1161
1162 WRITE_ONCE(adapter->base_incval, incval);
1163 smp_mb();
1164
1165
1166 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1167 memcpy(&adapter->hw_cc, &cc, sizeof(adapter->hw_cc));
1168 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1169}
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
1184{
1185 struct ixgbe_hw *hw = &adapter->hw;
1186 unsigned long flags;
1187
1188
1189 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1190
1191
1192 if (hw->mac.type == ixgbe_mac_82598EB)
1193 return;
1194
1195 ixgbe_ptp_start_cyclecounter(adapter);
1196
1197 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1198 timecounter_init(&adapter->hw_tc, &adapter->hw_cc,
1199 ktime_to_ns(ktime_get_real()));
1200 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1201
1202 adapter->last_overflow_check = jiffies;
1203
1204
1205
1206
1207 if (adapter->ptp_setup_sdp)
1208 adapter->ptp_setup_sdp(adapter);
1209}
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
1222{
1223 struct net_device *netdev = adapter->netdev;
1224 long err;
1225
1226
1227 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
1228 return 0;
1229
1230 switch (adapter->hw.mac.type) {
1231 case ixgbe_mac_X540:
1232 snprintf(adapter->ptp_caps.name,
1233 sizeof(adapter->ptp_caps.name),
1234 "%s", netdev->name);
1235 adapter->ptp_caps.owner = THIS_MODULE;
1236 adapter->ptp_caps.max_adj = 250000000;
1237 adapter->ptp_caps.n_alarm = 0;
1238 adapter->ptp_caps.n_ext_ts = 0;
1239 adapter->ptp_caps.n_per_out = 0;
1240 adapter->ptp_caps.pps = 1;
1241 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599;
1242 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1243 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1244 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1245 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1246 adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_x540;
1247 break;
1248 case ixgbe_mac_82599EB:
1249 snprintf(adapter->ptp_caps.name,
1250 sizeof(adapter->ptp_caps.name),
1251 "%s", netdev->name);
1252 adapter->ptp_caps.owner = THIS_MODULE;
1253 adapter->ptp_caps.max_adj = 250000000;
1254 adapter->ptp_caps.n_alarm = 0;
1255 adapter->ptp_caps.n_ext_ts = 0;
1256 adapter->ptp_caps.n_per_out = 0;
1257 adapter->ptp_caps.pps = 0;
1258 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599;
1259 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1260 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1261 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1262 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1263 break;
1264 case ixgbe_mac_X550:
1265 case ixgbe_mac_X550EM_x:
1266 case ixgbe_mac_x550em_a:
1267 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
1268 adapter->ptp_caps.owner = THIS_MODULE;
1269 adapter->ptp_caps.max_adj = 30000000;
1270 adapter->ptp_caps.n_alarm = 0;
1271 adapter->ptp_caps.n_ext_ts = 0;
1272 adapter->ptp_caps.n_per_out = 0;
1273 adapter->ptp_caps.pps = 0;
1274 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_X550;
1275 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1276 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1277 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1278 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1279 adapter->ptp_setup_sdp = NULL;
1280 break;
1281 default:
1282 adapter->ptp_clock = NULL;
1283 adapter->ptp_setup_sdp = NULL;
1284 return -EOPNOTSUPP;
1285 }
1286
1287 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1288 &adapter->pdev->dev);
1289 if (IS_ERR(adapter->ptp_clock)) {
1290 err = PTR_ERR(adapter->ptp_clock);
1291 adapter->ptp_clock = NULL;
1292 e_dev_err("ptp_clock_register failed\n");
1293 return err;
1294 } else if (adapter->ptp_clock)
1295 e_dev_info("registered PHC device on %s\n", netdev->name);
1296
1297
1298
1299
1300
1301 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1302 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1303
1304 return 0;
1305}
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
1316{
1317
1318
1319
1320
1321 spin_lock_init(&adapter->tmreg_lock);
1322
1323
1324 if (ixgbe_ptp_create_clock(adapter))
1325 return;
1326
1327
1328 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
1329
1330
1331 ixgbe_ptp_reset(adapter);
1332
1333
1334 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
1335
1336 return;
1337}
1338
1339
1340
1341
1342
1343
1344
1345
1346void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
1347{
1348
1349 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1350 return;
1351
1352 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
1353 if (adapter->ptp_setup_sdp)
1354 adapter->ptp_setup_sdp(adapter);
1355
1356
1357 cancel_work_sync(&adapter->ptp_tx_work);
1358 ixgbe_ptp_clear_tx_timestamp(adapter);
1359}
1360
1361
1362
1363
1364
1365
1366
1367
1368void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
1369{
1370
1371 ixgbe_ptp_suspend(adapter);
1372
1373
1374 if (adapter->ptp_clock) {
1375 ptp_clock_unregister(adapter->ptp_clock);
1376 adapter->ptp_clock = NULL;
1377 e_dev_info("removed PHC on %s\n",
1378 adapter->netdev->name);
1379 }
1380}
1381