1/******************************************************************************* 2 3 Intel 82599 Virtual Function driver 4 Copyright(c) 1999 - 2015 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#ifndef _IXGBEVF_DEFINES_H_ 28#define _IXGBEVF_DEFINES_H_ 29 30/* Device IDs */ 31#define IXGBE_DEV_ID_82599_VF 0x10ED 32#define IXGBE_DEV_ID_X540_VF 0x1515 33#define IXGBE_DEV_ID_X550_VF 0x1565 34#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 35#define IXGBE_DEV_ID_X550EM_A_VF 0x15C5 36 37#define IXGBE_DEV_ID_82599_VF_HV 0x152E 38#define IXGBE_DEV_ID_X540_VF_HV 0x1530 39#define IXGBE_DEV_ID_X550_VF_HV 0x1564 40#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9 41 42#define IXGBE_VF_IRQ_CLEAR_MASK 7 43#define IXGBE_VF_MAX_TX_QUEUES 8 44#define IXGBE_VF_MAX_RX_QUEUES 8 45 46/* DCB define */ 47#define IXGBE_VF_MAX_TRAFFIC_CLASS 8 48 49/* Link speed */ 50typedef u32 ixgbe_link_speed; 51#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 52#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 53#define IXGBE_LINK_SPEED_100_FULL 0x0008 54 55#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 56#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 57#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 58#define IXGBE_LINKS_UP 0x40000000 59#define IXGBE_LINKS_SPEED_82599 0x30000000 60#define IXGBE_LINKS_SPEED_10G_82599 0x30000000 61#define IXGBE_LINKS_SPEED_1G_82599 0x20000000 62#define IXGBE_LINKS_SPEED_100_82599 0x10000000 63 64/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 65#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 66#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 67#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 68 69/* Interrupt Vector Allocation Registers */ 70#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 71 72#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 73 74/* Receive Config masks */ 75#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 76#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 77#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 78#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 79#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ 80#define IXGBE_RXDCTL_RLPML_EN 0x00008000 81 82/* DCA Control */ 83#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */ 84 85/* PSRTYPE bit definitions */ 86#define IXGBE_PSRTYPE_TCPHDR 0x00000010 87#define IXGBE_PSRTYPE_UDPHDR 0x00000020 88#define IXGBE_PSRTYPE_IPV4HDR 0x00000100 89#define IXGBE_PSRTYPE_IPV6HDR 0x00000200 90#define IXGBE_PSRTYPE_L2HDR 0x00001000 91 92/* SRRCTL bit definitions */ 93#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 94#define IXGBE_SRRCTL_RDMTS_SHIFT 22 95#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 96#define IXGBE_SRRCTL_DROP_EN 0x10000000 97#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 98#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 99#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 100#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 101#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 102#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 103#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 104#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 105 106/* Receive Descriptor bit definitions */ 107#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 108#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 109#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 110#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 111#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 112#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 113#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 114#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 115#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 116#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 117#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 118#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 119#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 120#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 121#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 122#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 123#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 124#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 125#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 126#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 127#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 128#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 129#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 130#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 131#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 132#define IXGBE_RXDADV_ERR_MASK 0xFFF00000 /* RDESC.ERRORS mask */ 133#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 134#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 135#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 136#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 137#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 138#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 139#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 140#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 141#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 142#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 143#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 144#define IXGBE_RXD_PRI_SHIFT 13 145#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 146#define IXGBE_RXD_CFI_SHIFT 12 147 148#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 149#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 150#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 151#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 152#define IXGBE_RXDADV_STAT_MASK 0x000FFFFF /* Stat/NEXTP: bit 0-19 */ 153#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 154#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 155#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 156#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 157#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 158#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 159 160#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 161#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 162#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 163#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 164#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 165#define IXGBE_RXDADV_RSCCNT_SHIFT 17 166#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 167#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 168#define IXGBE_RXDADV_SPH 0x8000 169 170/* RSS Hash results */ 171#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 172#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 173#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 174#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 175#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 176#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 177#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 178#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 179#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 180#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 181 182#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 183 IXGBE_RXD_ERR_CE | \ 184 IXGBE_RXD_ERR_LE | \ 185 IXGBE_RXD_ERR_PE | \ 186 IXGBE_RXD_ERR_OSE | \ 187 IXGBE_RXD_ERR_USE) 188 189#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 190 IXGBE_RXDADV_ERR_CE | \ 191 IXGBE_RXDADV_ERR_LE | \ 192 IXGBE_RXDADV_ERR_PE | \ 193 IXGBE_RXDADV_ERR_OSE | \ 194 IXGBE_RXDADV_ERR_USE) 195 196#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 197#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 198#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 199#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 200#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 201#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 202#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor ext (0 = legacy) */ 203#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 204#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 205#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS) 206 207/* Transmit Descriptor - Advanced */ 208union ixgbe_adv_tx_desc { 209 struct { 210 __le64 buffer_addr; /* Address of descriptor's data buf */ 211 __le32 cmd_type_len; 212 __le32 olinfo_status; 213 } read; 214 struct { 215 __le64 rsvd; /* Reserved */ 216 __le32 nxtseq_seed; 217 __le32 status; 218 } wb; 219}; 220 221/* Receive Descriptor - Advanced */ 222union ixgbe_adv_rx_desc { 223 struct { 224 __le64 pkt_addr; /* Packet buffer address */ 225 __le64 hdr_addr; /* Header buffer address */ 226 } read; 227 struct { 228 struct { 229 union { 230 __le32 data; 231 struct { 232 __le16 pkt_info; /* RSS, Pkt type */ 233 __le16 hdr_info; /* Splithdr, hdrlen */ 234 } hs_rss; 235 } lo_dword; 236 union { 237 __le32 rss; /* RSS Hash */ 238 struct { 239 __le16 ip_id; /* IP id */ 240 __le16 csum; /* Packet Checksum */ 241 } csum_ip; 242 } hi_dword; 243 } lower; 244 struct { 245 __le32 status_error; /* ext status/error */ 246 __le16 length; /* Packet length */ 247 __le16 vlan; /* VLAN tag */ 248 } upper; 249 } wb; /* writeback */ 250}; 251 252/* Context descriptors */ 253struct ixgbe_adv_tx_context_desc { 254 __le32 vlan_macip_lens; 255 __le32 seqnum_seed; 256 __le32 type_tucmd_mlhl; 257 __le32 mss_l4len_idx; 258}; 259 260/* Adv Transmit Descriptor Config Masks */ 261#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 262#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 263#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 264#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 265#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 266#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 267#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 268#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 269#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 270#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 271#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 272#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 273#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 274#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 275#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 276#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 277#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 278#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 279#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 280 IXGBE_ADVTXD_POPTS_SHIFT) 281#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 282 IXGBE_ADVTXD_POPTS_SHIFT) 283#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 284#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 285#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 286#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 287#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 288 289/* Interrupt register bitmasks */ 290 291#define IXGBE_EITR_CNT_WDIS 0x80000000 292#define IXGBE_MAX_EITR 0x00000FF8 293#define IXGBE_MIN_EITR 8 294 295/* Error Codes */ 296#define IXGBE_ERR_INVALID_MAC_ADDR -1 297#define IXGBE_ERR_RESET_FAILED -2 298#define IXGBE_ERR_INVALID_ARGUMENT -3 299 300/* Transmit Config masks */ 301#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 302#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 303#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 304 305#define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* Rx Desc enable */ 306#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* Rx Desc header ena */ 307#define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* Rx Desc payload ena */ 308#define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* Rx rd Desc Relax Order */ 309#define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */ 310#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */ 311 312#define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ 313#define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ 314#define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */ 315#define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ 316 317#endif /* _IXGBEVF_DEFINES_H_ */ 318