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18#ifndef __DWMAC1000_H__
19#define __DWMAC1000_H__
20
21#include <linux/phy.h>
22#include "common.h"
23
24#define GMAC_CONTROL 0x00000000
25#define GMAC_FRAME_FILTER 0x00000004
26#define GMAC_HASH_HIGH 0x00000008
27#define GMAC_HASH_LOW 0x0000000c
28#define GMAC_MII_ADDR 0x00000010
29#define GMAC_MII_DATA 0x00000014
30#define GMAC_FLOW_CTRL 0x00000018
31#define GMAC_VLAN_TAG 0x0000001c
32#define GMAC_VERSION 0x00000020
33#define GMAC_DEBUG 0x00000024
34#define GMAC_WAKEUP_FILTER 0x00000028
35
36#define GMAC_INT_STATUS 0x00000038
37#define GMAC_INT_STATUS_PMT BIT(3)
38#define GMAC_INT_STATUS_MMCIS BIT(4)
39#define GMAC_INT_STATUS_MMCRIS BIT(5)
40#define GMAC_INT_STATUS_MMCTIS BIT(6)
41#define GMAC_INT_STATUS_MMCCSUM BIT(7)
42#define GMAC_INT_STATUS_TSTAMP BIT(9)
43#define GMAC_INT_STATUS_LPIIS BIT(10)
44
45
46#define GMAC_INT_MASK 0x0000003c
47#define GMAC_INT_DISABLE_RGMII BIT(0)
48#define GMAC_INT_DISABLE_PCSLINK BIT(1)
49#define GMAC_INT_DISABLE_PCSAN BIT(2)
50#define GMAC_INT_DISABLE_PMT BIT(3)
51#define GMAC_INT_DISABLE_TIMESTAMP BIT(9)
52#define GMAC_INT_DISABLE_PCS (GMAC_INT_DISABLE_RGMII | \
53 GMAC_INT_DISABLE_PCSLINK | \
54 GMAC_INT_DISABLE_PCSAN)
55#define GMAC_INT_DEFAULT_MASK (GMAC_INT_DISABLE_TIMESTAMP | \
56 GMAC_INT_DISABLE_PCS)
57
58
59#define GMAC_PMT 0x0000002c
60enum power_event {
61 pointer_reset = 0x80000000,
62 global_unicast = 0x00000200,
63 wake_up_rx_frame = 0x00000040,
64 magic_frame = 0x00000020,
65 wake_up_frame_en = 0x00000004,
66 magic_pkt_en = 0x00000002,
67 power_down = 0x00000001,
68};
69
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71
72
73
74#define LPI_CTRL_STATUS 0x0030
75#define LPI_TIMER_CTRL 0x0034
76
77
78#define LPI_CTRL_STATUS_LPITXA 0x00080000
79#define LPI_CTRL_STATUS_PLSEN 0x00040000
80#define LPI_CTRL_STATUS_PLS 0x00020000
81#define LPI_CTRL_STATUS_LPIEN 0x00010000
82#define LPI_CTRL_STATUS_RLPIST 0x00000200
83#define LPI_CTRL_STATUS_TLPIST 0x00000100
84#define LPI_CTRL_STATUS_RLPIEX 0x00000008
85#define LPI_CTRL_STATUS_RLPIEN 0x00000004
86#define LPI_CTRL_STATUS_TLPIEX 0x00000002
87#define LPI_CTRL_STATUS_TLPIEN 0x00000001
88
89
90#define GMAC_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \
91 (reg * 8))
92#define GMAC_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \
93 (reg * 8))
94#define GMAC_MAX_PERFECT_ADDRESSES 1
95
96#define GMAC_PCS_BASE 0x000000c0
97#define GMAC_RGSMIIIS 0x000000d8
98
99
100#define GMAC_RGSMIIIS_LNKMODE BIT(0)
101#define GMAC_RGSMIIIS_SPEED GENMASK(2, 1)
102#define GMAC_RGSMIIIS_SPEED_SHIFT 1
103#define GMAC_RGSMIIIS_LNKSTS BIT(3)
104#define GMAC_RGSMIIIS_JABTO BIT(4)
105#define GMAC_RGSMIIIS_FALSECARDET BIT(5)
106#define GMAC_RGSMIIIS_SMIDRXS BIT(16)
107
108#define GMAC_RGSMIIIS_LNKMOD_MASK 0x1
109
110#define GMAC_RGSMIIIS_SPEED_125 0x2
111#define GMAC_RGSMIIIS_SPEED_25 0x1
112#define GMAC_RGSMIIIS_SPEED_2_5 0x0
113
114
115#define GMAC_CONTROL_2K 0x08000000
116#define GMAC_CONTROL_TC 0x01000000
117#define GMAC_CONTROL_WD 0x00800000
118#define GMAC_CONTROL_JD 0x00400000
119#define GMAC_CONTROL_BE 0x00200000
120#define GMAC_CONTROL_JE 0x00100000
121enum inter_frame_gap {
122 GMAC_CONTROL_IFG_88 = 0x00040000,
123 GMAC_CONTROL_IFG_80 = 0x00020000,
124 GMAC_CONTROL_IFG_40 = 0x000e0000,
125};
126#define GMAC_CONTROL_DCRS 0x00010000
127#define GMAC_CONTROL_PS 0x00008000
128#define GMAC_CONTROL_FES 0x00004000
129#define GMAC_CONTROL_DO 0x00002000
130#define GMAC_CONTROL_LM 0x00001000
131#define GMAC_CONTROL_DM 0x00000800
132#define GMAC_CONTROL_IPC 0x00000400
133#define GMAC_CONTROL_DR 0x00000200
134#define GMAC_CONTROL_LUD 0x00000100
135#define GMAC_CONTROL_ACS 0x00000080
136#define GMAC_CONTROL_DC 0x00000010
137#define GMAC_CONTROL_TE 0x00000008
138#define GMAC_CONTROL_RE 0x00000004
139
140#define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \
141 GMAC_CONTROL_BE | GMAC_CONTROL_DCRS)
142
143
144#define GMAC_FRAME_FILTER_PR 0x00000001
145#define GMAC_FRAME_FILTER_HUC 0x00000002
146#define GMAC_FRAME_FILTER_HMC 0x00000004
147#define GMAC_FRAME_FILTER_DAIF 0x00000008
148#define GMAC_FRAME_FILTER_PM 0x00000010
149#define GMAC_FRAME_FILTER_DBF 0x00000020
150#define GMAC_FRAME_FILTER_SAIF 0x00000100
151#define GMAC_FRAME_FILTER_SAF 0x00000200
152#define GMAC_FRAME_FILTER_HPF 0x00000400
153#define GMAC_FRAME_FILTER_RA 0x80000000
154
155#define GMAC_MII_ADDR_WRITE 0x00000002
156#define GMAC_MII_ADDR_BUSY 0x00000001
157
158#define GMAC_FLOW_CTRL_PT_MASK 0xffff0000
159#define GMAC_FLOW_CTRL_PT_SHIFT 16
160#define GMAC_FLOW_CTRL_UP 0x00000008
161#define GMAC_FLOW_CTRL_RFE 0x00000004
162#define GMAC_FLOW_CTRL_TFE 0x00000002
163#define GMAC_FLOW_CTRL_FCB_BPA 0x00000001
164
165
166
167#define GMAC_DEBUG_TXSTSFSTS BIT(25)
168#define GMAC_DEBUG_TXFSTS BIT(24)
169#define GMAC_DEBUG_TWCSTS BIT(22)
170
171#define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20)
172#define GMAC_DEBUG_TRCSTS_SHIFT 20
173#define GMAC_DEBUG_TRCSTS_IDLE 0
174#define GMAC_DEBUG_TRCSTS_READ 1
175#define GMAC_DEBUG_TRCSTS_TXW 2
176#define GMAC_DEBUG_TRCSTS_WRITE 3
177#define GMAC_DEBUG_TXPAUSED BIT(19)
178
179#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
180#define GMAC_DEBUG_TFCSTS_SHIFT 17
181#define GMAC_DEBUG_TFCSTS_IDLE 0
182#define GMAC_DEBUG_TFCSTS_WAIT 1
183#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
184#define GMAC_DEBUG_TFCSTS_XFER 3
185
186#define GMAC_DEBUG_TPESTS BIT(16)
187#define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8)
188#define GMAC_DEBUG_RXFSTS_SHIFT 8
189#define GMAC_DEBUG_RXFSTS_EMPTY 0
190#define GMAC_DEBUG_RXFSTS_BT 1
191#define GMAC_DEBUG_RXFSTS_AT 2
192#define GMAC_DEBUG_RXFSTS_FULL 3
193#define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5)
194#define GMAC_DEBUG_RRCSTS_SHIFT 5
195#define GMAC_DEBUG_RRCSTS_IDLE 0
196#define GMAC_DEBUG_RRCSTS_RDATA 1
197#define GMAC_DEBUG_RRCSTS_RSTAT 2
198#define GMAC_DEBUG_RRCSTS_FLUSH 3
199#define GMAC_DEBUG_RWCSTS BIT(4)
200
201#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
202#define GMAC_DEBUG_RFCFCSTS_SHIFT 1
203
204#define GMAC_DEBUG_RPESTS BIT(0)
205
206
207
208#define DMA_BUS_MODE_DA 0x00000002
209#define DMA_BUS_MODE_DSL_MASK 0x0000007c
210#define DMA_BUS_MODE_DSL_SHIFT 2
211
212#define DMA_BUS_MODE_PBL_MASK 0x00003f00
213#define DMA_BUS_MODE_PBL_SHIFT 8
214#define DMA_BUS_MODE_ATDS 0x00000080
215
216enum rx_tx_priority_ratio {
217 double_ratio = 0x00004000,
218 triple_ratio = 0x00008000,
219 quadruple_ratio = 0x0000c000,
220};
221
222#define DMA_BUS_MODE_FB 0x00010000
223#define DMA_BUS_MODE_MB 0x04000000
224#define DMA_BUS_MODE_RPBL_MASK 0x007e0000
225#define DMA_BUS_MODE_RPBL_SHIFT 17
226#define DMA_BUS_MODE_USP 0x00800000
227#define DMA_BUS_MODE_MAXPBL 0x01000000
228#define DMA_BUS_MODE_AAL 0x02000000
229
230
231#define DMA_HOST_TX_DESC 0x00001048
232#define DMA_HOST_RX_DESC 0x0000104c
233
234#define DMA_BUS_PR_RATIO_MASK 0x0000c000
235#define DMA_BUS_PR_RATIO_SHIFT 14
236#define DMA_BUS_FB 0x00010000
237
238
239
240#define DMA_CONTROL_DT 0x04000000
241#define DMA_CONTROL_RSF 0x02000000
242#define DMA_CONTROL_DFF 0x01000000
243
244enum rfa {
245 act_full_minus_1 = 0x00800000,
246 act_full_minus_2 = 0x00800200,
247 act_full_minus_3 = 0x00800400,
248 act_full_minus_4 = 0x00800600,
249};
250
251enum rfd {
252 deac_full_minus_1 = 0x00400000,
253 deac_full_minus_2 = 0x00400800,
254 deac_full_minus_3 = 0x00401000,
255 deac_full_minus_4 = 0x00401800,
256};
257#define DMA_CONTROL_TSF 0x00200000
258
259enum ttc_control {
260 DMA_CONTROL_TTC_64 = 0x00000000,
261 DMA_CONTROL_TTC_128 = 0x00004000,
262 DMA_CONTROL_TTC_192 = 0x00008000,
263 DMA_CONTROL_TTC_256 = 0x0000c000,
264 DMA_CONTROL_TTC_40 = 0x00010000,
265 DMA_CONTROL_TTC_32 = 0x00014000,
266 DMA_CONTROL_TTC_24 = 0x00018000,
267 DMA_CONTROL_TTC_16 = 0x0001c000,
268};
269#define DMA_CONTROL_TC_TX_MASK 0xfffe3fff
270
271#define DMA_CONTROL_EFC 0x00000100
272#define DMA_CONTROL_FEF 0x00000080
273#define DMA_CONTROL_FUF 0x00000040
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278#define DMA_CONTROL_RFA_MASK 0x00800600
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283#define DMA_CONTROL_RFD_MASK 0x00401800
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309#define RFA_FULL_MINUS_1K 0x00000000
310#define RFA_FULL_MINUS_2K 0x00000200
311#define RFA_FULL_MINUS_3K 0x00000400
312#define RFA_FULL_MINUS_4K 0x00000600
313#define RFA_FULL_MINUS_5K 0x00800000
314#define RFA_FULL_MINUS_6K 0x00800200
315#define RFA_FULL_MINUS_7K 0x00800400
316
317#define RFD_FULL_MINUS_1K 0x00000000
318#define RFD_FULL_MINUS_2K 0x00000800
319#define RFD_FULL_MINUS_3K 0x00001000
320#define RFD_FULL_MINUS_4K 0x00001800
321#define RFD_FULL_MINUS_5K 0x00400000
322#define RFD_FULL_MINUS_6K 0x00400800
323#define RFD_FULL_MINUS_7K 0x00401000
324
325enum rtc_control {
326 DMA_CONTROL_RTC_64 = 0x00000000,
327 DMA_CONTROL_RTC_32 = 0x00000008,
328 DMA_CONTROL_RTC_96 = 0x00000010,
329 DMA_CONTROL_RTC_128 = 0x00000018,
330};
331#define DMA_CONTROL_TC_RX_MASK 0xffffffe7
332
333#define DMA_CONTROL_OSF 0x00000004
334
335
336#define GMAC_MMC_CTRL 0x100
337#define GMAC_MMC_RX_INTR 0x104
338#define GMAC_MMC_TX_INTR 0x108
339#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
340#define GMAC_EXTHASH_BASE 0x500
341
342extern const struct stmmac_dma_ops dwmac1000_dma_ops;
343#endif
344