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26#ifndef __HD64572_H
27#define __HD64572_H
28
29
30#define ILAR 0x00
31
32
33#define PABR0L 0x20
34#define PABR0H 0x21
35#define PABR1L 0x22
36#define PABR1H 0x23
37#define WCRL 0x24
38#define WCRM 0x25
39#define WCRH 0x26
40
41
42#define IVR 0x60
43#define IMVR 0x64
44#define ITCR 0x68
45#define ISR0 0x6c
46#define ISR1 0x70
47#define IER0 0x74
48#define IER1 0x78
49
50
51#define M_REG(reg, chan) (reg + 0x80*chan)
52#define DRX_REG(reg, chan) (reg + 0x40*chan)
53#define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1))
54#define TRX_REG(reg, chan) (reg + 0x20*chan)
55#define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1))
56#define ST_REG(reg, chan) (reg + 0x80*chan)
57#define IR0_DRX(val, chan) ((val)<<(8*(chan)))
58#define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1)))
59#define IR0_M(val, chan) ((val)<<(8*(chan)))
60
61
62#define MSCI0_OFFSET 0x00
63#define MSCI1_OFFSET 0x80
64
65#define MD0 0x138
66#define MD1 0x139
67#define MD2 0x13a
68#define MD3 0x13b
69#define CTL 0x130
70#define RXS 0x13c
71#define TXS 0x13d
72#define EXS 0x13e
73#define TMCT 0x144
74#define TMCR 0x145
75#define CMD 0x128
76#define ST0 0x118
77#define ST1 0x119
78#define ST2 0x11a
79#define ST3 0x11b
80#define ST4 0x11c
81#define FST 0x11d
82#define IE0 0x120
83#define IE1 0x121
84#define IE2 0x122
85#define IE4 0x124
86#define FIE 0x125
87#define SA0 0x140
88#define SA1 0x141
89#define IDL 0x142
90#define TRBL 0x100
91#define TRBK 0x101
92#define TRBJ 0x102
93#define TRBH 0x103
94#define TRC0 0x148
95#define TRC1 0x149
96#define RRC 0x14a
97#define CST0 0x108
98#define CST1 0x109
99#define CST2 0x10a
100#define CST3 0x10b
101#define GPO 0x131
102#define TFS 0x14b
103#define TFN 0x143
104#define TBN 0x110
105#define RBN 0x111
106#define TNR0 0x150
107#define TNR1 0x151
108#define TCR 0x152
109#define RNR 0x154
110#define RCR 0x156
111
112
113#define TIMER0RX_OFFSET 0x00
114#define TIMER0TX_OFFSET 0x10
115#define TIMER1RX_OFFSET 0x20
116#define TIMER1TX_OFFSET 0x30
117
118#define TCNTL 0x200
119#define TCNTH 0x201
120#define TCONRL 0x204
121#define TCONRH 0x205
122#define TCSR 0x206
123#define TEPR 0x207
124
125
126#define PCR 0x40
127#define DRR 0x44
128#define DMER 0x07
129#define BTCR 0x08
130#define BOLR 0x0c
131#define DSR_RX(chan) (0x48 + 2*chan)
132#define DSR_TX(chan) (0x49 + 2*chan)
133#define DIR_RX(chan) (0x4c + 2*chan)
134#define DIR_TX(chan) (0x4d + 2*chan)
135#define FCT_RX(chan) (0x50 + 2*chan)
136#define FCT_TX(chan) (0x51 + 2*chan)
137#define DMR_RX(chan) (0x54 + 2*chan)
138#define DMR_TX(chan) (0x55 + 2*chan)
139#define DCR_RX(chan) (0x58 + 2*chan)
140#define DCR_TX(chan) (0x59 + 2*chan)
141
142
143#define DMAC0RX_OFFSET 0x00
144#define DMAC0TX_OFFSET 0x20
145#define DMAC1RX_OFFSET 0x40
146#define DMAC1TX_OFFSET 0x60
147
148#define DARL 0x80
149#define DARH 0x81
150#define DARB 0x82
151#define DARBH 0x83
152#define SARL 0x80
153#define SARH 0x81
154#define SARB 0x82
155#define DARBH 0x83
156#define BARL 0x80
157#define BARH 0x81
158#define BARB 0x82
159#define BARBH 0x83
160#define CDAL 0x84
161#define CDAH 0x85
162#define CDAB 0x86
163#define CDABH 0x87
164#define EDAL 0x88
165#define EDAH 0x89
166#define EDAB 0x8a
167#define EDABH 0x8b
168#define BFLL 0x90
169#define BFLH 0x91
170#define BCRL 0x8c
171#define BCRH 0x8d
172
173
174typedef struct {
175 unsigned long next;
176 unsigned long ptbuf;
177 unsigned short len;
178 unsigned char status;
179 unsigned char filler[5];
180} pcsca_bd_t;
181
182
183typedef struct {
184 u32 cp;
185 u32 bp;
186 u16 len;
187 u8 stat;
188 u8 unused;
189}pkt_desc;
190
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204
205
206#define DST_EOT 0x01
207#define DST_OSB 0x02
208#define DST_CRC 0x04
209#define DST_OVR 0x08
210#define DST_UDR 0x08
211#define DST_RBIT 0x10
212#define DST_ABT 0x20
213#define DST_SHRT 0x40
214#define DST_EOM 0x80
215
216
217
218#define ST_TX_EOM 0x80
219#define ST_TX_UNDRRUN 0x08
220#define ST_TX_OWNRSHP 0x02
221#define ST_TX_EOT 0x01
222
223#define ST_RX_EOM 0x80
224#define ST_RX_SHORT 0x40
225#define ST_RX_ABORT 0x20
226#define ST_RX_RESBIT 0x10
227#define ST_RX_OVERRUN 0x08
228#define ST_RX_CRC 0x04
229#define ST_RX_OWNRSHP 0x02
230
231#define ST_ERROR_MASK 0x7C
232
233
234#define CMCR 0x158
235#define TECNTL 0x160
236#define TECNTM 0x161
237#define TECNTH 0x162
238#define TECCR 0x163
239#define URCNTL 0x164
240#define URCNTH 0x165
241#define URCCR 0x167
242#define RECNTL 0x168
243#define RECNTM 0x169
244#define RECNTH 0x16a
245#define RECCR 0x16b
246#define ORCNTL 0x16c
247#define ORCNTH 0x16d
248#define ORCCR 0x16f
249#define CECNTL 0x170
250#define CECNTH 0x171
251#define CECCR 0x173
252#define ABCNTL 0x174
253#define ABCNTH 0x175
254#define ABCCR 0x177
255#define SHCNTL 0x178
256#define SHCNTH 0x179
257#define SHCCR 0x17b
258#define RSCNTL 0x17c
259#define RSCNTH 0x17d
260#define RSCCR 0x17f
261
262
263
264#define IR0_DMIC 0x00000001
265#define IR0_DMIB 0x00000002
266#define IR0_DMIA 0x00000004
267#define IR0_EFT 0x00000008
268#define IR0_DMAREQ 0x00010000
269#define IR0_TXINT 0x00020000
270#define IR0_RXINTB 0x00040000
271#define IR0_RXINTA 0x00080000
272#define IR0_TXRDY 0x00100000
273#define IR0_RXRDY 0x00200000
274
275#define MD0_CRC16_0 0x00
276#define MD0_CRC16_1 0x01
277#define MD0_CRC32 0x02
278#define MD0_CRC_CCITT 0x03
279#define MD0_CRCC0 0x04
280#define MD0_CRCC1 0x08
281#define MD0_AUTO_ENA 0x10
282#define MD0_ASYNC 0x00
283#define MD0_BY_MSYNC 0x20
284#define MD0_BY_BISYNC 0x40
285#define MD0_BY_EXT 0x60
286#define MD0_BIT_SYNC 0x80
287#define MD0_TRANSP 0xc0
288
289#define MD0_HDLC 0x80
290
291#define MD0_CRC_NONE 0x00
292#define MD0_CRC_16_0 0x04
293#define MD0_CRC_16 0x05
294#define MD0_CRC_ITU32 0x06
295#define MD0_CRC_ITU 0x07
296
297#define MD1_NOADDR 0x00
298#define MD1_SADDR1 0x40
299#define MD1_SADDR2 0x80
300#define MD1_DADDR 0xc0
301
302#define MD2_NRZI_IEEE 0x40
303#define MD2_MANCHESTER 0x80
304#define MD2_FM_MARK 0xA0
305#define MD2_FM_SPACE 0xC0
306#define MD2_LOOPBACK 0x03
307
308#define MD2_F_DUPLEX 0x00
309#define MD2_AUTO_ECHO 0x01
310#define MD2_LOOP_HI_Z 0x02
311#define MD2_LOOP_MIR 0x03
312#define MD2_ADPLL_X8 0x00
313#define MD2_ADPLL_X16 0x08
314#define MD2_ADPLL_X32 0x10
315#define MD2_NRZ 0x00
316#define MD2_NRZI 0x20
317#define MD2_NRZ_IEEE 0x40
318#define MD2_MANCH 0x00
319#define MD2_FM1 0x20
320#define MD2_FM0 0x40
321#define MD2_FM 0x80
322
323#define CTL_RTS 0x01
324#define CTL_DTR 0x02
325#define CTL_SYN 0x04
326#define CTL_IDLC 0x10
327#define CTL_UDRNC 0x20
328#define CTL_URSKP 0x40
329#define CTL_URCT 0x80
330
331#define CTL_NORTS 0x01
332#define CTL_NODTR 0x02
333#define CTL_IDLE 0x10
334
335#define RXS_BR0 0x01
336#define RXS_BR1 0x02
337#define RXS_BR2 0x04
338#define RXS_BR3 0x08
339#define RXS_ECLK 0x00
340#define RXS_ECLK_NS 0x20
341#define RXS_IBRG 0x40
342#define RXS_PLL1 0x50
343#define RXS_PLL2 0x60
344#define RXS_PLL3 0x70
345#define RXS_DRTXC 0x80
346
347#define TXS_BR0 0x01
348#define TXS_BR1 0x02
349#define TXS_BR2 0x04
350#define TXS_BR3 0x08
351#define TXS_ECLK 0x00
352#define TXS_IBRG 0x40
353#define TXS_RCLK 0x60
354#define TXS_DTRXC 0x80
355
356#define EXS_RES0 0x01
357#define EXS_RES1 0x02
358#define EXS_RES2 0x04
359#define EXS_TES0 0x10
360#define EXS_TES1 0x20
361#define EXS_TES2 0x40
362
363#define CLK_BRG_MASK 0x0F
364#define CLK_PIN_OUT 0x80
365#define CLK_LINE 0x00
366#define CLK_BRG 0x40
367#define CLK_TX_RXCLK 0x60
368
369#define CMD_RX_RST 0x11
370#define CMD_RX_ENA 0x12
371#define CMD_RX_DIS 0x13
372#define CMD_RX_CRC_INIT 0x14
373#define CMD_RX_MSG_REJ 0x15
374#define CMD_RX_MP_SRCH 0x16
375#define CMD_RX_CRC_EXC 0x17
376#define CMD_RX_CRC_FRC 0x18
377#define CMD_TX_RST 0x01
378#define CMD_TX_ENA 0x02
379#define CMD_TX_DISA 0x03
380#define CMD_TX_CRC_INIT 0x04
381#define CMD_TX_CRC_EXC 0x05
382#define CMD_TX_EOM 0x06
383#define CMD_TX_ABORT 0x07
384#define CMD_TX_MP_ON 0x08
385#define CMD_TX_BUF_CLR 0x09
386#define CMD_TX_DISB 0x0b
387#define CMD_CH_RST 0x21
388#define CMD_SRCH_MODE 0x31
389#define CMD_NOP 0x00
390
391#define CMD_RESET 0x21
392#define CMD_TX_ENABLE 0x02
393#define CMD_RX_ENABLE 0x12
394
395#define ST0_RXRDY 0x01
396#define ST0_TXRDY 0x02
397#define ST0_RXINTB 0x20
398#define ST0_RXINTA 0x40
399#define ST0_TXINT 0x80
400
401#define ST1_IDLE 0x01
402#define ST1_ABORT 0x02
403#define ST1_CDCD 0x04
404#define ST1_CCTS 0x08
405#define ST1_SYN_FLAG 0x10
406#define ST1_CLMD 0x20
407#define ST1_TXIDLE 0x40
408#define ST1_UDRN 0x80
409
410#define ST2_CRCE 0x04
411#define ST2_ONRN 0x08
412#define ST2_RBIT 0x10
413#define ST2_ABORT 0x20
414#define ST2_SHORT 0x40
415#define ST2_EOM 0x80
416
417#define ST3_RX_ENA 0x01
418#define ST3_TX_ENA 0x02
419#define ST3_DCD 0x04
420#define ST3_CTS 0x08
421#define ST3_SRCH_MODE 0x10
422#define ST3_SLOOP 0x20
423#define ST3_GPI 0x80
424
425#define ST4_RDNR 0x01
426#define ST4_RDCR 0x02
427#define ST4_TDNR 0x04
428#define ST4_TDCR 0x08
429#define ST4_OCLM 0x20
430#define ST4_CFT 0x40
431#define ST4_CGPI 0x80
432
433#define FST_CRCEF 0x04
434#define FST_OVRNF 0x08
435#define FST_RBIF 0x10
436#define FST_ABTF 0x20
437#define FST_SHRTF 0x40
438#define FST_EOMF 0x80
439
440#define IE0_RXRDY 0x01
441#define IE0_TXRDY 0x02
442#define IE0_RXINTB 0x20
443#define IE0_RXINTA 0x40
444#define IE0_TXINT 0x80
445#define IE0_UDRN 0x00008000
446#define IE0_CDCD 0x00000400
447
448#define IE1_IDLD 0x01
449#define IE1_ABTD 0x02
450#define IE1_CDCD 0x04
451#define IE1_CCTS 0x08
452#define IE1_SYNCD 0x10
453#define IE1_CLMD 0x20
454#define IE1_IDL 0x40
455#define IE1_UDRN 0x80
456
457#define IE2_CRCE 0x04
458#define IE2_OVRN 0x08
459#define IE2_RBIT 0x10
460#define IE2_ABT 0x20
461#define IE2_SHRT 0x40
462#define IE2_EOM 0x80
463
464#define IE4_RDNR 0x01
465#define IE4_RDCR 0x02
466#define IE4_TDNR 0x04
467#define IE4_TDCR 0x08
468#define IE4_OCLM 0x20
469#define IE4_CFT 0x40
470#define IE4_CGPI 0x80
471
472#define FIE_CRCEF 0x04
473#define FIE_OVRNF 0x08
474#define FIE_RBIF 0x10
475#define FIE_ABTF 0x20
476#define FIE_SHRTF 0x40
477#define FIE_EOMF 0x80
478
479#define DSR_DWE 0x01
480#define DSR_DE 0x02
481#define DSR_REF 0x04
482#define DSR_UDRF 0x04
483#define DSR_COA 0x08
484#define DSR_COF 0x10
485#define DSR_BOF 0x20
486#define DSR_EOM 0x40
487#define DSR_EOT 0x80
488
489#define DIR_REF 0x04
490#define DIR_UDRF 0x04
491#define DIR_COA 0x08
492#define DIR_COF 0x10
493#define DIR_BOF 0x20
494#define DIR_EOM 0x40
495#define DIR_EOT 0x80
496
497#define DIR_REFE 0x04
498#define DIR_UDRFE 0x04
499#define DIR_COAE 0x08
500#define DIR_COFE 0x10
501#define DIR_BOFE 0x20
502#define DIR_EOME 0x40
503#define DIR_EOTE 0x80
504
505#define DMR_CNTE 0x02
506#define DMR_NF 0x04
507#define DMR_SEOME 0x08
508#define DMR_TMOD 0x10
509
510#define DMER_DME 0x80
511
512#define DCR_SW_ABT 0x01
513#define DCR_FCT_CLR 0x02
514
515#define DCR_ABORT 0x01
516#define DCR_CLEAR_EOF 0x02
517
518#define PCR_COTE 0x80
519#define PCR_PR0 0x01
520#define PCR_PR1 0x02
521#define PCR_PR2 0x04
522#define PCR_CCC 0x08
523#define PCR_BRC 0x10
524#define PCR_OSB 0x40
525#define PCR_BURST 0x80
526
527#endif
528