LXR linux/drivers/net/wireless/ath/ath10k/pci.h

   1/*
   2 * Copyright (c) 2005-2011 Atheros Communications Inc.
   3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4 *
   5 * Permission to use, copy, modify, and/or distribute this software for any
   6 * purpose with or without fee is hereby granted, provided that the above
   7 * copyright notice and this permission notice appear in all copies.
   8 *
   9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16 */
  17
  18#ifndef _PCI_H_
  19#define _PCI_H_
  20
  21#include <linux/interrupt.h>
  22
  23#include "hw.h"
  24#include "ce.h"
  25#include "ahb.h"
  26
  27/*
  28 * maximum number of bytes that can be
  29 * handled atomically by DiagRead/DiagWrite
  30 */
  31#define DIAG_TRANSFER_LIMIT 2048
  32
  33struct bmi_xfer {
  34        bool tx_done;
  35        bool rx_done;
  36        bool wait_for_resp;
  37        u32 resp_len;
  38};
  39
  40/*
  41 * PCI-specific Target state
  42 *
  43 * NOTE: Structure is shared between Host software and Target firmware!
  44 *
  45 * Much of this may be of interest to the Host so
  46 * HOST_INTEREST->hi_interconnect_state points here
  47 * (and all members are 32-bit quantities in order to
  48 * facilitate Host access). In particular, Host software is
  49 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
  50 */
  51struct pcie_state {
  52        /* Pipe configuration Target address */
  53        /* NB: ce_pipe_config[CE_COUNT] */
  54        u32 pipe_cfg_addr;
  55
  56        /* Service to pipe map Target address */
  57        /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
  58        u32 svc_to_pipe_map;
  59
  60        /* number of MSI interrupts requested */
  61        u32 msi_requested;
  62
  63        /* number of MSI interrupts granted */
  64        u32 msi_granted;
  65
  66        /* Message Signalled Interrupt address */
  67        u32 msi_addr;
  68
  69        /* Base data */
  70        u32 msi_data;
  71
  72        /*
  73         * Data for firmware interrupt;
  74         * MSI data for other interrupts are
  75         * in various SoC registers
  76         */
  77        u32 msi_fw_intr_data;
  78
  79        /* PCIE_PWR_METHOD_* */
  80        u32 power_mgmt_method;
  81
  82        /* PCIE_CONFIG_FLAG_* */
  83        u32 config_flags;
  84};
  85
  86/* PCIE_CONFIG_FLAG definitions */
  87#define PCIE_CONFIG_FLAG_ENABLE_L1  0x0000001
  88
  89/* Host software's Copy Engine configuration. */
  90#define CE_ATTR_FLAGS 0
  91
  92/*
  93 * Configuration information for a Copy Engine pipe.
  94 * Passed from Host to Target during startup (one per CE).
  95 *
  96 * NOTE: Structure is shared between Host software and Target firmware!
  97 */
  98struct ce_pipe_config {
  99        __le32 pipenum;
 100        __le32 pipedir;
 101        __le32 nentries;
 102        __le32 nbytes_max;
 103        __le32 flags;
 104        __le32 reserved;
 105};
 106
 107/*
 108 * Directions for interconnect pipe configuration.
 109 * These definitions may be used during configuration and are shared
 110 * between Host and Target.
 111 *
 112 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
 113 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
 114 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
 115 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
 116 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
 117 * over the interconnect.
 118 */
 119#define PIPEDIR_NONE    0
 120#define PIPEDIR_IN      1  /* Target-->Host, WiFi Rx direction */
 121#define PIPEDIR_OUT     2  /* Host->Target, WiFi Tx direction */
 122#define PIPEDIR_INOUT   3  /* bidirectional */
 123
 124/* Establish a mapping between a service/direction and a pipe. */
 125struct service_to_pipe {
 126        __le32 service_id;
 127        __le32 pipedir;
 128        __le32 pipenum;
 129};
 130
 131/* Per-pipe state. */
 132struct ath10k_pci_pipe {
 133        /* Handle of underlying Copy Engine */
 134        struct ath10k_ce_pipe *ce_hdl;
 135
 136        /* Our pipe number; facilitiates use of pipe_info ptrs. */
 137        u8 pipe_num;
 138
 139        /* Convenience back pointer to hif_ce_state. */
 140        struct ath10k *hif_ce_state;
 141
 142        size_t buf_sz;
 143
 144        /* protects compl_free and num_send_allowed */
 145        spinlock_t pipe_lock;
 146};
 147
 148struct ath10k_pci_supp_chip {
 149        u32 dev_id;
 150        u32 rev_id;
 151};
 152
 153enum ath10k_pci_irq_mode {
 154        ATH10K_PCI_IRQ_AUTO = 0,
 155        ATH10K_PCI_IRQ_LEGACY = 1,
 156        ATH10K_PCI_IRQ_MSI = 2,
 157};
 158
 159struct ath10k_pci {
 160        struct pci_dev *pdev;
 161        struct device *dev;
 162        struct ath10k *ar;
 163        void __iomem *mem;
 164        size_t mem_len;
 165
 166        /* Operating interrupt mode */
 167        enum ath10k_pci_irq_mode oper_irq_mode;
 168
 169        struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
 170
 171        /* Copy Engine used for Diagnostic Accesses */
 172        struct ath10k_ce_pipe *ce_diag;
 173
 174        struct ath10k_ce ce;
 175        struct timer_list rx_post_retry;
 176
 177        /* Due to HW quirks it is recommended to disable ASPM during device
 178         * bootup. To do that the original PCI-E Link Control is stored before
 179         * device bootup is executed and re-programmed later.
 180         */
 181        u16 link_ctl;
 182
 183        /* Protects ps_awake and ps_wake_refcount */
 184        spinlock_t ps_lock;
 185
 186        /* The device has a special powersave-oriented register. When device is
 187         * considered asleep it drains less power and driver is forbidden from
 188         * accessing most MMIO registers. If host were to access them without
 189         * waking up the device might scribble over host memory or return
 190         * 0xdeadbeef readouts.
 191         */
 192        unsigned long ps_wake_refcount;
 193
 194        /* Waking up takes some time (up to 2ms in some cases) so it can be bad
 195         * for latency. To mitigate this the device isn't immediately allowed
 196         * to sleep after all references are undone - instead there's a grace
 197         * period after which the powersave register is updated unless some
 198         * activity to/from device happened in the meantime.
 199         *
 200         * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
 201         */
 202        struct timer_list ps_timer;
 203
 204        /* MMIO registers are used to communicate with the device. With
 205         * intensive traffic accessing powersave register would be a bit
 206         * wasteful overhead and would needlessly stall CPU. It is far more
 207         * efficient to rely on a variable in RAM and update it only upon
 208         * powersave register state changes.
 209         */
 210        bool ps_awake;
 211
 212        /* pci power save, disable for QCA988X and QCA99X0.
 213         * Writing 'false' to this variable avoids frequent locking
 214         * on MMIO read/write.
 215         */
 216        bool pci_ps;
 217
 218        /* Chip specific pci reset routine used to do a safe reset */
 219        int (*pci_soft_reset)(struct ath10k *ar);
 220
 221        /* Chip specific pci full reset function */
 222        int (*pci_hard_reset)(struct ath10k *ar);
 223
 224        /* chip specific methods for converting target CPU virtual address
 225         * space to CE address space
 226         */
 227        u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
 228
 229        /* Keep this entry in the last, memory for struct ath10k_ahb is
 230         * allocated (ahb support enabled case) in the continuation of
 231         * this struct.
 232         */
 233        struct ath10k_ahb ahb[0];
 234};
 235
 236static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
 237{
 238        return (struct ath10k_pci *)ar->drv_priv;
 239}
 240
 241#define ATH10K_PCI_RX_POST_RETRY_MS 50
 242#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
 243#define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
 244#define PCIE_WAKE_LATE_US 10000 /* 10ms */
 245
 246#define BAR_NUM 0
 247
 248#define CDC_WAR_MAGIC_STR   0xceef0000
 249#define CDC_WAR_DATA_CE     4
 250
 251/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
 252#define DIAG_ACCESS_CE_TIMEOUT_MS 10
 253
 254void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
 255void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
 256void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
 257
 258u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
 259u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
 260u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
 261
 262int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
 263                         struct ath10k_hif_sg_item *items, int n_items);
 264int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
 265                             size_t buf_len);
 266int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
 267                              const void *data, int nbytes);
 268int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
 269                                    void *resp, u32 *resp_len);
 270int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
 271                                       u8 *ul_pipe, u8 *dl_pipe);
 272void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
 273                                     u8 *dl_pipe);
 274void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
 275                                        int force);
 276u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
 277void ath10k_pci_hif_power_down(struct ath10k *ar);
 278int ath10k_pci_alloc_pipes(struct ath10k *ar);
 279void ath10k_pci_free_pipes(struct ath10k *ar);
 280void ath10k_pci_free_pipes(struct ath10k *ar);
 281void ath10k_pci_rx_replenish_retry(struct timer_list *t);
 282void ath10k_pci_ce_deinit(struct ath10k *ar);
 283void ath10k_pci_init_napi(struct ath10k *ar);
 284int ath10k_pci_init_pipes(struct ath10k *ar);
 285int ath10k_pci_init_config(struct ath10k *ar);
 286void ath10k_pci_rx_post(struct ath10k *ar);
 287void ath10k_pci_flush(struct ath10k *ar);
 288void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
 289bool ath10k_pci_irq_pending(struct ath10k *ar);
 290void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
 291void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
 292int ath10k_pci_wait_for_target_init(struct ath10k *ar);
 293int ath10k_pci_setup_resource(struct ath10k *ar);
 294void ath10k_pci_release_resource(struct ath10k *ar);
 295
 296/* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
 297 * frequently. To avoid this put SoC to sleep after a very conservative grace
 298 * period. Adjust with great care.
 299 */
 300#define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
 301
 302#endif /* _PCI_H_ */
 303