LXR linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2009-2013  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * The full GNU General Public License is included in this distribution in the
  15 * file called LICENSE.
  16 *
  17 * Contact Information:
  18 * wlanfae <wlanfae@realtek.com>
  19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20 * Hsinchu 300, Taiwan.
  21 *
  22 * Larry Finger <Larry.Finger@lwfinger.net>
  23 *
  24 *****************************************************************************/
  25
  26#ifndef __RTL8723E_PWRSEQ_H__
  27#define __RTL8723E_PWRSEQ_H__
  28
  29#include "../pwrseqcmd.h"
  30/* Check document WM-20110607-Paul-RTL8188EE_Power_Architecture-R02.vsd
  31 *      There are 6 HW Power States:
  32 *      0: POFF--Power Off
  33 *      1: PDN--Power Down
  34 *      2: CARDEMU--Card Emulation
  35 *      3: ACT--Active Mode
  36 *      4: LPS--Low Power State
  37 *      5: SUS--Suspend
  38 *
  39 *      The transision from different states are defined below
  40 *      TRANS_CARDEMU_TO_ACT
  41 *      TRANS_ACT_TO_CARDEMU
  42 *      TRANS_CARDEMU_TO_SUS
  43 *      TRANS_SUS_TO_CARDEMU
  44 *      TRANS_CARDEMU_TO_PDN
  45 *      TRANS_ACT_TO_LPS
  46 *      TRANS_LPS_TO_ACT
  47 *
  48 *      TRANS_END
  49 *      PWR SEQ Version: rtl8188ee_PwrSeq_V09.h
  50 */
  51
  52#define RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS    10
  53#define RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS    10
  54#define RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS    10
  55#define RTL8188EE_TRANS_SUS_TO_CARDEMU_STEPS    10
  56#define RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS    10
  57#define RTL8188EE_TRANS_PDN_TO_CARDEMU_STEPS    10
  58#define RTL8188EE_TRANS_ACT_TO_LPS_STEPS                15
  59#define RTL8188EE_TRANS_LPS_TO_ACT_STEPS                15
  60#define RTL8188EE_TRANS_END_STEPS               1
  61
  62/* The following macros have the following format:
  63 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
  64 *   comments },
  65 */
  66#define RTL8188EE_TRANS_CARDEMU_TO_ACT                                  \
  67        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  68        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)               \
  69        /* wait till 0x04[17] = 1    power ready*/},                    \
  70        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  71        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0               \
  72        /* 0x02[1:0] = 0        reset BB*/},                            \
  73        {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  74        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)                 \
  75        /*0x24[23] = 2b'01 schmit trigger */},                          \
  76        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  77        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0                      \
  78        /* 0x04[15] = 0 disable HWPDN (control by DRV)*/},              \
  79        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  80        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0               \
  81        /*0x04[12:11] = 2b'00 disable WL suspend*/},                    \
  82        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  83        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)                 \
  84        /*0x04[8] = 1 polling until return 0*/},                        \
  85        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  86        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0                    \
  87        /*wait till 0x04[8] = 0*/},                                     \
  88        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  89        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0                      \
  90        /*LDO normal mode*/},                                           \
  91        {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
  92        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)                 \
  93        /*SDIO Driving*/},
  94
  95#define RTL8188EE_TRANS_ACT_TO_CARDEMU                                  \
  96        {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  97        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0                        \
  98        /*0x1F[7:0] = 0 turn off RF*/},                                 \
  99        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 100        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)                 \
 101        /*LDO Sleep mode*/},                                            \
 102        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 103        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)                 \
 104        /*0x04[9] = 1 turn off MAC by HW state machine*/},              \
 105        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 106        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0                    \
 107        /*wait till 0x04[9] = 0 polling until return 0 to disable*/},
 108
 109#define RTL8188EE_TRANS_CARDEMU_TO_SUS                                  \
 110        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 111        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 112        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)          \
 113        /*0x04[12:11] = 2b'01enable WL suspend*/},                      \
 114        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 115        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)   \
 116        /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/},             \
 117        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 118        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 119        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7)                   \
 120        /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */},\
 121        {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 122        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 123        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0                      \
 124        /*Clear SIC_EN register 0x40[12] = 1'b0 */},                    \
 125        {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 126        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 127        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)                 \
 128        /*Set USB suspend enable local register  0xfe10[4]=1 */},       \
 129        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 130        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)                \
 131        /*Set SDIO suspend local register*/},                           \
 132        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 133        PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0                   \
 134        /*wait power state to suspend*/},
 135
 136#define RTL8188EE_TRANS_SUS_TO_CARDEMU                                  \
 137        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 138        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0                     \
 139        /*Set SDIO suspend local register*/},                           \
 140        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 141        PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)              \
 142        /*wait power state to suspend*/},                               \
 143        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 144        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0             \
 145        /*0x04[12:11] = 2b'01enable WL suspend*/},
 146
 147#define RTL8188EE_TRANS_CARDEMU_TO_CARDDIS                              \
 148        {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 149        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)                 \
 150        /*0x24[23] = 2b'01 schmit trigger */},                          \
 151        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 152        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 153        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)        \
 154        /*0x04[12:11] = 2b'01 enable WL suspend*/},                     \
 155        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 156        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 157        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0                        \
 158        /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */},\
 159        {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 160        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 161        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0                      \
 162        /*Clear SIC_EN register 0x40[12] = 1'b0 */},                    \
 163        {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 164        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)                 \
 165        /*Set USB suspend enable local register  0xfe10[4]=1 */},       \
 166        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 167        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)                \
 168        /*Set SDIO suspend local register*/},                           \
 169        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 170        PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0                   \
 171        /*wait power state to suspend*/},
 172
 173#define RTL8188EE_TRANS_CARDDIS_TO_CARDEMU                              \
 174        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 175        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0                     \
 176        /*Set SDIO suspend local register*/},                           \
 177        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 178        PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)              \
 179        /*wait power state to suspend*/},                               \
 180        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 181        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0               \
 182        /*0x04[12:11] = 2b'01enable WL suspend*/},
 183
 184#define RTL8188EE_TRANS_CARDEMU_TO_PDN                                  \
 185        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 186        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/},   \
 187        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 188        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)                 \
 189        /* 0x04[15] = 1*/},
 190
 191#define RTL8188EE_TRANS_PDN_TO_CARDEMU                                  \
 192        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 193        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/},
 194
 195#define RTL8188EE_TRANS_ACT_TO_LPS                                      \
 196        {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 197        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F                     \
 198        /*Tx Pause*/},                                                  \
 199        {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 200        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0                      \
 201        /*Should be zero if no packet is transmitting*/},               \
 202        {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 203        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0                      \
 204        /*Should be zero if no packet is transmitting*/},               \
 205        {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 206        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0                      \
 207        /*Should be zero if no packet is transmitting*/},               \
 208        {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 209        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0                      \
 210        /*Should be zero if no packet is transmitting*/},               \
 211        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 212        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0                      \
 213        /*CCK and OFDM are disabled,and clock are gated*/},             \
 214        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 215        PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US             \
 216        /*Delay 1us*/},                                                 \
 217        {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 218        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F                     \
 219        /*Reset MAC TRX*/},                                             \
 220        {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 221        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0                      \
 222        /*check if removed later*/},                                    \
 223        {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 224        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)                 \
 225        /*Respond TxOK to scheduler*/},
 226
 227
 228#define RTL8188EE_TRANS_LPS_TO_ACT                                      \
 229        {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 230        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84                    \
 231        /*SDIO RPWM*/},                                                 \
 232        {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 233        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84                     \
 234        /*USB RPWM*/},                                                  \
 235        {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 236        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84                     \
 237        /*PCIe RPWM*/},                                                 \
 238        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 239        PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS             \
 240        /*Delay*/},                                                     \
 241        {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 242        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0                      \
 243        /*.     0x08[4] = 0              switch TSF to 40M*/},          \
 244        {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 245        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0                    \
 246        /*Polling 0x109[7]=0  TSF in 40M*/},                            \
 247        {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 248        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0               \
 249        /*.     0x29[7:6] = 2b'00        enable BB clock*/},            \
 250        {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 251        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)                 \
 252        /*.     0x101[1] = 1*/},                                        \
 253        {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 254        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF                     \
 255        /*.     0x100[7:0] = 0xFF        enable WMAC TRX*/},            \
 256        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 257        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)   \
 258        /*.     0x02[1:0] = 2b'11        enable BB macro*/},            \
 259        {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 260        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0                        \
 261        /*.     0x522 = 0*/},
 262
 263#define RTL8188EE_TRANS_END             \
 264        {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 265        0, PWR_CMD_END, 0, 0}
 266
 267extern struct wlan_pwr_cfg rtl8188ee_power_on_flow
 268                [RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS +
 269                 RTL8188EE_TRANS_END_STEPS];
 270extern struct wlan_pwr_cfg rtl8188ee_radio_off_flow
 271                [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
 272                 RTL8188EE_TRANS_END_STEPS];
 273extern struct wlan_pwr_cfg rtl8188ee_card_disable_flow
 274                [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
 275                 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
 276                 RTL8188EE_TRANS_END_STEPS];
 277extern struct wlan_pwr_cfg rtl8188ee_card_enable_flow
 278                [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
 279                 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
 280                 RTL8188EE_TRANS_END_STEPS];
 281extern struct wlan_pwr_cfg rtl8188ee_suspend_flow
 282                [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
 283                 RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS +
 284                 RTL8188EE_TRANS_END_STEPS];
 285extern struct wlan_pwr_cfg rtl8188ee_resume_flow
 286                [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
 287                 RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS +
 288                 RTL8188EE_TRANS_END_STEPS];
 289extern struct wlan_pwr_cfg rtl8188ee_hwpdn_flow
 290                [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
 291                 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
 292                 RTL8188EE_TRANS_END_STEPS];
 293extern struct wlan_pwr_cfg rtl8188ee_enter_lps_flow
 294                [RTL8188EE_TRANS_ACT_TO_LPS_STEPS +
 295                 RTL8188EE_TRANS_END_STEPS];
 296extern struct wlan_pwr_cfg rtl8188ee_leave_lps_flow
 297                [RTL8188EE_TRANS_LPS_TO_ACT_STEPS +
 298                 RTL8188EE_TRANS_END_STEPS];
 299
 300/* RTL8723 Power Configuration CMDs for PCIe interface */
 301#define RTL8188EE_NIC_PWR_ON_FLOW       rtl8188ee_power_on_flow
 302#define RTL8188EE_NIC_RF_OFF_FLOW       rtl8188ee_radio_off_flow
 303#define RTL8188EE_NIC_DISABLE_FLOW      rtl8188ee_card_disable_flow
 304#define RTL8188EE_NIC_ENABLE_FLOW       rtl8188ee_card_enable_flow
 305#define RTL8188EE_NIC_SUSPEND_FLOW      rtl8188ee_suspend_flow
 306#define RTL8188EE_NIC_RESUME_FLOW       rtl8188ee_resume_flow
 307#define RTL8188EE_NIC_PDN_FLOW          rtl8188ee_hwpdn_flow
 308#define RTL8188EE_NIC_LPS_ENTER_FLOW    rtl8188ee_enter_lps_flow
 309#define RTL8188EE_NIC_LPS_LEAVE_FLOW    rtl8188ee_leave_lps_flow
 310
 311#endif
 312