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14#include <linux/acpi.h>
15#include <linux/bcd.h>
16#include <linux/i2c.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/rtc/ds1307.h>
21#include <linux/rtc.h>
22#include <linux/slab.h>
23#include <linux/string.h>
24#include <linux/hwmon.h>
25#include <linux/hwmon-sysfs.h>
26#include <linux/clk-provider.h>
27#include <linux/regmap.h>
28
29
30
31
32
33
34
35enum ds_type {
36 ds_1307,
37 ds_1308,
38 ds_1337,
39 ds_1338,
40 ds_1339,
41 ds_1340,
42 ds_1341,
43 ds_1388,
44 ds_3231,
45 m41t0,
46 m41t00,
47 mcp794xx,
48 rx_8025,
49 rx_8130,
50 last_ds_type
51
52};
53
54
55#define DS1307_REG_SECS 0x00
56# define DS1307_BIT_CH 0x80
57# define DS1340_BIT_nEOSC 0x80
58# define MCP794XX_BIT_ST 0x80
59#define DS1307_REG_MIN 0x01
60# define M41T0_BIT_OF 0x80
61#define DS1307_REG_HOUR 0x02
62# define DS1307_BIT_12HR 0x40
63# define DS1307_BIT_PM 0x20
64# define DS1340_BIT_CENTURY_EN 0x80
65# define DS1340_BIT_CENTURY 0x40
66#define DS1307_REG_WDAY 0x03
67# define MCP794XX_BIT_VBATEN 0x08
68#define DS1307_REG_MDAY 0x04
69#define DS1307_REG_MONTH 0x05
70# define DS1337_BIT_CENTURY 0x80
71#define DS1307_REG_YEAR 0x06
72
73
74
75
76
77
78#define DS1307_REG_CONTROL 0x07
79# define DS1307_BIT_OUT 0x80
80# define DS1338_BIT_OSF 0x20
81# define DS1307_BIT_SQWE 0x10
82# define DS1307_BIT_RS1 0x02
83# define DS1307_BIT_RS0 0x01
84#define DS1337_REG_CONTROL 0x0e
85# define DS1337_BIT_nEOSC 0x80
86# define DS1339_BIT_BBSQI 0x20
87# define DS3231_BIT_BBSQW 0x40
88# define DS1337_BIT_RS2 0x10
89# define DS1337_BIT_RS1 0x08
90# define DS1337_BIT_INTCN 0x04
91# define DS1337_BIT_A2IE 0x02
92# define DS1337_BIT_A1IE 0x01
93#define DS1340_REG_CONTROL 0x07
94# define DS1340_BIT_OUT 0x80
95# define DS1340_BIT_FT 0x40
96# define DS1340_BIT_CALIB_SIGN 0x20
97# define DS1340_M_CALIBRATION 0x1f
98#define DS1340_REG_FLAG 0x09
99# define DS1340_BIT_OSF 0x80
100#define DS1337_REG_STATUS 0x0f
101# define DS1337_BIT_OSF 0x80
102# define DS3231_BIT_EN32KHZ 0x08
103# define DS1337_BIT_A2I 0x02
104# define DS1337_BIT_A1I 0x01
105#define DS1339_REG_ALARM1_SECS 0x07
106
107#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
108
109#define RX8025_REG_CTRL1 0x0e
110# define RX8025_BIT_2412 0x20
111#define RX8025_REG_CTRL2 0x0f
112# define RX8025_BIT_PON 0x10
113# define RX8025_BIT_VDET 0x40
114# define RX8025_BIT_XST 0x20
115
116struct ds1307 {
117 struct nvmem_config nvmem_cfg;
118 enum ds_type type;
119 unsigned long flags;
120#define HAS_NVRAM 0
121#define HAS_ALARM 1
122 struct device *dev;
123 struct regmap *regmap;
124 const char *name;
125 struct rtc_device *rtc;
126#ifdef CONFIG_COMMON_CLK
127 struct clk_hw clks[2];
128#endif
129};
130
131struct chip_desc {
132 unsigned alarm:1;
133 u16 nvram_offset;
134 u16 nvram_size;
135 u8 offset;
136 u8 century_reg;
137 u8 century_enable_bit;
138 u8 century_bit;
139 u8 bbsqi_bit;
140 irq_handler_t irq_handler;
141 const struct rtc_class_ops *rtc_ops;
142 u16 trickle_charger_reg;
143 u8 (*do_trickle_setup)(struct ds1307 *, u32,
144 bool);
145};
146
147static int ds1307_get_time(struct device *dev, struct rtc_time *t);
148static int ds1307_set_time(struct device *dev, struct rtc_time *t);
149static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
150static irqreturn_t rx8130_irq(int irq, void *dev_id);
151static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t);
152static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t);
153static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled);
154static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
155static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t);
156static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t);
157static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
158
159static const struct rtc_class_ops rx8130_rtc_ops = {
160 .read_time = ds1307_get_time,
161 .set_time = ds1307_set_time,
162 .read_alarm = rx8130_read_alarm,
163 .set_alarm = rx8130_set_alarm,
164 .alarm_irq_enable = rx8130_alarm_irq_enable,
165};
166
167static const struct rtc_class_ops mcp794xx_rtc_ops = {
168 .read_time = ds1307_get_time,
169 .set_time = ds1307_set_time,
170 .read_alarm = mcp794xx_read_alarm,
171 .set_alarm = mcp794xx_set_alarm,
172 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
173};
174
175static const struct chip_desc chips[last_ds_type] = {
176 [ds_1307] = {
177 .nvram_offset = 8,
178 .nvram_size = 56,
179 },
180 [ds_1308] = {
181 .nvram_offset = 8,
182 .nvram_size = 56,
183 },
184 [ds_1337] = {
185 .alarm = 1,
186 .century_reg = DS1307_REG_MONTH,
187 .century_bit = DS1337_BIT_CENTURY,
188 },
189 [ds_1338] = {
190 .nvram_offset = 8,
191 .nvram_size = 56,
192 },
193 [ds_1339] = {
194 .alarm = 1,
195 .century_reg = DS1307_REG_MONTH,
196 .century_bit = DS1337_BIT_CENTURY,
197 .bbsqi_bit = DS1339_BIT_BBSQI,
198 .trickle_charger_reg = 0x10,
199 .do_trickle_setup = &do_trickle_setup_ds1339,
200 },
201 [ds_1340] = {
202 .century_reg = DS1307_REG_HOUR,
203 .century_enable_bit = DS1340_BIT_CENTURY_EN,
204 .century_bit = DS1340_BIT_CENTURY,
205 .trickle_charger_reg = 0x08,
206 },
207 [ds_1341] = {
208 .century_reg = DS1307_REG_MONTH,
209 .century_bit = DS1337_BIT_CENTURY,
210 },
211 [ds_1388] = {
212 .offset = 1,
213 .trickle_charger_reg = 0x0a,
214 },
215 [ds_3231] = {
216 .alarm = 1,
217 .century_reg = DS1307_REG_MONTH,
218 .century_bit = DS1337_BIT_CENTURY,
219 .bbsqi_bit = DS3231_BIT_BBSQW,
220 },
221 [rx_8130] = {
222 .alarm = 1,
223
224 .nvram_offset = 0x20,
225 .nvram_size = 4,
226 .offset = 0x10,
227 .irq_handler = rx8130_irq,
228 .rtc_ops = &rx8130_rtc_ops,
229 },
230 [mcp794xx] = {
231 .alarm = 1,
232
233 .nvram_offset = 0x20,
234 .nvram_size = 0x40,
235 .irq_handler = mcp794xx_irq,
236 .rtc_ops = &mcp794xx_rtc_ops,
237 },
238};
239
240static const struct i2c_device_id ds1307_id[] = {
241 { "ds1307", ds_1307 },
242 { "ds1308", ds_1308 },
243 { "ds1337", ds_1337 },
244 { "ds1338", ds_1338 },
245 { "ds1339", ds_1339 },
246 { "ds1388", ds_1388 },
247 { "ds1340", ds_1340 },
248 { "ds1341", ds_1341 },
249 { "ds3231", ds_3231 },
250 { "m41t0", m41t0 },
251 { "m41t00", m41t00 },
252 { "mcp7940x", mcp794xx },
253 { "mcp7941x", mcp794xx },
254 { "pt7c4338", ds_1307 },
255 { "rx8025", rx_8025 },
256 { "isl12057", ds_1337 },
257 { "rx8130", rx_8130 },
258 { }
259};
260MODULE_DEVICE_TABLE(i2c, ds1307_id);
261
262#ifdef CONFIG_OF
263static const struct of_device_id ds1307_of_match[] = {
264 {
265 .compatible = "dallas,ds1307",
266 .data = (void *)ds_1307
267 },
268 {
269 .compatible = "dallas,ds1308",
270 .data = (void *)ds_1308
271 },
272 {
273 .compatible = "dallas,ds1337",
274 .data = (void *)ds_1337
275 },
276 {
277 .compatible = "dallas,ds1338",
278 .data = (void *)ds_1338
279 },
280 {
281 .compatible = "dallas,ds1339",
282 .data = (void *)ds_1339
283 },
284 {
285 .compatible = "dallas,ds1388",
286 .data = (void *)ds_1388
287 },
288 {
289 .compatible = "dallas,ds1340",
290 .data = (void *)ds_1340
291 },
292 {
293 .compatible = "dallas,ds1341",
294 .data = (void *)ds_1341
295 },
296 {
297 .compatible = "maxim,ds3231",
298 .data = (void *)ds_3231
299 },
300 {
301 .compatible = "st,m41t0",
302 .data = (void *)m41t00
303 },
304 {
305 .compatible = "st,m41t00",
306 .data = (void *)m41t00
307 },
308 {
309 .compatible = "microchip,mcp7940x",
310 .data = (void *)mcp794xx
311 },
312 {
313 .compatible = "microchip,mcp7941x",
314 .data = (void *)mcp794xx
315 },
316 {
317 .compatible = "pericom,pt7c4338",
318 .data = (void *)ds_1307
319 },
320 {
321 .compatible = "epson,rx8025",
322 .data = (void *)rx_8025
323 },
324 {
325 .compatible = "isil,isl12057",
326 .data = (void *)ds_1337
327 },
328 {
329 .compatible = "epson,rx8130",
330 .data = (void *)rx_8130
331 },
332 { }
333};
334MODULE_DEVICE_TABLE(of, ds1307_of_match);
335#endif
336
337#ifdef CONFIG_ACPI
338static const struct acpi_device_id ds1307_acpi_ids[] = {
339 { .id = "DS1307", .driver_data = ds_1307 },
340 { .id = "DS1308", .driver_data = ds_1308 },
341 { .id = "DS1337", .driver_data = ds_1337 },
342 { .id = "DS1338", .driver_data = ds_1338 },
343 { .id = "DS1339", .driver_data = ds_1339 },
344 { .id = "DS1388", .driver_data = ds_1388 },
345 { .id = "DS1340", .driver_data = ds_1340 },
346 { .id = "DS1341", .driver_data = ds_1341 },
347 { .id = "DS3231", .driver_data = ds_3231 },
348 { .id = "M41T0", .driver_data = m41t0 },
349 { .id = "M41T00", .driver_data = m41t00 },
350 { .id = "MCP7940X", .driver_data = mcp794xx },
351 { .id = "MCP7941X", .driver_data = mcp794xx },
352 { .id = "PT7C4338", .driver_data = ds_1307 },
353 { .id = "RX8025", .driver_data = rx_8025 },
354 { .id = "ISL12057", .driver_data = ds_1337 },
355 { .id = "RX8130", .driver_data = rx_8130 },
356 { }
357};
358MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
359#endif
360
361
362
363
364
365
366static irqreturn_t ds1307_irq(int irq, void *dev_id)
367{
368 struct ds1307 *ds1307 = dev_id;
369 struct mutex *lock = &ds1307->rtc->ops_lock;
370 int stat, ret;
371
372 mutex_lock(lock);
373 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
374 if (ret)
375 goto out;
376
377 if (stat & DS1337_BIT_A1I) {
378 stat &= ~DS1337_BIT_A1I;
379 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
380
381 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
382 DS1337_BIT_A1IE, 0);
383 if (ret)
384 goto out;
385
386 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
387 }
388
389out:
390 mutex_unlock(lock);
391
392 return IRQ_HANDLED;
393}
394
395
396
397static int ds1307_get_time(struct device *dev, struct rtc_time *t)
398{
399 struct ds1307 *ds1307 = dev_get_drvdata(dev);
400 int tmp, ret;
401 const struct chip_desc *chip = &chips[ds1307->type];
402 u8 regs[7];
403
404
405 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
406 sizeof(regs));
407 if (ret) {
408 dev_err(dev, "%s error %d\n", "read", ret);
409 return ret;
410 }
411
412 dev_dbg(dev, "%s: %7ph\n", "read", regs);
413
414
415 if (ds1307->type == m41t0 &&
416 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
417 dev_warn_once(dev, "oscillator failed, set time!\n");
418 return -EINVAL;
419 }
420
421 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
422 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
423 tmp = regs[DS1307_REG_HOUR] & 0x3f;
424 t->tm_hour = bcd2bin(tmp);
425 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
426 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
427 tmp = regs[DS1307_REG_MONTH] & 0x1f;
428 t->tm_mon = bcd2bin(tmp) - 1;
429 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
430
431 if (regs[chip->century_reg] & chip->century_bit &&
432 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
433 t->tm_year += 100;
434
435 dev_dbg(dev, "%s secs=%d, mins=%d, "
436 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
437 "read", t->tm_sec, t->tm_min,
438 t->tm_hour, t->tm_mday,
439 t->tm_mon, t->tm_year, t->tm_wday);
440
441
442 return rtc_valid_tm(t);
443}
444
445static int ds1307_set_time(struct device *dev, struct rtc_time *t)
446{
447 struct ds1307 *ds1307 = dev_get_drvdata(dev);
448 const struct chip_desc *chip = &chips[ds1307->type];
449 int result;
450 int tmp;
451 u8 regs[7];
452
453 dev_dbg(dev, "%s secs=%d, mins=%d, "
454 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
455 "write", t->tm_sec, t->tm_min,
456 t->tm_hour, t->tm_mday,
457 t->tm_mon, t->tm_year, t->tm_wday);
458
459 if (t->tm_year < 100)
460 return -EINVAL;
461
462#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
463 if (t->tm_year > (chip->century_bit ? 299 : 199))
464 return -EINVAL;
465#else
466 if (t->tm_year > 199)
467 return -EINVAL;
468#endif
469
470 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
471 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
472 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
473 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
474 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
475 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
476
477
478 tmp = t->tm_year - 100;
479 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
480
481 if (chip->century_enable_bit)
482 regs[chip->century_reg] |= chip->century_enable_bit;
483 if (t->tm_year > 199 && chip->century_bit)
484 regs[chip->century_reg] |= chip->century_bit;
485
486 if (ds1307->type == mcp794xx) {
487
488
489
490
491
492 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
493 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
494 }
495
496 dev_dbg(dev, "%s: %7ph\n", "write", regs);
497
498 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
499 sizeof(regs));
500 if (result) {
501 dev_err(dev, "%s error %d\n", "write", result);
502 return result;
503 }
504 return 0;
505}
506
507static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
508{
509 struct ds1307 *ds1307 = dev_get_drvdata(dev);
510 int ret;
511 u8 regs[9];
512
513 if (!test_bit(HAS_ALARM, &ds1307->flags))
514 return -EINVAL;
515
516
517 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
518 regs, sizeof(regs));
519 if (ret) {
520 dev_err(dev, "%s error %d\n", "alarm read", ret);
521 return ret;
522 }
523
524 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
525 ®s[0], ®s[4], ®s[7]);
526
527
528
529
530
531 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
532 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
533 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
534 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
535
536
537 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
538 t->pending = !!(regs[8] & DS1337_BIT_A1I);
539
540 dev_dbg(dev, "%s secs=%d, mins=%d, "
541 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
542 "alarm read", t->time.tm_sec, t->time.tm_min,
543 t->time.tm_hour, t->time.tm_mday,
544 t->enabled, t->pending);
545
546 return 0;
547}
548
549static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
550{
551 struct ds1307 *ds1307 = dev_get_drvdata(dev);
552 unsigned char regs[9];
553 u8 control, status;
554 int ret;
555
556 if (!test_bit(HAS_ALARM, &ds1307->flags))
557 return -EINVAL;
558
559 dev_dbg(dev, "%s secs=%d, mins=%d, "
560 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
561 "alarm set", t->time.tm_sec, t->time.tm_min,
562 t->time.tm_hour, t->time.tm_mday,
563 t->enabled, t->pending);
564
565
566 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
567 sizeof(regs));
568 if (ret) {
569 dev_err(dev, "%s error %d\n", "alarm write", ret);
570 return ret;
571 }
572 control = regs[7];
573 status = regs[8];
574
575 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
576 ®s[0], ®s[4], control, status);
577
578
579 regs[0] = bin2bcd(t->time.tm_sec);
580 regs[1] = bin2bcd(t->time.tm_min);
581 regs[2] = bin2bcd(t->time.tm_hour);
582 regs[3] = bin2bcd(t->time.tm_mday);
583
584
585 regs[4] = 0;
586 regs[5] = 0;
587 regs[6] = 0;
588
589
590 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
591 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
592
593 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
594 sizeof(regs));
595 if (ret) {
596 dev_err(dev, "can't set alarm time\n");
597 return ret;
598 }
599
600
601 if (t->enabled) {
602 dev_dbg(dev, "alarm IRQ armed\n");
603 regs[7] |= DS1337_BIT_A1IE;
604 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
605 }
606
607 return 0;
608}
609
610static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
611{
612 struct ds1307 *ds1307 = dev_get_drvdata(dev);
613
614 if (!test_bit(HAS_ALARM, &ds1307->flags))
615 return -ENOTTY;
616
617 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
618 DS1337_BIT_A1IE,
619 enabled ? DS1337_BIT_A1IE : 0);
620}
621
622static const struct rtc_class_ops ds13xx_rtc_ops = {
623 .read_time = ds1307_get_time,
624 .set_time = ds1307_set_time,
625 .read_alarm = ds1337_read_alarm,
626 .set_alarm = ds1337_set_alarm,
627 .alarm_irq_enable = ds1307_alarm_irq_enable,
628};
629
630
631
632
633
634
635
636#define RX8130_REG_ALARM_MIN 0x07
637#define RX8130_REG_ALARM_HOUR 0x08
638#define RX8130_REG_ALARM_WEEK_OR_DAY 0x09
639#define RX8130_REG_EXTENSION 0x0c
640#define RX8130_REG_EXTENSION_WADA BIT(3)
641#define RX8130_REG_FLAG 0x0d
642#define RX8130_REG_FLAG_AF BIT(3)
643#define RX8130_REG_CONTROL0 0x0e
644#define RX8130_REG_CONTROL0_AIE BIT(3)
645
646static irqreturn_t rx8130_irq(int irq, void *dev_id)
647{
648 struct ds1307 *ds1307 = dev_id;
649 struct mutex *lock = &ds1307->rtc->ops_lock;
650 u8 ctl[3];
651 int ret;
652
653 mutex_lock(lock);
654
655
656 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
657 sizeof(ctl));
658 if (ret < 0)
659 goto out;
660 if (!(ctl[1] & RX8130_REG_FLAG_AF))
661 goto out;
662 ctl[1] &= ~RX8130_REG_FLAG_AF;
663 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
664
665 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
666 sizeof(ctl));
667 if (ret < 0)
668 goto out;
669
670 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
671
672out:
673 mutex_unlock(lock);
674
675 return IRQ_HANDLED;
676}
677
678static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
679{
680 struct ds1307 *ds1307 = dev_get_drvdata(dev);
681 u8 ald[3], ctl[3];
682 int ret;
683
684 if (!test_bit(HAS_ALARM, &ds1307->flags))
685 return -EINVAL;
686
687
688 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
689 sizeof(ald));
690 if (ret < 0)
691 return ret;
692
693
694 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
695 sizeof(ctl));
696 if (ret < 0)
697 return ret;
698
699 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
700 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
701
702
703 t->time.tm_sec = -1;
704 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
705 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
706 t->time.tm_wday = -1;
707 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
708 t->time.tm_mon = -1;
709 t->time.tm_year = -1;
710 t->time.tm_yday = -1;
711 t->time.tm_isdst = -1;
712
713 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
714 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
715 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
716
717 return 0;
718}
719
720static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
721{
722 struct ds1307 *ds1307 = dev_get_drvdata(dev);
723 u8 ald[3], ctl[3];
724 int ret;
725
726 if (!test_bit(HAS_ALARM, &ds1307->flags))
727 return -EINVAL;
728
729 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
730 "enabled=%d pending=%d\n", __func__,
731 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
732 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
733 t->enabled, t->pending);
734
735
736 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
737 sizeof(ctl));
738 if (ret < 0)
739 return ret;
740
741 ctl[0] &= ~RX8130_REG_EXTENSION_WADA;
742 ctl[1] |= RX8130_REG_FLAG_AF;
743 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
744
745 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
746 sizeof(ctl));
747 if (ret < 0)
748 return ret;
749
750
751 ald[0] = bin2bcd(t->time.tm_min);
752 ald[1] = bin2bcd(t->time.tm_hour);
753 ald[2] = bin2bcd(t->time.tm_mday);
754
755 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
756 sizeof(ald));
757 if (ret < 0)
758 return ret;
759
760 if (!t->enabled)
761 return 0;
762
763 ctl[2] |= RX8130_REG_CONTROL0_AIE;
764
765 return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
766 sizeof(ctl));
767}
768
769static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
770{
771 struct ds1307 *ds1307 = dev_get_drvdata(dev);
772 int ret, reg;
773
774 if (!test_bit(HAS_ALARM, &ds1307->flags))
775 return -EINVAL;
776
777 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
778 if (ret < 0)
779 return ret;
780
781 if (enabled)
782 reg |= RX8130_REG_CONTROL0_AIE;
783 else
784 reg &= ~RX8130_REG_CONTROL0_AIE;
785
786 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
787}
788
789
790
791
792
793
794
795#define MCP794XX_REG_CONTROL 0x07
796# define MCP794XX_BIT_ALM0_EN 0x10
797# define MCP794XX_BIT_ALM1_EN 0x20
798#define MCP794XX_REG_ALARM0_BASE 0x0a
799#define MCP794XX_REG_ALARM0_CTRL 0x0d
800#define MCP794XX_REG_ALARM1_BASE 0x11
801#define MCP794XX_REG_ALARM1_CTRL 0x14
802# define MCP794XX_BIT_ALMX_IF BIT(3)
803# define MCP794XX_BIT_ALMX_C0 BIT(4)
804# define MCP794XX_BIT_ALMX_C1 BIT(5)
805# define MCP794XX_BIT_ALMX_C2 BIT(6)
806# define MCP794XX_BIT_ALMX_POL BIT(7)
807# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
808 MCP794XX_BIT_ALMX_C1 | \
809 MCP794XX_BIT_ALMX_C2)
810
811static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
812{
813 struct ds1307 *ds1307 = dev_id;
814 struct mutex *lock = &ds1307->rtc->ops_lock;
815 int reg, ret;
816
817 mutex_lock(lock);
818
819
820 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
821 if (ret)
822 goto out;
823 if (!(reg & MCP794XX_BIT_ALMX_IF))
824 goto out;
825 reg &= ~MCP794XX_BIT_ALMX_IF;
826 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
827 if (ret)
828 goto out;
829
830
831 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
832 MCP794XX_BIT_ALM0_EN, 0);
833 if (ret)
834 goto out;
835
836 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
837
838out:
839 mutex_unlock(lock);
840
841 return IRQ_HANDLED;
842}
843
844static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
845{
846 struct ds1307 *ds1307 = dev_get_drvdata(dev);
847 u8 regs[10];
848 int ret;
849
850 if (!test_bit(HAS_ALARM, &ds1307->flags))
851 return -EINVAL;
852
853
854 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
855 sizeof(regs));
856 if (ret)
857 return ret;
858
859 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
860
861
862 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
863 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
864 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
865 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
866 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
867 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
868 t->time.tm_year = -1;
869 t->time.tm_yday = -1;
870 t->time.tm_isdst = -1;
871
872 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
873 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
874 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
875 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
876 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
877 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
878 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
879
880 return 0;
881}
882
883
884
885
886
887static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
888{
889 struct rtc_time tm_now;
890 int days_now, days_alarm, ret;
891
892 ret = ds1307_get_time(dev, &tm_now);
893 if (ret)
894 return ret;
895
896 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
897 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
898
899 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
900}
901
902static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
903{
904 struct ds1307 *ds1307 = dev_get_drvdata(dev);
905 unsigned char regs[10];
906 int wday, ret;
907
908 if (!test_bit(HAS_ALARM, &ds1307->flags))
909 return -EINVAL;
910
911 wday = mcp794xx_alm_weekday(dev, &t->time);
912 if (wday < 0)
913 return wday;
914
915 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
916 "enabled=%d pending=%d\n", __func__,
917 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
918 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
919 t->enabled, t->pending);
920
921
922 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
923 sizeof(regs));
924 if (ret)
925 return ret;
926
927
928 regs[3] = bin2bcd(t->time.tm_sec);
929 regs[4] = bin2bcd(t->time.tm_min);
930 regs[5] = bin2bcd(t->time.tm_hour);
931 regs[6] = wday;
932 regs[7] = bin2bcd(t->time.tm_mday);
933 regs[8] = bin2bcd(t->time.tm_mon + 1);
934
935
936 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
937
938 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
939
940 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
941
942 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
943 sizeof(regs));
944 if (ret)
945 return ret;
946
947 if (!t->enabled)
948 return 0;
949 regs[0] |= MCP794XX_BIT_ALM0_EN;
950 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
951}
952
953static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
954{
955 struct ds1307 *ds1307 = dev_get_drvdata(dev);
956
957 if (!test_bit(HAS_ALARM, &ds1307->flags))
958 return -EINVAL;
959
960 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
961 MCP794XX_BIT_ALM0_EN,
962 enabled ? MCP794XX_BIT_ALM0_EN : 0);
963}
964
965
966
967static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
968 size_t bytes)
969{
970 struct ds1307 *ds1307 = priv;
971 const struct chip_desc *chip = &chips[ds1307->type];
972
973 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
974 val, bytes);
975}
976
977static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
978 size_t bytes)
979{
980 struct ds1307 *ds1307 = priv;
981 const struct chip_desc *chip = &chips[ds1307->type];
982
983 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
984 val, bytes);
985}
986
987
988
989static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
990 u32 ohms, bool diode)
991{
992 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
993 DS1307_TRICKLE_CHARGER_NO_DIODE;
994
995 switch (ohms) {
996 case 250:
997 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
998 break;
999 case 2000:
1000 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
1001 break;
1002 case 4000:
1003 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
1004 break;
1005 default:
1006 dev_warn(ds1307->dev,
1007 "Unsupported ohm value %u in dt\n", ohms);
1008 return 0;
1009 }
1010 return setup;
1011}
1012
1013static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1014 const struct chip_desc *chip)
1015{
1016 u32 ohms;
1017 bool diode = true;
1018
1019 if (!chip->do_trickle_setup)
1020 return 0;
1021
1022 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1023 &ohms))
1024 return 0;
1025
1026 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1027 diode = false;
1028
1029 return chip->do_trickle_setup(ds1307, ohms, diode);
1030}
1031
1032
1033
1034#ifdef CONFIG_RTC_DRV_DS1307_HWMON
1035
1036
1037
1038
1039
1040#define DS3231_REG_TEMPERATURE 0x11
1041
1042
1043
1044
1045
1046static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1047{
1048 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1049 u8 temp_buf[2];
1050 s16 temp;
1051 int ret;
1052
1053 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1054 temp_buf, sizeof(temp_buf));
1055 if (ret)
1056 return ret;
1057
1058
1059
1060
1061 temp = (temp_buf[0] << 8) | temp_buf[1];
1062 temp >>= 6;
1063 *mC = temp * 250;
1064
1065 return 0;
1066}
1067
1068static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1069 struct device_attribute *attr, char *buf)
1070{
1071 int ret;
1072 s32 temp;
1073
1074 ret = ds3231_hwmon_read_temp(dev, &temp);
1075 if (ret)
1076 return ret;
1077
1078 return sprintf(buf, "%d\n", temp);
1079}
1080static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1081 NULL, 0);
1082
1083static struct attribute *ds3231_hwmon_attrs[] = {
1084 &sensor_dev_attr_temp1_input.dev_attr.attr,
1085 NULL,
1086};
1087ATTRIBUTE_GROUPS(ds3231_hwmon);
1088
1089static void ds1307_hwmon_register(struct ds1307 *ds1307)
1090{
1091 struct device *dev;
1092
1093 if (ds1307->type != ds_3231)
1094 return;
1095
1096 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1097 ds1307,
1098 ds3231_hwmon_groups);
1099 if (IS_ERR(dev)) {
1100 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1101 PTR_ERR(dev));
1102 }
1103}
1104
1105#else
1106
1107static void ds1307_hwmon_register(struct ds1307 *ds1307)
1108{
1109}
1110
1111#endif
1112
1113
1114
1115
1116
1117
1118
1119#ifdef CONFIG_COMMON_CLK
1120
1121enum {
1122 DS3231_CLK_SQW = 0,
1123 DS3231_CLK_32KHZ,
1124};
1125
1126#define clk_sqw_to_ds1307(clk) \
1127 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1128#define clk_32khz_to_ds1307(clk) \
1129 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1130
1131static int ds3231_clk_sqw_rates[] = {
1132 1,
1133 1024,
1134 4096,
1135 8192,
1136};
1137
1138static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1139{
1140 struct mutex *lock = &ds1307->rtc->ops_lock;
1141 int ret;
1142
1143 mutex_lock(lock);
1144 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1145 mask, value);
1146 mutex_unlock(lock);
1147
1148 return ret;
1149}
1150
1151static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1152 unsigned long parent_rate)
1153{
1154 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1155 int control, ret;
1156 int rate_sel = 0;
1157
1158 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1159 if (ret)
1160 return ret;
1161 if (control & DS1337_BIT_RS1)
1162 rate_sel += 1;
1163 if (control & DS1337_BIT_RS2)
1164 rate_sel += 2;
1165
1166 return ds3231_clk_sqw_rates[rate_sel];
1167}
1168
1169static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1170 unsigned long *prate)
1171{
1172 int i;
1173
1174 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1175 if (ds3231_clk_sqw_rates[i] <= rate)
1176 return ds3231_clk_sqw_rates[i];
1177 }
1178
1179 return 0;
1180}
1181
1182static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1183 unsigned long parent_rate)
1184{
1185 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1186 int control = 0;
1187 int rate_sel;
1188
1189 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1190 rate_sel++) {
1191 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1192 break;
1193 }
1194
1195 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1196 return -EINVAL;
1197
1198 if (rate_sel & 1)
1199 control |= DS1337_BIT_RS1;
1200 if (rate_sel & 2)
1201 control |= DS1337_BIT_RS2;
1202
1203 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1204 control);
1205}
1206
1207static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1208{
1209 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1210
1211 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1212}
1213
1214static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1215{
1216 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1217
1218 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1219}
1220
1221static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1222{
1223 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1224 int control, ret;
1225
1226 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1227 if (ret)
1228 return ret;
1229
1230 return !(control & DS1337_BIT_INTCN);
1231}
1232
1233static const struct clk_ops ds3231_clk_sqw_ops = {
1234 .prepare = ds3231_clk_sqw_prepare,
1235 .unprepare = ds3231_clk_sqw_unprepare,
1236 .is_prepared = ds3231_clk_sqw_is_prepared,
1237 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1238 .round_rate = ds3231_clk_sqw_round_rate,
1239 .set_rate = ds3231_clk_sqw_set_rate,
1240};
1241
1242static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1243 unsigned long parent_rate)
1244{
1245 return 32768;
1246}
1247
1248static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1249{
1250 struct mutex *lock = &ds1307->rtc->ops_lock;
1251 int ret;
1252
1253 mutex_lock(lock);
1254 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1255 DS3231_BIT_EN32KHZ,
1256 enable ? DS3231_BIT_EN32KHZ : 0);
1257 mutex_unlock(lock);
1258
1259 return ret;
1260}
1261
1262static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1263{
1264 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1265
1266 return ds3231_clk_32khz_control(ds1307, true);
1267}
1268
1269static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1270{
1271 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1272
1273 ds3231_clk_32khz_control(ds1307, false);
1274}
1275
1276static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1277{
1278 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1279 int status, ret;
1280
1281 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1282 if (ret)
1283 return ret;
1284
1285 return !!(status & DS3231_BIT_EN32KHZ);
1286}
1287
1288static const struct clk_ops ds3231_clk_32khz_ops = {
1289 .prepare = ds3231_clk_32khz_prepare,
1290 .unprepare = ds3231_clk_32khz_unprepare,
1291 .is_prepared = ds3231_clk_32khz_is_prepared,
1292 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1293};
1294
1295static struct clk_init_data ds3231_clks_init[] = {
1296 [DS3231_CLK_SQW] = {
1297 .name = "ds3231_clk_sqw",
1298 .ops = &ds3231_clk_sqw_ops,
1299 },
1300 [DS3231_CLK_32KHZ] = {
1301 .name = "ds3231_clk_32khz",
1302 .ops = &ds3231_clk_32khz_ops,
1303 },
1304};
1305
1306static int ds3231_clks_register(struct ds1307 *ds1307)
1307{
1308 struct device_node *node = ds1307->dev->of_node;
1309 struct clk_onecell_data *onecell;
1310 int i;
1311
1312 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1313 if (!onecell)
1314 return -ENOMEM;
1315
1316 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1317 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1318 sizeof(onecell->clks[0]), GFP_KERNEL);
1319 if (!onecell->clks)
1320 return -ENOMEM;
1321
1322 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1323 struct clk_init_data init = ds3231_clks_init[i];
1324
1325
1326
1327
1328
1329 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1330 continue;
1331
1332
1333 of_property_read_string_index(node, "clock-output-names", i,
1334 &init.name);
1335 ds1307->clks[i].init = &init;
1336
1337 onecell->clks[i] = devm_clk_register(ds1307->dev,
1338 &ds1307->clks[i]);
1339 if (IS_ERR(onecell->clks[i]))
1340 return PTR_ERR(onecell->clks[i]);
1341 }
1342
1343 if (!node)
1344 return 0;
1345
1346 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1347
1348 return 0;
1349}
1350
1351static void ds1307_clks_register(struct ds1307 *ds1307)
1352{
1353 int ret;
1354
1355 if (ds1307->type != ds_3231)
1356 return;
1357
1358 ret = ds3231_clks_register(ds1307);
1359 if (ret) {
1360 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1361 ret);
1362 }
1363}
1364
1365#else
1366
1367static void ds1307_clks_register(struct ds1307 *ds1307)
1368{
1369}
1370
1371#endif
1372
1373static const struct regmap_config regmap_config = {
1374 .reg_bits = 8,
1375 .val_bits = 8,
1376};
1377
1378static int ds1307_probe(struct i2c_client *client,
1379 const struct i2c_device_id *id)
1380{
1381 struct ds1307 *ds1307;
1382 int err = -ENODEV;
1383 int tmp;
1384 const struct chip_desc *chip;
1385 bool want_irq;
1386 bool ds1307_can_wakeup_device = false;
1387 unsigned char regs[8];
1388 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1389 u8 trickle_charger_setup = 0;
1390
1391 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1392 if (!ds1307)
1393 return -ENOMEM;
1394
1395 dev_set_drvdata(&client->dev, ds1307);
1396 ds1307->dev = &client->dev;
1397 ds1307->name = client->name;
1398
1399 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
1400 if (IS_ERR(ds1307->regmap)) {
1401 dev_err(ds1307->dev, "regmap allocation failed\n");
1402 return PTR_ERR(ds1307->regmap);
1403 }
1404
1405 i2c_set_clientdata(client, ds1307);
1406
1407 if (client->dev.of_node) {
1408 ds1307->type = (enum ds_type)
1409 of_device_get_match_data(&client->dev);
1410 chip = &chips[ds1307->type];
1411 } else if (id) {
1412 chip = &chips[id->driver_data];
1413 ds1307->type = id->driver_data;
1414 } else {
1415 const struct acpi_device_id *acpi_id;
1416
1417 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1418 ds1307->dev);
1419 if (!acpi_id)
1420 return -ENODEV;
1421 chip = &chips[acpi_id->driver_data];
1422 ds1307->type = acpi_id->driver_data;
1423 }
1424
1425 want_irq = client->irq > 0 && chip->alarm;
1426
1427 if (!pdata)
1428 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1429 else if (pdata->trickle_charger_setup)
1430 trickle_charger_setup = pdata->trickle_charger_setup;
1431
1432 if (trickle_charger_setup && chip->trickle_charger_reg) {
1433 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1434 dev_dbg(ds1307->dev,
1435 "writing trickle charger info 0x%x to 0x%x\n",
1436 trickle_charger_setup, chip->trickle_charger_reg);
1437 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1438 trickle_charger_setup);
1439 }
1440
1441#ifdef CONFIG_OF
1442
1443
1444
1445
1446
1447
1448
1449
1450 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1451 "wakeup-source"))
1452 ds1307_can_wakeup_device = true;
1453#endif
1454
1455 switch (ds1307->type) {
1456 case ds_1337:
1457 case ds_1339:
1458 case ds_1341:
1459 case ds_3231:
1460
1461 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1462 regs, 2);
1463 if (err) {
1464 dev_dbg(ds1307->dev, "read error %d\n", err);
1465 goto exit;
1466 }
1467
1468
1469 if (regs[0] & DS1337_BIT_nEOSC)
1470 regs[0] &= ~DS1337_BIT_nEOSC;
1471
1472
1473
1474
1475
1476
1477
1478 if (want_irq || ds1307_can_wakeup_device) {
1479 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1480 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1481 }
1482
1483 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1484 regs[0]);
1485
1486
1487 if (regs[1] & DS1337_BIT_OSF) {
1488 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1489 regs[1] & ~DS1337_BIT_OSF);
1490 dev_warn(ds1307->dev, "SET TIME!\n");
1491 }
1492 break;
1493
1494 case rx_8025:
1495 err = regmap_bulk_read(ds1307->regmap,
1496 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1497 if (err) {
1498 dev_dbg(ds1307->dev, "read error %d\n", err);
1499 goto exit;
1500 }
1501
1502
1503 if (!(regs[1] & RX8025_BIT_XST)) {
1504 regs[1] |= RX8025_BIT_XST;
1505 regmap_write(ds1307->regmap,
1506 RX8025_REG_CTRL2 << 4 | 0x08,
1507 regs[1]);
1508 dev_warn(ds1307->dev,
1509 "oscillator stop detected - SET TIME!\n");
1510 }
1511
1512 if (regs[1] & RX8025_BIT_PON) {
1513 regs[1] &= ~RX8025_BIT_PON;
1514 regmap_write(ds1307->regmap,
1515 RX8025_REG_CTRL2 << 4 | 0x08,
1516 regs[1]);
1517 dev_warn(ds1307->dev, "power-on detected\n");
1518 }
1519
1520 if (regs[1] & RX8025_BIT_VDET) {
1521 regs[1] &= ~RX8025_BIT_VDET;
1522 regmap_write(ds1307->regmap,
1523 RX8025_REG_CTRL2 << 4 | 0x08,
1524 regs[1]);
1525 dev_warn(ds1307->dev, "voltage drop detected\n");
1526 }
1527
1528
1529 if (!(regs[0] & RX8025_BIT_2412)) {
1530 u8 hour;
1531
1532
1533 regmap_write(ds1307->regmap,
1534 RX8025_REG_CTRL1 << 4 | 0x08,
1535 regs[0] | RX8025_BIT_2412);
1536
1537 err = regmap_bulk_read(ds1307->regmap,
1538 RX8025_REG_CTRL1 << 4 | 0x08,
1539 regs, 2);
1540 if (err) {
1541 dev_dbg(ds1307->dev, "read error %d\n", err);
1542 goto exit;
1543 }
1544
1545
1546 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1547 if (hour == 12)
1548 hour = 0;
1549 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1550 hour += 12;
1551
1552 regmap_write(ds1307->regmap,
1553 DS1307_REG_HOUR << 4 | 0x08, hour);
1554 }
1555 break;
1556 default:
1557 break;
1558 }
1559
1560read_rtc:
1561
1562 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1563 sizeof(regs));
1564 if (err) {
1565 dev_dbg(ds1307->dev, "read error %d\n", err);
1566 goto exit;
1567 }
1568
1569
1570
1571
1572
1573
1574 tmp = regs[DS1307_REG_SECS];
1575 switch (ds1307->type) {
1576 case ds_1307:
1577 case m41t0:
1578 case m41t00:
1579
1580 if (tmp & DS1307_BIT_CH) {
1581 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1582 dev_warn(ds1307->dev, "SET TIME!\n");
1583 goto read_rtc;
1584 }
1585 break;
1586 case ds_1308:
1587 case ds_1338:
1588
1589 if (tmp & DS1307_BIT_CH)
1590 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1591
1592
1593 if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1594 regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1595 regs[DS1307_REG_CONTROL] &
1596 ~DS1338_BIT_OSF);
1597 dev_warn(ds1307->dev, "SET TIME!\n");
1598 goto read_rtc;
1599 }
1600 break;
1601 case ds_1340:
1602
1603 if (tmp & DS1340_BIT_nEOSC)
1604 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1605
1606 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1607 if (err) {
1608 dev_dbg(ds1307->dev, "read error %d\n", err);
1609 goto exit;
1610 }
1611
1612
1613 if (tmp & DS1340_BIT_OSF) {
1614 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1615 dev_warn(ds1307->dev, "SET TIME!\n");
1616 }
1617 break;
1618 case mcp794xx:
1619
1620 if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1621 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1622 regs[DS1307_REG_WDAY] |
1623 MCP794XX_BIT_VBATEN);
1624 }
1625
1626
1627 if (!(tmp & MCP794XX_BIT_ST)) {
1628 regmap_write(ds1307->regmap, DS1307_REG_SECS,
1629 MCP794XX_BIT_ST);
1630 dev_warn(ds1307->dev, "SET TIME!\n");
1631 goto read_rtc;
1632 }
1633
1634 break;
1635 default:
1636 break;
1637 }
1638
1639 tmp = regs[DS1307_REG_HOUR];
1640 switch (ds1307->type) {
1641 case ds_1340:
1642 case m41t0:
1643 case m41t00:
1644
1645
1646
1647
1648 break;
1649 case rx_8025:
1650 break;
1651 default:
1652 if (!(tmp & DS1307_BIT_12HR))
1653 break;
1654
1655
1656
1657
1658
1659 tmp = bcd2bin(tmp & 0x1f);
1660 if (tmp == 12)
1661 tmp = 0;
1662 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1663 tmp += 12;
1664 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1665 bin2bcd(tmp));
1666 }
1667
1668 if (want_irq || ds1307_can_wakeup_device) {
1669 device_set_wakeup_capable(ds1307->dev, true);
1670 set_bit(HAS_ALARM, &ds1307->flags);
1671 }
1672
1673 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1674 if (IS_ERR(ds1307->rtc))
1675 return PTR_ERR(ds1307->rtc);
1676
1677 if (ds1307_can_wakeup_device && !want_irq) {
1678 dev_info(ds1307->dev,
1679 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1680
1681 ds1307->rtc->uie_unsupported = 1;
1682 }
1683
1684 if (want_irq) {
1685 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1686 chip->irq_handler ?: ds1307_irq,
1687 IRQF_SHARED | IRQF_ONESHOT,
1688 ds1307->name, ds1307);
1689 if (err) {
1690 client->irq = 0;
1691 device_set_wakeup_capable(ds1307->dev, false);
1692 clear_bit(HAS_ALARM, &ds1307->flags);
1693 dev_err(ds1307->dev, "unable to request IRQ!\n");
1694 } else {
1695 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1696 }
1697 }
1698
1699 if (chip->nvram_size) {
1700 ds1307->nvmem_cfg.name = "ds1307_nvram";
1701 ds1307->nvmem_cfg.word_size = 1;
1702 ds1307->nvmem_cfg.stride = 1;
1703 ds1307->nvmem_cfg.size = chip->nvram_size;
1704 ds1307->nvmem_cfg.reg_read = ds1307_nvram_read;
1705 ds1307->nvmem_cfg.reg_write = ds1307_nvram_write;
1706 ds1307->nvmem_cfg.priv = ds1307;
1707
1708 ds1307->rtc->nvmem_config = &ds1307->nvmem_cfg;
1709 ds1307->rtc->nvram_old_abi = true;
1710 }
1711
1712 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1713 err = rtc_register_device(ds1307->rtc);
1714 if (err)
1715 return err;
1716
1717 ds1307_hwmon_register(ds1307);
1718 ds1307_clks_register(ds1307);
1719
1720 return 0;
1721
1722exit:
1723 return err;
1724}
1725
1726static struct i2c_driver ds1307_driver = {
1727 .driver = {
1728 .name = "rtc-ds1307",
1729 .of_match_table = of_match_ptr(ds1307_of_match),
1730 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1731 },
1732 .probe = ds1307_probe,
1733 .id_table = ds1307_id,
1734};
1735
1736module_i2c_driver(ds1307_driver);
1737
1738MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1739MODULE_LICENSE("GPL");
1740
