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24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/idr.h>
28#include <linux/interrupt.h>
29#include <linux/module.h>
30#include <linux/kthread.h>
31#include <linux/pci.h>
32#include <linux/spinlock.h>
33#include <linux/ctype.h>
34#include <linux/aer.h>
35#include <linux/slab.h>
36#include <linux/firmware.h>
37#include <linux/miscdevice.h>
38#include <linux/percpu.h>
39#include <linux/msi.h>
40#include <linux/bitops.h>
41
42#include <scsi/scsi.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_transport_fc.h>
46#include <scsi/scsi_tcq.h>
47#include <scsi/fc/fc_fs.h>
48
49#include <linux/nvme-fc-driver.h>
50
51#include "lpfc_hw4.h"
52#include "lpfc_hw.h"
53#include "lpfc_sli.h"
54#include "lpfc_sli4.h"
55#include "lpfc_nl.h"
56#include "lpfc_disc.h"
57#include "lpfc.h"
58#include "lpfc_scsi.h"
59#include "lpfc_nvme.h"
60#include "lpfc_nvmet.h"
61#include "lpfc_logmsg.h"
62#include "lpfc_crtn.h"
63#include "lpfc_vport.h"
64#include "lpfc_version.h"
65#include "lpfc_ids.h"
66
67char *_dump_buf_data;
68unsigned long _dump_buf_data_order;
69char *_dump_buf_dif;
70unsigned long _dump_buf_dif_order;
71spinlock_t _dump_buf_lock;
72
73
74uint16_t *lpfc_used_cpu;
75uint32_t lpfc_present_cpu;
76
77static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
78static int lpfc_post_rcv_buf(struct lpfc_hba *);
79static int lpfc_sli4_queue_verify(struct lpfc_hba *);
80static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
81static int lpfc_setup_endian_order(struct lpfc_hba *);
82static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
83static void lpfc_free_els_sgl_list(struct lpfc_hba *);
84static void lpfc_free_nvmet_sgl_list(struct lpfc_hba *);
85static void lpfc_init_sgl_list(struct lpfc_hba *);
86static int lpfc_init_active_sgl_array(struct lpfc_hba *);
87static void lpfc_free_active_sgl(struct lpfc_hba *);
88static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
89static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
90static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
91static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
92static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
93static void lpfc_sli4_disable_intr(struct lpfc_hba *);
94static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
95static void lpfc_sli4_oas_verify(struct lpfc_hba *phba);
96
97static struct scsi_transport_template *lpfc_transport_template = NULL;
98static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
99static DEFINE_IDR(lpfc_hba_index);
100#define LPFC_NVMET_BUF_POST 254
101
102
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113
114
115
116int
117lpfc_config_port_prep(struct lpfc_hba *phba)
118{
119 lpfc_vpd_t *vp = &phba->vpd;
120 int i = 0, rc;
121 LPFC_MBOXQ_t *pmb;
122 MAILBOX_t *mb;
123 char *lpfc_vpd_data = NULL;
124 uint16_t offset = 0;
125 static char licensed[56] =
126 "key unlock for use with gnu public licensed code only\0";
127 static int init_key = 1;
128
129 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
130 if (!pmb) {
131 phba->link_state = LPFC_HBA_ERROR;
132 return -ENOMEM;
133 }
134
135 mb = &pmb->u.mb;
136 phba->link_state = LPFC_INIT_MBX_CMDS;
137
138 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
139 if (init_key) {
140 uint32_t *ptext = (uint32_t *) licensed;
141
142 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
143 *ptext = cpu_to_be32(*ptext);
144 init_key = 0;
145 }
146
147 lpfc_read_nv(phba, pmb);
148 memset((char*)mb->un.varRDnvp.rsvd3, 0,
149 sizeof (mb->un.varRDnvp.rsvd3));
150 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
151 sizeof (licensed));
152
153 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
154
155 if (rc != MBX_SUCCESS) {
156 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
157 "0324 Config Port initialization "
158 "error, mbxCmd x%x READ_NVPARM, "
159 "mbxStatus x%x\n",
160 mb->mbxCommand, mb->mbxStatus);
161 mempool_free(pmb, phba->mbox_mem_pool);
162 return -ERESTART;
163 }
164 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
165 sizeof(phba->wwnn));
166 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
167 sizeof(phba->wwpn));
168 }
169
170 phba->sli3_options = 0x0;
171
172
173 lpfc_read_rev(phba, pmb);
174 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
175 if (rc != MBX_SUCCESS) {
176 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
177 "0439 Adapter failed to init, mbxCmd x%x "
178 "READ_REV, mbxStatus x%x\n",
179 mb->mbxCommand, mb->mbxStatus);
180 mempool_free( pmb, phba->mbox_mem_pool);
181 return -ERESTART;
182 }
183
184
185
186
187
188
189 if (mb->un.varRdRev.rr == 0) {
190 vp->rev.rBit = 0;
191 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
192 "0440 Adapter failed to init, READ_REV has "
193 "missing revision information.\n");
194 mempool_free(pmb, phba->mbox_mem_pool);
195 return -ERESTART;
196 }
197
198 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
199 mempool_free(pmb, phba->mbox_mem_pool);
200 return -EINVAL;
201 }
202
203
204 vp->rev.rBit = 1;
205 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
206 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
207 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
208 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
209 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
210 vp->rev.biuRev = mb->un.varRdRev.biuRev;
211 vp->rev.smRev = mb->un.varRdRev.smRev;
212 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
213 vp->rev.endecRev = mb->un.varRdRev.endecRev;
214 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
215 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
216 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
217 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
218 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
219 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
220
221
222
223
224
225 if (vp->rev.feaLevelHigh < 9)
226 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
227
228 if (lpfc_is_LC_HBA(phba->pcidev->device))
229 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
230 sizeof (phba->RandomData));
231
232
233 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
234 if (!lpfc_vpd_data)
235 goto out_free_mbox;
236 do {
237 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
238 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
239
240 if (rc != MBX_SUCCESS) {
241 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
242 "0441 VPD not present on adapter, "
243 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
244 mb->mbxCommand, mb->mbxStatus);
245 mb->un.varDmp.word_cnt = 0;
246 }
247
248
249
250 if (mb->un.varDmp.word_cnt == 0)
251 break;
252 if (mb->un.varDmp.word_cnt > DMP_VPD_SIZE - offset)
253 mb->un.varDmp.word_cnt = DMP_VPD_SIZE - offset;
254 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
255 lpfc_vpd_data + offset,
256 mb->un.varDmp.word_cnt);
257 offset += mb->un.varDmp.word_cnt;
258 } while (mb->un.varDmp.word_cnt && offset < DMP_VPD_SIZE);
259 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
260
261 kfree(lpfc_vpd_data);
262out_free_mbox:
263 mempool_free(pmb, phba->mbox_mem_pool);
264 return 0;
265}
266
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273
274
275
276
277static void
278lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
279{
280 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
281 phba->temp_sensor_support = 1;
282 else
283 phba->temp_sensor_support = 0;
284 mempool_free(pmboxq, phba->mbox_mem_pool);
285 return;
286}
287
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295
296
297
298static void
299lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
300{
301 struct prog_id *prg;
302 uint32_t prog_id_word;
303 char dist = ' ';
304
305 char dist_char[] = "nabx";
306
307 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
308 mempool_free(pmboxq, phba->mbox_mem_pool);
309 return;
310 }
311
312 prg = (struct prog_id *) &prog_id_word;
313
314
315 prog_id_word = pmboxq->u.mb.un.varWords[7];
316
317
318 if (prg->dist < 4)
319 dist = dist_char[prg->dist];
320
321 if ((prg->dist == 3) && (prg->num == 0))
322 snprintf(phba->OptionROMVersion, 32, "%d.%d%d",
323 prg->ver, prg->rev, prg->lev);
324 else
325 snprintf(phba->OptionROMVersion, 32, "%d.%d%d%c%d",
326 prg->ver, prg->rev, prg->lev,
327 dist, prg->num);
328 mempool_free(pmboxq, phba->mbox_mem_pool);
329 return;
330}
331
332
333
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335
336
337
338
339
340
341void
342lpfc_update_vport_wwn(struct lpfc_vport *vport)
343{
344 uint8_t vvvl = vport->fc_sparam.cmn.valid_vendor_ver_level;
345 u32 *fawwpn_key = (u32 *)&vport->fc_sparam.un.vendorVersion[0];
346
347
348 if (vport->phba->cfg_soft_wwnn)
349 u64_to_wwn(vport->phba->cfg_soft_wwnn,
350 vport->fc_sparam.nodeName.u.wwn);
351 if (vport->phba->cfg_soft_wwpn)
352 u64_to_wwn(vport->phba->cfg_soft_wwpn,
353 vport->fc_sparam.portName.u.wwn);
354
355
356
357
358
359 if (vport->fc_nodename.u.wwn[0] == 0 || vport->phba->cfg_soft_wwnn)
360 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
361 sizeof(struct lpfc_name));
362 else
363 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
364 sizeof(struct lpfc_name));
365
366
367
368
369
370 if (vport->fc_portname.u.wwn[0] != 0 &&
371 memcmp(&vport->fc_portname, &vport->fc_sparam.portName,
372 sizeof(struct lpfc_name)))
373 vport->vport_flag |= FAWWPN_PARAM_CHG;
374
375 if (vport->fc_portname.u.wwn[0] == 0 ||
376 vport->phba->cfg_soft_wwpn ||
377 (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR) ||
378 vport->vport_flag & FAWWPN_SET) {
379 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
380 sizeof(struct lpfc_name));
381 vport->vport_flag &= ~FAWWPN_SET;
382 if (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR)
383 vport->vport_flag |= FAWWPN_SET;
384 }
385 else
386 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
387 sizeof(struct lpfc_name));
388}
389
390
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401
402
403int
404lpfc_config_port_post(struct lpfc_hba *phba)
405{
406 struct lpfc_vport *vport = phba->pport;
407 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
408 LPFC_MBOXQ_t *pmb;
409 MAILBOX_t *mb;
410 struct lpfc_dmabuf *mp;
411 struct lpfc_sli *psli = &phba->sli;
412 uint32_t status, timeout;
413 int i, j;
414 int rc;
415
416 spin_lock_irq(&phba->hbalock);
417
418
419
420
421 if (phba->over_temp_state == HBA_OVER_TEMP)
422 phba->over_temp_state = HBA_NORMAL_TEMP;
423 spin_unlock_irq(&phba->hbalock);
424
425 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
426 if (!pmb) {
427 phba->link_state = LPFC_HBA_ERROR;
428 return -ENOMEM;
429 }
430 mb = &pmb->u.mb;
431
432
433 rc = lpfc_read_sparam(phba, pmb, 0);
434 if (rc) {
435 mempool_free(pmb, phba->mbox_mem_pool);
436 return -ENOMEM;
437 }
438
439 pmb->vport = vport;
440 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
441 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
442 "0448 Adapter failed init, mbxCmd x%x "
443 "READ_SPARM mbxStatus x%x\n",
444 mb->mbxCommand, mb->mbxStatus);
445 phba->link_state = LPFC_HBA_ERROR;
446 mp = (struct lpfc_dmabuf *) pmb->context1;
447 mempool_free(pmb, phba->mbox_mem_pool);
448 lpfc_mbuf_free(phba, mp->virt, mp->phys);
449 kfree(mp);
450 return -EIO;
451 }
452
453 mp = (struct lpfc_dmabuf *) pmb->context1;
454
455 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
456 lpfc_mbuf_free(phba, mp->virt, mp->phys);
457 kfree(mp);
458 pmb->context1 = NULL;
459 lpfc_update_vport_wwn(vport);
460
461
462 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
463 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
464 fc_host_max_npiv_vports(shost) = phba->max_vpi;
465
466
467
468 if (phba->SerialNumber[0] == 0) {
469 uint8_t *outptr;
470
471 outptr = &vport->fc_nodename.u.s.IEEE[0];
472 for (i = 0; i < 12; i++) {
473 status = *outptr++;
474 j = ((status & 0xf0) >> 4);
475 if (j <= 9)
476 phba->SerialNumber[i] =
477 (char)((uint8_t) 0x30 + (uint8_t) j);
478 else
479 phba->SerialNumber[i] =
480 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
481 i++;
482 j = (status & 0xf);
483 if (j <= 9)
484 phba->SerialNumber[i] =
485 (char)((uint8_t) 0x30 + (uint8_t) j);
486 else
487 phba->SerialNumber[i] =
488 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
489 }
490 }
491
492 lpfc_read_config(phba, pmb);
493 pmb->vport = vport;
494 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
495 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
496 "0453 Adapter failed to init, mbxCmd x%x "
497 "READ_CONFIG, mbxStatus x%x\n",
498 mb->mbxCommand, mb->mbxStatus);
499 phba->link_state = LPFC_HBA_ERROR;
500 mempool_free( pmb, phba->mbox_mem_pool);
501 return -EIO;
502 }
503
504
505 lpfc_sli_read_link_ste(phba);
506
507
508 i = (mb->un.varRdConfig.max_xri + 1);
509 if (phba->cfg_hba_queue_depth > i) {
510 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
511 "3359 HBA queue depth changed from %d to %d\n",
512 phba->cfg_hba_queue_depth, i);
513 phba->cfg_hba_queue_depth = i;
514 }
515
516
517 i = (mb->un.varRdConfig.max_xri >> 3);
518 if (phba->pport->cfg_lun_queue_depth > i) {
519 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
520 "3360 LUN queue depth changed from %d to %d\n",
521 phba->pport->cfg_lun_queue_depth, i);
522 phba->pport->cfg_lun_queue_depth = i;
523 }
524
525 phba->lmt = mb->un.varRdConfig.lmt;
526
527
528 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
529
530 phba->link_state = LPFC_LINK_DOWN;
531
532
533 if (psli->sli3_ring[LPFC_EXTRA_RING].sli.sli3.cmdringaddr)
534 psli->sli3_ring[LPFC_EXTRA_RING].flag |= LPFC_STOP_IOCB_EVENT;
535 if (psli->sli3_ring[LPFC_FCP_RING].sli.sli3.cmdringaddr)
536 psli->sli3_ring[LPFC_FCP_RING].flag |= LPFC_STOP_IOCB_EVENT;
537
538
539 if (phba->sli_rev != 3)
540 lpfc_post_rcv_buf(phba);
541
542
543
544
545 if (phba->intr_type == MSIX) {
546 rc = lpfc_config_msi(phba, pmb);
547 if (rc) {
548 mempool_free(pmb, phba->mbox_mem_pool);
549 return -EIO;
550 }
551 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
552 if (rc != MBX_SUCCESS) {
553 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
554 "0352 Config MSI mailbox command "
555 "failed, mbxCmd x%x, mbxStatus x%x\n",
556 pmb->u.mb.mbxCommand,
557 pmb->u.mb.mbxStatus);
558 mempool_free(pmb, phba->mbox_mem_pool);
559 return -EIO;
560 }
561 }
562
563 spin_lock_irq(&phba->hbalock);
564
565 phba->hba_flag &= ~HBA_ERATT_HANDLED;
566
567
568 if (lpfc_readl(phba->HCregaddr, &status)) {
569 spin_unlock_irq(&phba->hbalock);
570 return -EIO;
571 }
572 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
573 if (psli->num_rings > 0)
574 status |= HC_R0INT_ENA;
575 if (psli->num_rings > 1)
576 status |= HC_R1INT_ENA;
577 if (psli->num_rings > 2)
578 status |= HC_R2INT_ENA;
579 if (psli->num_rings > 3)
580 status |= HC_R3INT_ENA;
581
582 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
583 (phba->cfg_poll & DISABLE_FCP_RING_INT))
584 status &= ~(HC_R0INT_ENA);
585
586 writel(status, phba->HCregaddr);
587 readl(phba->HCregaddr);
588 spin_unlock_irq(&phba->hbalock);
589
590
591 timeout = phba->fc_ratov * 2;
592 mod_timer(&vport->els_tmofunc,
593 jiffies + msecs_to_jiffies(1000 * timeout));
594
595 mod_timer(&phba->hb_tmofunc,
596 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
597 phba->hb_outstanding = 0;
598 phba->last_completion_time = jiffies;
599
600 mod_timer(&phba->eratt_poll,
601 jiffies + msecs_to_jiffies(1000 * phba->eratt_poll_interval));
602
603 if (phba->hba_flag & LINK_DISABLED) {
604 lpfc_printf_log(phba,
605 KERN_ERR, LOG_INIT,
606 "2598 Adapter Link is disabled.\n");
607 lpfc_down_link(phba, pmb);
608 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
609 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
610 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
611 lpfc_printf_log(phba,
612 KERN_ERR, LOG_INIT,
613 "2599 Adapter failed to issue DOWN_LINK"
614 " mbox command rc 0x%x\n", rc);
615
616 mempool_free(pmb, phba->mbox_mem_pool);
617 return -EIO;
618 }
619 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
620 mempool_free(pmb, phba->mbox_mem_pool);
621 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
622 if (rc)
623 return rc;
624 }
625
626 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
627 if (!pmb) {
628 phba->link_state = LPFC_HBA_ERROR;
629 return -ENOMEM;
630 }
631
632 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
633 pmb->mbox_cmpl = lpfc_config_async_cmpl;
634 pmb->vport = phba->pport;
635 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
636
637 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
638 lpfc_printf_log(phba,
639 KERN_ERR,
640 LOG_INIT,
641 "0456 Adapter failed to issue "
642 "ASYNCEVT_ENABLE mbox status x%x\n",
643 rc);
644 mempool_free(pmb, phba->mbox_mem_pool);
645 }
646
647
648 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
649 if (!pmb) {
650 phba->link_state = LPFC_HBA_ERROR;
651 return -ENOMEM;
652 }
653
654 lpfc_dump_wakeup_param(phba, pmb);
655 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
656 pmb->vport = phba->pport;
657 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
658
659 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
660 lpfc_printf_log(phba, KERN_ERR, LOG_INIT, "0435 Adapter failed "
661 "to get Option ROM version status x%x\n", rc);
662 mempool_free(pmb, phba->mbox_mem_pool);
663 }
664
665 return 0;
666}
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682static int
683lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
684{
685 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
686}
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703int
704lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
705 uint32_t flag)
706{
707 struct lpfc_vport *vport = phba->pport;
708 LPFC_MBOXQ_t *pmb;
709 MAILBOX_t *mb;
710 int rc;
711
712 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
713 if (!pmb) {
714 phba->link_state = LPFC_HBA_ERROR;
715 return -ENOMEM;
716 }
717 mb = &pmb->u.mb;
718 pmb->vport = vport;
719
720 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
721 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
722 !(phba->lmt & LMT_1Gb)) ||
723 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
724 !(phba->lmt & LMT_2Gb)) ||
725 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
726 !(phba->lmt & LMT_4Gb)) ||
727 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
728 !(phba->lmt & LMT_8Gb)) ||
729 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
730 !(phba->lmt & LMT_10Gb)) ||
731 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
732 !(phba->lmt & LMT_16Gb)) ||
733 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) &&
734 !(phba->lmt & LMT_32Gb))) {
735
736 lpfc_printf_log(phba, KERN_ERR, LOG_LINK_EVENT,
737 "1302 Invalid speed for this board:%d "
738 "Reset link speed to auto.\n",
739 phba->cfg_link_speed);
740 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
741 }
742 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
743 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
744 if (phba->sli_rev < LPFC_SLI_REV4)
745 lpfc_set_loopback_flag(phba);
746 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
747 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
748 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
749 "0498 Adapter failed to init, mbxCmd x%x "
750 "INIT_LINK, mbxStatus x%x\n",
751 mb->mbxCommand, mb->mbxStatus);
752 if (phba->sli_rev <= LPFC_SLI_REV3) {
753
754 writel(0, phba->HCregaddr);
755 readl(phba->HCregaddr);
756
757 writel(0xffffffff, phba->HAregaddr);
758 readl(phba->HAregaddr);
759 }
760 phba->link_state = LPFC_HBA_ERROR;
761 if (rc != MBX_BUSY || flag == MBX_POLL)
762 mempool_free(pmb, phba->mbox_mem_pool);
763 return -EIO;
764 }
765 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
766 if (flag == MBX_POLL)
767 mempool_free(pmb, phba->mbox_mem_pool);
768
769 return 0;
770}
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785static int
786lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
787{
788 LPFC_MBOXQ_t *pmb;
789 int rc;
790
791 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
792 if (!pmb) {
793 phba->link_state = LPFC_HBA_ERROR;
794 return -ENOMEM;
795 }
796
797 lpfc_printf_log(phba,
798 KERN_ERR, LOG_INIT,
799 "0491 Adapter Link is disabled.\n");
800 lpfc_down_link(phba, pmb);
801 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
802 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
803 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
804 lpfc_printf_log(phba,
805 KERN_ERR, LOG_INIT,
806 "2522 Adapter failed to issue DOWN_LINK"
807 " mbox command rc 0x%x\n", rc);
808
809 mempool_free(pmb, phba->mbox_mem_pool);
810 return -EIO;
811 }
812 if (flag == MBX_POLL)
813 mempool_free(pmb, phba->mbox_mem_pool);
814
815 return 0;
816}
817
818
819
820
821
822
823
824
825
826
827
828
829int
830lpfc_hba_down_prep(struct lpfc_hba *phba)
831{
832 struct lpfc_vport **vports;
833 int i;
834
835 if (phba->sli_rev <= LPFC_SLI_REV3) {
836
837 writel(0, phba->HCregaddr);
838 readl(phba->HCregaddr);
839 }
840
841 if (phba->pport->load_flag & FC_UNLOADING)
842 lpfc_cleanup_discovery_resources(phba->pport);
843 else {
844 vports = lpfc_create_vport_work_array(phba);
845 if (vports != NULL)
846 for (i = 0; i <= phba->max_vports &&
847 vports[i] != NULL; i++)
848 lpfc_cleanup_discovery_resources(vports[i]);
849 lpfc_destroy_vport_work_array(phba, vports);
850 }
851 return 0;
852}
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867static void
868lpfc_sli4_free_sp_events(struct lpfc_hba *phba)
869{
870 struct lpfc_iocbq *rspiocbq;
871 struct hbq_dmabuf *dmabuf;
872 struct lpfc_cq_event *cq_event;
873
874 spin_lock_irq(&phba->hbalock);
875 phba->hba_flag &= ~HBA_SP_QUEUE_EVT;
876 spin_unlock_irq(&phba->hbalock);
877
878 while (!list_empty(&phba->sli4_hba.sp_queue_event)) {
879
880 spin_lock_irq(&phba->hbalock);
881 list_remove_head(&phba->sli4_hba.sp_queue_event,
882 cq_event, struct lpfc_cq_event, list);
883 spin_unlock_irq(&phba->hbalock);
884
885 switch (bf_get(lpfc_wcqe_c_code, &cq_event->cqe.wcqe_cmpl)) {
886 case CQE_CODE_COMPL_WQE:
887 rspiocbq = container_of(cq_event, struct lpfc_iocbq,
888 cq_event);
889 lpfc_sli_release_iocbq(phba, rspiocbq);
890 break;
891 case CQE_CODE_RECEIVE:
892 case CQE_CODE_RECEIVE_V1:
893 dmabuf = container_of(cq_event, struct hbq_dmabuf,
894 cq_event);
895 lpfc_in_buf_free(phba, &dmabuf->dbuf);
896 }
897 }
898}
899
900
901
902
903
904
905
906
907
908
909
910
911static void
912lpfc_hba_free_post_buf(struct lpfc_hba *phba)
913{
914 struct lpfc_sli *psli = &phba->sli;
915 struct lpfc_sli_ring *pring;
916 struct lpfc_dmabuf *mp, *next_mp;
917 LIST_HEAD(buflist);
918 int count;
919
920 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
921 lpfc_sli_hbqbuf_free_all(phba);
922 else {
923
924 pring = &psli->sli3_ring[LPFC_ELS_RING];
925 spin_lock_irq(&phba->hbalock);
926 list_splice_init(&pring->postbufq, &buflist);
927 spin_unlock_irq(&phba->hbalock);
928
929 count = 0;
930 list_for_each_entry_safe(mp, next_mp, &buflist, list) {
931 list_del(&mp->list);
932 count++;
933 lpfc_mbuf_free(phba, mp->virt, mp->phys);
934 kfree(mp);
935 }
936
937 spin_lock_irq(&phba->hbalock);
938 pring->postbufq_cnt -= count;
939 spin_unlock_irq(&phba->hbalock);
940 }
941}
942
943
944
945
946
947
948
949
950
951
952
953static void
954lpfc_hba_clean_txcmplq(struct lpfc_hba *phba)
955{
956 struct lpfc_sli *psli = &phba->sli;
957 struct lpfc_queue *qp = NULL;
958 struct lpfc_sli_ring *pring;
959 LIST_HEAD(completions);
960 int i;
961
962 if (phba->sli_rev != LPFC_SLI_REV4) {
963 for (i = 0; i < psli->num_rings; i++) {
964 pring = &psli->sli3_ring[i];
965 spin_lock_irq(&phba->hbalock);
966
967
968
969
970 list_splice_init(&pring->txcmplq, &completions);
971 pring->txcmplq_cnt = 0;
972 spin_unlock_irq(&phba->hbalock);
973
974 lpfc_sli_abort_iocb_ring(phba, pring);
975 }
976
977 lpfc_sli_cancel_iocbs(phba, &completions,
978 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
979 return;
980 }
981 list_for_each_entry(qp, &phba->sli4_hba.lpfc_wq_list, wq_list) {
982 pring = qp->pring;
983 if (!pring)
984 continue;
985 spin_lock_irq(&pring->ring_lock);
986 list_splice_init(&pring->txcmplq, &completions);
987 pring->txcmplq_cnt = 0;
988 spin_unlock_irq(&pring->ring_lock);
989 lpfc_sli_abort_iocb_ring(phba, pring);
990 }
991
992 lpfc_sli_cancel_iocbs(phba, &completions,
993 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
994}
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008static int
1009lpfc_hba_down_post_s3(struct lpfc_hba *phba)
1010{
1011 lpfc_hba_free_post_buf(phba);
1012 lpfc_hba_clean_txcmplq(phba);
1013 return 0;
1014}
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027static int
1028lpfc_hba_down_post_s4(struct lpfc_hba *phba)
1029{
1030 struct lpfc_scsi_buf *psb, *psb_next;
1031 struct lpfc_nvmet_rcv_ctx *ctxp, *ctxp_next;
1032 LIST_HEAD(aborts);
1033 LIST_HEAD(nvme_aborts);
1034 LIST_HEAD(nvmet_aborts);
1035 unsigned long iflag = 0;
1036 struct lpfc_sglq *sglq_entry = NULL;
1037
1038
1039 lpfc_sli_hbqbuf_free_all(phba);
1040 lpfc_hba_clean_txcmplq(phba);
1041
1042
1043
1044
1045
1046
1047
1048 spin_lock_irq(&phba->hbalock);
1049
1050
1051
1052
1053 spin_lock(&phba->sli4_hba.sgl_list_lock);
1054 list_for_each_entry(sglq_entry,
1055 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
1056 sglq_entry->state = SGL_FREED;
1057
1058 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
1059 &phba->sli4_hba.lpfc_els_sgl_list);
1060
1061
1062 spin_unlock(&phba->sli4_hba.sgl_list_lock);
1063
1064
1065
1066 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
1067 spin_lock(&phba->sli4_hba.abts_scsi_buf_list_lock);
1068 list_splice_init(&phba->sli4_hba.lpfc_abts_scsi_buf_list,
1069 &aborts);
1070 spin_unlock(&phba->sli4_hba.abts_scsi_buf_list_lock);
1071 }
1072
1073 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
1074 spin_lock(&phba->sli4_hba.abts_nvme_buf_list_lock);
1075 list_splice_init(&phba->sli4_hba.lpfc_abts_nvme_buf_list,
1076 &nvme_aborts);
1077 list_splice_init(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list,
1078 &nvmet_aborts);
1079 spin_unlock(&phba->sli4_hba.abts_nvme_buf_list_lock);
1080 }
1081
1082 spin_unlock_irq(&phba->hbalock);
1083
1084 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
1085 psb->pCmd = NULL;
1086 psb->status = IOSTAT_SUCCESS;
1087 }
1088 spin_lock_irqsave(&phba->scsi_buf_list_put_lock, iflag);
1089 list_splice(&aborts, &phba->lpfc_scsi_buf_list_put);
1090 spin_unlock_irqrestore(&phba->scsi_buf_list_put_lock, iflag);
1091
1092 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
1093 list_for_each_entry_safe(psb, psb_next, &nvme_aborts, list) {
1094 psb->pCmd = NULL;
1095 psb->status = IOSTAT_SUCCESS;
1096 }
1097 spin_lock_irqsave(&phba->nvme_buf_list_put_lock, iflag);
1098 list_splice(&nvme_aborts, &phba->lpfc_nvme_buf_list_put);
1099 spin_unlock_irqrestore(&phba->nvme_buf_list_put_lock, iflag);
1100
1101 list_for_each_entry_safe(ctxp, ctxp_next, &nvmet_aborts, list) {
1102 ctxp->flag &= ~(LPFC_NVMET_XBUSY | LPFC_NVMET_ABORT_OP);
1103 lpfc_nvmet_ctxbuf_post(phba, ctxp->ctxbuf);
1104 }
1105 }
1106
1107 lpfc_sli4_free_sp_events(phba);
1108 return 0;
1109}
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122int
1123lpfc_hba_down_post(struct lpfc_hba *phba)
1124{
1125 return (*phba->lpfc_hba_down_post)(phba);
1126}
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140static void
1141lpfc_hb_timeout(struct timer_list *t)
1142{
1143 struct lpfc_hba *phba;
1144 uint32_t tmo_posted;
1145 unsigned long iflag;
1146
1147 phba = from_timer(phba, t, hb_tmofunc);
1148
1149
1150 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
1151 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
1152 if (!tmo_posted)
1153 phba->pport->work_port_events |= WORKER_HB_TMO;
1154 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1155
1156
1157 if (!tmo_posted)
1158 lpfc_worker_wake_up(phba);
1159 return;
1160}
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174static void
1175lpfc_rrq_timeout(struct timer_list *t)
1176{
1177 struct lpfc_hba *phba;
1178 unsigned long iflag;
1179
1180 phba = from_timer(phba, t, rrq_tmr);
1181 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
1182 if (!(phba->pport->load_flag & FC_UNLOADING))
1183 phba->hba_flag |= HBA_RRQ_ACTIVE;
1184 else
1185 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
1186 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1187
1188 if (!(phba->pport->load_flag & FC_UNLOADING))
1189 lpfc_worker_wake_up(phba);
1190}
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208static void
1209lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1210{
1211 unsigned long drvr_flag;
1212
1213 spin_lock_irqsave(&phba->hbalock, drvr_flag);
1214 phba->hb_outstanding = 0;
1215 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1216
1217
1218 mempool_free(pmboxq, phba->mbox_mem_pool);
1219 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1220 !(phba->link_state == LPFC_HBA_ERROR) &&
1221 !(phba->pport->load_flag & FC_UNLOADING))
1222 mod_timer(&phba->hb_tmofunc,
1223 jiffies +
1224 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1225 return;
1226}
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244void
1245lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1246{
1247 struct lpfc_vport **vports;
1248 LPFC_MBOXQ_t *pmboxq;
1249 struct lpfc_dmabuf *buf_ptr;
1250 int retval, i;
1251 struct lpfc_sli *psli = &phba->sli;
1252 LIST_HEAD(completions);
1253 struct lpfc_queue *qp;
1254 unsigned long time_elapsed;
1255 uint32_t tick_cqe, max_cqe, val;
1256 uint64_t tot, data1, data2, data3;
1257 struct lpfc_nvmet_tgtport *tgtp;
1258 struct lpfc_register reg_data;
1259 void __iomem *eqdreg = phba->sli4_hba.u.if_type2.EQDregaddr;
1260
1261 vports = lpfc_create_vport_work_array(phba);
1262 if (vports != NULL)
1263 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
1264 lpfc_rcv_seq_check_edtov(vports[i]);
1265 lpfc_fdmi_num_disc_check(vports[i]);
1266 }
1267 lpfc_destroy_vport_work_array(phba, vports);
1268
1269 if ((phba->link_state == LPFC_HBA_ERROR) ||
1270 (phba->pport->load_flag & FC_UNLOADING) ||
1271 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1272 return;
1273
1274 if (phba->cfg_auto_imax) {
1275 if (!phba->last_eqdelay_time) {
1276 phba->last_eqdelay_time = jiffies;
1277 goto skip_eqdelay;
1278 }
1279 time_elapsed = jiffies - phba->last_eqdelay_time;
1280 phba->last_eqdelay_time = jiffies;
1281
1282 tot = 0xffff;
1283
1284 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
1285 if (phba->nvmet_support) {
1286 tgtp = phba->targetport->private;
1287
1288 tot = atomic_read(&tgtp->rcv_fcp_cmd_drop);
1289 tot += atomic_read(&tgtp->xmt_fcp_release);
1290 tot = atomic_read(&tgtp->rcv_fcp_cmd_in) - tot;
1291 } else {
1292 tot = atomic_read(&phba->fc4NvmeIoCmpls);
1293 data1 = atomic_read(
1294 &phba->fc4NvmeInputRequests);
1295 data2 = atomic_read(
1296 &phba->fc4NvmeOutputRequests);
1297 data3 = atomic_read(
1298 &phba->fc4NvmeControlRequests);
1299 tot = (data1 + data2 + data3) - tot;
1300 }
1301 }
1302
1303
1304 val = phba->cfg_fcp_imax / phba->io_channel_irqs;
1305 tick_cqe = val / CONFIG_HZ;
1306
1307
1308 max_cqe = time_elapsed * tick_cqe;
1309
1310 for (i = 0; i < phba->io_channel_irqs; i++) {
1311
1312 qp = phba->sli4_hba.hba_eq[i];
1313 if (!qp)
1314 continue;
1315
1316
1317
1318
1319
1320
1321 if (tot < LPFC_NODELAY_MAX_IO ||
1322 qp->EQ_cqe_cnt <= max_cqe)
1323 val = 0;
1324 else
1325 val = phba->cfg_fcp_imax;
1326
1327 if (phba->sli.sli_flag & LPFC_SLI_USE_EQDR) {
1328
1329
1330
1331 if (val) {
1332
1333 val = phba->cfg_fcp_imax /
1334 phba->io_channel_irqs;
1335
1336
1337 val = LPFC_SEC_TO_USEC / val;
1338 }
1339 if (val != qp->q_mode) {
1340 reg_data.word0 = 0;
1341 bf_set(lpfc_sliport_eqdelay_id,
1342 ®_data, qp->queue_id);
1343 bf_set(lpfc_sliport_eqdelay_delay,
1344 ®_data, val);
1345 writel(reg_data.word0, eqdreg);
1346 }
1347 } else {
1348
1349 if (val != qp->q_mode)
1350 lpfc_modify_hba_eq_delay(phba, i,
1351 1, val);
1352 }
1353
1354
1355
1356
1357
1358 qp->q_mode = val;
1359 qp->EQ_cqe_cnt = 0;
1360 }
1361 }
1362
1363skip_eqdelay:
1364 spin_lock_irq(&phba->pport->work_port_lock);
1365
1366 if (time_after(phba->last_completion_time +
1367 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1368 jiffies)) {
1369 spin_unlock_irq(&phba->pport->work_port_lock);
1370 if (!phba->hb_outstanding)
1371 mod_timer(&phba->hb_tmofunc,
1372 jiffies +
1373 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1374 else
1375 mod_timer(&phba->hb_tmofunc,
1376 jiffies +
1377 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1378 return;
1379 }
1380 spin_unlock_irq(&phba->pport->work_port_lock);
1381
1382 if (phba->elsbuf_cnt &&
1383 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1384 spin_lock_irq(&phba->hbalock);
1385 list_splice_init(&phba->elsbuf, &completions);
1386 phba->elsbuf_cnt = 0;
1387 phba->elsbuf_prev_cnt = 0;
1388 spin_unlock_irq(&phba->hbalock);
1389
1390 while (!list_empty(&completions)) {
1391 list_remove_head(&completions, buf_ptr,
1392 struct lpfc_dmabuf, list);
1393 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1394 kfree(buf_ptr);
1395 }
1396 }
1397 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1398
1399
1400 if (phba->cfg_enable_hba_heartbeat) {
1401 if (!phba->hb_outstanding) {
1402 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1403 (list_empty(&psli->mboxq))) {
1404 pmboxq = mempool_alloc(phba->mbox_mem_pool,
1405 GFP_KERNEL);
1406 if (!pmboxq) {
1407 mod_timer(&phba->hb_tmofunc,
1408 jiffies +
1409 msecs_to_jiffies(1000 *
1410 LPFC_HB_MBOX_INTERVAL));
1411 return;
1412 }
1413
1414 lpfc_heart_beat(phba, pmboxq);
1415 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1416 pmboxq->vport = phba->pport;
1417 retval = lpfc_sli_issue_mbox(phba, pmboxq,
1418 MBX_NOWAIT);
1419
1420 if (retval != MBX_BUSY &&
1421 retval != MBX_SUCCESS) {
1422 mempool_free(pmboxq,
1423 phba->mbox_mem_pool);
1424 mod_timer(&phba->hb_tmofunc,
1425 jiffies +
1426 msecs_to_jiffies(1000 *
1427 LPFC_HB_MBOX_INTERVAL));
1428 return;
1429 }
1430 phba->skipped_hb = 0;
1431 phba->hb_outstanding = 1;
1432 } else if (time_before_eq(phba->last_completion_time,
1433 phba->skipped_hb)) {
1434 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1435 "2857 Last completion time not "
1436 " updated in %d ms\n",
1437 jiffies_to_msecs(jiffies
1438 - phba->last_completion_time));
1439 } else
1440 phba->skipped_hb = jiffies;
1441
1442 mod_timer(&phba->hb_tmofunc,
1443 jiffies +
1444 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1445 return;
1446 } else {
1447
1448
1449
1450
1451
1452 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1453 "0459 Adapter heartbeat still out"
1454 "standing:last compl time was %d ms.\n",
1455 jiffies_to_msecs(jiffies
1456 - phba->last_completion_time));
1457 mod_timer(&phba->hb_tmofunc,
1458 jiffies +
1459 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1460 }
1461 } else {
1462 mod_timer(&phba->hb_tmofunc,
1463 jiffies +
1464 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1465 }
1466}
1467
1468
1469
1470
1471
1472
1473
1474
1475static void
1476lpfc_offline_eratt(struct lpfc_hba *phba)
1477{
1478 struct lpfc_sli *psli = &phba->sli;
1479
1480 spin_lock_irq(&phba->hbalock);
1481 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1482 spin_unlock_irq(&phba->hbalock);
1483 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1484
1485 lpfc_offline(phba);
1486 lpfc_reset_barrier(phba);
1487 spin_lock_irq(&phba->hbalock);
1488 lpfc_sli_brdreset(phba);
1489 spin_unlock_irq(&phba->hbalock);
1490 lpfc_hba_down_post(phba);
1491 lpfc_sli_brdready(phba, HS_MBRDY);
1492 lpfc_unblock_mgmt_io(phba);
1493 phba->link_state = LPFC_HBA_ERROR;
1494 return;
1495}
1496
1497
1498
1499
1500
1501
1502
1503
1504void
1505lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1506{
1507 spin_lock_irq(&phba->hbalock);
1508 phba->link_state = LPFC_HBA_ERROR;
1509 spin_unlock_irq(&phba->hbalock);
1510
1511 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1512 lpfc_offline(phba);
1513 lpfc_hba_down_post(phba);
1514 lpfc_unblock_mgmt_io(phba);
1515}
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526static void
1527lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1528{
1529 uint32_t old_host_status = phba->work_hs;
1530 struct lpfc_sli *psli = &phba->sli;
1531
1532
1533
1534
1535 if (pci_channel_offline(phba->pcidev)) {
1536 spin_lock_irq(&phba->hbalock);
1537 phba->hba_flag &= ~DEFER_ERATT;
1538 spin_unlock_irq(&phba->hbalock);
1539 return;
1540 }
1541
1542 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1543 "0479 Deferred Adapter Hardware Error "
1544 "Data: x%x x%x x%x\n",
1545 phba->work_hs,
1546 phba->work_status[0], phba->work_status[1]);
1547
1548 spin_lock_irq(&phba->hbalock);
1549 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1550 spin_unlock_irq(&phba->hbalock);
1551
1552
1553
1554
1555
1556
1557
1558 lpfc_sli_abort_fcp_rings(phba);
1559
1560
1561
1562
1563
1564 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
1565 lpfc_offline(phba);
1566
1567
1568 while (phba->work_hs & HS_FFER1) {
1569 msleep(100);
1570 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1571 phba->work_hs = UNPLUG_ERR ;
1572 break;
1573 }
1574
1575 if (phba->pport->load_flag & FC_UNLOADING) {
1576 phba->work_hs = 0;
1577 break;
1578 }
1579 }
1580
1581
1582
1583
1584
1585
1586 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1587 phba->work_hs = old_host_status & ~HS_FFER1;
1588
1589 spin_lock_irq(&phba->hbalock);
1590 phba->hba_flag &= ~DEFER_ERATT;
1591 spin_unlock_irq(&phba->hbalock);
1592 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1593 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1594}
1595
1596static void
1597lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1598{
1599 struct lpfc_board_event_header board_event;
1600 struct Scsi_Host *shost;
1601
1602 board_event.event_type = FC_REG_BOARD_EVENT;
1603 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1604 shost = lpfc_shost_from_vport(phba->pport);
1605 fc_host_post_vendor_event(shost, fc_get_event_number(),
1606 sizeof(board_event),
1607 (char *) &board_event,
1608 LPFC_NL_VENDOR_ID);
1609}
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621static void
1622lpfc_handle_eratt_s3(struct lpfc_hba *phba)
1623{
1624 struct lpfc_vport *vport = phba->pport;
1625 struct lpfc_sli *psli = &phba->sli;
1626 uint32_t event_data;
1627 unsigned long temperature;
1628 struct temp_event temp_event_data;
1629 struct Scsi_Host *shost;
1630
1631
1632
1633
1634 if (pci_channel_offline(phba->pcidev)) {
1635 spin_lock_irq(&phba->hbalock);
1636 phba->hba_flag &= ~DEFER_ERATT;
1637 spin_unlock_irq(&phba->hbalock);
1638 return;
1639 }
1640
1641
1642 if (!phba->cfg_enable_hba_reset)
1643 return;
1644
1645
1646 lpfc_board_errevt_to_mgmt(phba);
1647
1648 if (phba->hba_flag & DEFER_ERATT)
1649 lpfc_handle_deferred_eratt(phba);
1650
1651 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1652 if (phba->work_hs & HS_FFER6)
1653
1654 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1655 "1301 Re-establishing Link "
1656 "Data: x%x x%x x%x\n",
1657 phba->work_hs, phba->work_status[0],
1658 phba->work_status[1]);
1659 if (phba->work_hs & HS_FFER8)
1660
1661 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1662 "2861 Host Authentication device "
1663 "zeroization Data:x%x x%x x%x\n",
1664 phba->work_hs, phba->work_status[0],
1665 phba->work_status[1]);
1666
1667 spin_lock_irq(&phba->hbalock);
1668 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1669 spin_unlock_irq(&phba->hbalock);
1670
1671
1672
1673
1674
1675
1676
1677 lpfc_sli_abort_fcp_rings(phba);
1678
1679
1680
1681
1682
1683 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1684 lpfc_offline(phba);
1685 lpfc_sli_brdrestart(phba);
1686 if (lpfc_online(phba) == 0) {
1687 lpfc_unblock_mgmt_io(phba);
1688 return;
1689 }
1690 lpfc_unblock_mgmt_io(phba);
1691 } else if (phba->work_hs & HS_CRIT_TEMP) {
1692 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1693 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1694 temp_event_data.event_code = LPFC_CRIT_TEMP;
1695 temp_event_data.data = (uint32_t)temperature;
1696
1697 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1698 "0406 Adapter maximum temperature exceeded "
1699 "(%ld), taking this port offline "
1700 "Data: x%x x%x x%x\n",
1701 temperature, phba->work_hs,
1702 phba->work_status[0], phba->work_status[1]);
1703
1704 shost = lpfc_shost_from_vport(phba->pport);
1705 fc_host_post_vendor_event(shost, fc_get_event_number(),
1706 sizeof(temp_event_data),
1707 (char *) &temp_event_data,
1708 SCSI_NL_VID_TYPE_PCI
1709 | PCI_VENDOR_ID_EMULEX);
1710
1711 spin_lock_irq(&phba->hbalock);
1712 phba->over_temp_state = HBA_OVER_TEMP;
1713 spin_unlock_irq(&phba->hbalock);
1714 lpfc_offline_eratt(phba);
1715
1716 } else {
1717
1718
1719
1720
1721 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1722 "0457 Adapter Hardware Error "
1723 "Data: x%x x%x x%x\n",
1724 phba->work_hs,
1725 phba->work_status[0], phba->work_status[1]);
1726
1727 event_data = FC_REG_DUMP_EVENT;
1728 shost = lpfc_shost_from_vport(vport);
1729 fc_host_post_vendor_event(shost, fc_get_event_number(),
1730 sizeof(event_data), (char *) &event_data,
1731 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1732
1733 lpfc_offline_eratt(phba);
1734 }
1735 return;
1736}
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749static int
1750lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action,
1751 bool en_rn_msg)
1752{
1753 int rc;
1754 uint32_t intr_mode;
1755
1756 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
1757 LPFC_SLI_INTF_IF_TYPE_2) {
1758
1759
1760
1761
1762 rc = lpfc_sli4_pdev_status_reg_wait(phba);
1763 if (rc)
1764 return rc;
1765 }
1766
1767
1768 if (en_rn_msg)
1769 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1770 "2887 Reset Needed: Attempting Port "
1771 "Recovery...\n");
1772 lpfc_offline_prep(phba, mbx_action);
1773 lpfc_offline(phba);
1774
1775 lpfc_sli4_disable_intr(phba);
1776 lpfc_sli_brdrestart(phba);
1777
1778 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1779 if (intr_mode == LPFC_INTR_ERROR) {
1780 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1781 "3175 Failed to enable interrupt\n");
1782 return -EIO;
1783 }
1784 phba->intr_mode = intr_mode;
1785 rc = lpfc_online(phba);
1786 if (rc == 0)
1787 lpfc_unblock_mgmt_io(phba);
1788
1789 return rc;
1790}
1791
1792
1793
1794
1795
1796
1797
1798
1799static void
1800lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1801{
1802 struct lpfc_vport *vport = phba->pport;
1803 uint32_t event_data;
1804 struct Scsi_Host *shost;
1805 uint32_t if_type;
1806 struct lpfc_register portstat_reg = {0};
1807 uint32_t reg_err1, reg_err2;
1808 uint32_t uerrlo_reg, uemasklo_reg;
1809 uint32_t smphr_port_status = 0, pci_rd_rc1, pci_rd_rc2;
1810 bool en_rn_msg = true;
1811 struct temp_event temp_event_data;
1812 struct lpfc_register portsmphr_reg;
1813 int rc, i;
1814
1815
1816
1817
1818 if (pci_channel_offline(phba->pcidev))
1819 return;
1820
1821 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
1822 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
1823 switch (if_type) {
1824 case LPFC_SLI_INTF_IF_TYPE_0:
1825 pci_rd_rc1 = lpfc_readl(
1826 phba->sli4_hba.u.if_type0.UERRLOregaddr,
1827 &uerrlo_reg);
1828 pci_rd_rc2 = lpfc_readl(
1829 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
1830 &uemasklo_reg);
1831
1832 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
1833 return;
1834 if (!(phba->hba_flag & HBA_RECOVERABLE_UE)) {
1835 lpfc_sli4_offline_eratt(phba);
1836 return;
1837 }
1838 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1839 "7623 Checking UE recoverable");
1840
1841 for (i = 0; i < phba->sli4_hba.ue_to_sr / 1000; i++) {
1842 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1843 &portsmphr_reg.word0))
1844 continue;
1845
1846 smphr_port_status = bf_get(lpfc_port_smphr_port_status,
1847 &portsmphr_reg);
1848 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1849 LPFC_PORT_SEM_UE_RECOVERABLE)
1850 break;
1851
1852 msleep(1000);
1853 }
1854
1855 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1856 "4827 smphr_port_status x%x : Waited %dSec",
1857 smphr_port_status, i);
1858
1859
1860 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1861 LPFC_PORT_SEM_UE_RECOVERABLE) {
1862 for (i = 0; i < 20; i++) {
1863 msleep(1000);
1864 if (!lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1865 &portsmphr_reg.word0) &&
1866 (LPFC_POST_STAGE_PORT_READY ==
1867 bf_get(lpfc_port_smphr_port_status,
1868 &portsmphr_reg))) {
1869 rc = lpfc_sli4_port_sta_fn_reset(phba,
1870 LPFC_MBX_NO_WAIT, en_rn_msg);
1871 if (rc == 0)
1872 return;
1873 lpfc_printf_log(phba,
1874 KERN_ERR, LOG_INIT,
1875 "4215 Failed to recover UE");
1876 break;
1877 }
1878 }
1879 }
1880 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1881 "7624 Firmware not ready: Failing UE recovery,"
1882 " waited %dSec", i);
1883 lpfc_sli4_offline_eratt(phba);
1884 break;
1885
1886 case LPFC_SLI_INTF_IF_TYPE_2:
1887 pci_rd_rc1 = lpfc_readl(
1888 phba->sli4_hba.u.if_type2.STATUSregaddr,
1889 &portstat_reg.word0);
1890
1891 if (pci_rd_rc1 == -EIO) {
1892 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1893 "3151 PCI bus read access failure: x%x\n",
1894 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
1895 return;
1896 }
1897 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
1898 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
1899 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
1900 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1901 "2889 Port Overtemperature event, "
1902 "taking port offline Data: x%x x%x\n",
1903 reg_err1, reg_err2);
1904
1905 phba->sfp_alarm |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
1906 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1907 temp_event_data.event_code = LPFC_CRIT_TEMP;
1908 temp_event_data.data = 0xFFFFFFFF;
1909
1910 shost = lpfc_shost_from_vport(phba->pport);
1911 fc_host_post_vendor_event(shost, fc_get_event_number(),
1912 sizeof(temp_event_data),
1913 (char *)&temp_event_data,
1914 SCSI_NL_VID_TYPE_PCI
1915 | PCI_VENDOR_ID_EMULEX);
1916
1917 spin_lock_irq(&phba->hbalock);
1918 phba->over_temp_state = HBA_OVER_TEMP;
1919 spin_unlock_irq(&phba->hbalock);
1920 lpfc_sli4_offline_eratt(phba);
1921 return;
1922 }
1923 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1924 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART) {
1925 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1926 "3143 Port Down: Firmware Update "
1927 "Detected\n");
1928 en_rn_msg = false;
1929 } else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1930 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1931 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1932 "3144 Port Down: Debug Dump\n");
1933 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1934 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
1935 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1936 "3145 Port Down: Provisioning\n");
1937
1938
1939 if (!phba->cfg_enable_hba_reset)
1940 return;
1941
1942
1943 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
1944 en_rn_msg);
1945 if (rc == 0) {
1946
1947 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1948 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1949 return;
1950 else
1951 break;
1952 }
1953
1954 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1955 "3152 Unrecoverable error, bring the port "
1956 "offline\n");
1957 lpfc_sli4_offline_eratt(phba);
1958 break;
1959 case LPFC_SLI_INTF_IF_TYPE_1:
1960 default:
1961 break;
1962 }
1963 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1964 "3123 Report dump event to upper layer\n");
1965
1966 lpfc_board_errevt_to_mgmt(phba);
1967
1968 event_data = FC_REG_DUMP_EVENT;
1969 shost = lpfc_shost_from_vport(vport);
1970 fc_host_post_vendor_event(shost, fc_get_event_number(),
1971 sizeof(event_data), (char *) &event_data,
1972 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1973}
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986void
1987lpfc_handle_eratt(struct lpfc_hba *phba)
1988{
1989 (*phba->lpfc_handle_eratt)(phba);
1990}
1991
1992
1993
1994
1995
1996
1997
1998
1999void
2000lpfc_handle_latt(struct lpfc_hba *phba)
2001{
2002 struct lpfc_vport *vport = phba->pport;
2003 struct lpfc_sli *psli = &phba->sli;
2004 LPFC_MBOXQ_t *pmb;
2005 volatile uint32_t control;
2006 struct lpfc_dmabuf *mp;
2007 int rc = 0;
2008
2009 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
2010 if (!pmb) {
2011 rc = 1;
2012 goto lpfc_handle_latt_err_exit;
2013 }
2014
2015 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
2016 if (!mp) {
2017 rc = 2;
2018 goto lpfc_handle_latt_free_pmb;
2019 }
2020
2021 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
2022 if (!mp->virt) {
2023 rc = 3;
2024 goto lpfc_handle_latt_free_mp;
2025 }
2026
2027
2028 lpfc_els_flush_all_cmd(phba);
2029
2030 psli->slistat.link_event++;
2031 lpfc_read_topology(phba, pmb, mp);
2032 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
2033 pmb->vport = vport;
2034
2035 phba->sli.sli3_ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
2036 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
2037 if (rc == MBX_NOT_FINISHED) {
2038 rc = 4;
2039 goto lpfc_handle_latt_free_mbuf;
2040 }
2041
2042
2043 spin_lock_irq(&phba->hbalock);
2044 writel(HA_LATT, phba->HAregaddr);
2045 readl(phba->HAregaddr);
2046 spin_unlock_irq(&phba->hbalock);
2047
2048 return;
2049
2050lpfc_handle_latt_free_mbuf:
2051 phba->sli.sli3_ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
2052 lpfc_mbuf_free(phba, mp->virt, mp->phys);
2053lpfc_handle_latt_free_mp:
2054 kfree(mp);
2055lpfc_handle_latt_free_pmb:
2056 mempool_free(pmb, phba->mbox_mem_pool);
2057lpfc_handle_latt_err_exit:
2058
2059 spin_lock_irq(&phba->hbalock);
2060 psli->sli_flag |= LPFC_PROCESS_LA;
2061 control = readl(phba->HCregaddr);
2062 control |= HC_LAINT_ENA;
2063 writel(control, phba->HCregaddr);
2064 readl(phba->HCregaddr);
2065
2066
2067 writel(HA_LATT, phba->HAregaddr);
2068 readl(phba->HAregaddr);
2069 spin_unlock_irq(&phba->hbalock);
2070 lpfc_linkdown(phba);
2071 phba->link_state = LPFC_HBA_ERROR;
2072
2073 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
2074 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
2075
2076 return;
2077}
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093int
2094lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
2095{
2096 uint8_t lenlo, lenhi;
2097 int Length;
2098 int i, j;
2099 int finished = 0;
2100 int index = 0;
2101
2102 if (!vpd)
2103 return 0;
2104
2105
2106 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2107 "0455 Vital Product Data: x%x x%x x%x x%x\n",
2108 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
2109 (uint32_t) vpd[3]);
2110 while (!finished && (index < (len - 4))) {
2111 switch (vpd[index]) {
2112 case 0x82:
2113 case 0x91:
2114 index += 1;
2115 lenlo = vpd[index];
2116 index += 1;
2117 lenhi = vpd[index];
2118 index += 1;
2119 i = ((((unsigned short)lenhi) << 8) + lenlo);
2120 index += i;
2121 break;
2122 case 0x90:
2123 index += 1;
2124 lenlo = vpd[index];
2125 index += 1;
2126 lenhi = vpd[index];
2127 index += 1;
2128 Length = ((((unsigned short)lenhi) << 8) + lenlo);
2129 if (Length > len - index)
2130 Length = len - index;
2131 while (Length > 0) {
2132
2133 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
2134 index += 2;
2135 i = vpd[index];
2136 index += 1;
2137 j = 0;
2138 Length -= (3+i);
2139 while(i--) {
2140 phba->SerialNumber[j++] = vpd[index++];
2141 if (j == 31)
2142 break;
2143 }
2144 phba->SerialNumber[j] = 0;
2145 continue;
2146 }
2147 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
2148 phba->vpd_flag |= VPD_MODEL_DESC;
2149 index += 2;
2150 i = vpd[index];
2151 index += 1;
2152 j = 0;
2153 Length -= (3+i);
2154 while(i--) {
2155 phba->ModelDesc[j++] = vpd[index++];
2156 if (j == 255)
2157 break;
2158 }
2159 phba->ModelDesc[j] = 0;
2160 continue;
2161 }
2162 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
2163 phba->vpd_flag |= VPD_MODEL_NAME;
2164 index += 2;
2165 i = vpd[index];
2166 index += 1;
2167 j = 0;
2168 Length -= (3+i);
2169 while(i--) {
2170 phba->ModelName[j++] = vpd[index++];
2171 if (j == 79)
2172 break;
2173 }
2174 phba->ModelName[j] = 0;
2175 continue;
2176 }
2177 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
2178 phba->vpd_flag |= VPD_PROGRAM_TYPE;
2179 index += 2;
2180 i = vpd[index];
2181 index += 1;
2182 j = 0;
2183 Length -= (3+i);
2184 while(i--) {
2185 phba->ProgramType[j++] = vpd[index++];
2186 if (j == 255)
2187 break;
2188 }
2189 phba->ProgramType[j] = 0;
2190 continue;
2191 }
2192 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
2193 phba->vpd_flag |= VPD_PORT;
2194 index += 2;
2195 i = vpd[index];
2196 index += 1;
2197 j = 0;
2198 Length -= (3+i);
2199 while(i--) {
2200 if ((phba->sli_rev == LPFC_SLI_REV4) &&
2201 (phba->sli4_hba.pport_name_sta ==
2202 LPFC_SLI4_PPNAME_GET)) {
2203 j++;
2204 index++;
2205 } else
2206 phba->Port[j++] = vpd[index++];
2207 if (j == 19)
2208 break;
2209 }
2210 if ((phba->sli_rev != LPFC_SLI_REV4) ||
2211 (phba->sli4_hba.pport_name_sta ==
2212 LPFC_SLI4_PPNAME_NON))
2213 phba->Port[j] = 0;
2214 continue;
2215 }
2216 else {
2217 index += 2;
2218 i = vpd[index];
2219 index += 1;
2220 index += i;
2221 Length -= (3 + i);
2222 }
2223 }
2224 finished = 0;
2225 break;
2226 case 0x78:
2227 finished = 1;
2228 break;
2229 default:
2230 index ++;
2231 break;
2232 }
2233 }
2234
2235 return(1);
2236}
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250static void
2251lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
2252{
2253 lpfc_vpd_t *vp;
2254 uint16_t dev_id = phba->pcidev->device;
2255 int max_speed;
2256 int GE = 0;
2257 int oneConnect = 0;
2258 struct {
2259 char *name;
2260 char *bus;
2261 char *function;
2262 } m = {"<Unknown>", "", ""};
2263
2264 if (mdp && mdp[0] != '\0'
2265 && descp && descp[0] != '\0')
2266 return;
2267
2268 if (phba->lmt & LMT_32Gb)
2269 max_speed = 32;
2270 else if (phba->lmt & LMT_16Gb)
2271 max_speed = 16;
2272 else if (phba->lmt & LMT_10Gb)
2273 max_speed = 10;
2274 else if (phba->lmt & LMT_8Gb)
2275 max_speed = 8;
2276 else if (phba->lmt & LMT_4Gb)
2277 max_speed = 4;
2278 else if (phba->lmt & LMT_2Gb)
2279 max_speed = 2;
2280 else if (phba->lmt & LMT_1Gb)
2281 max_speed = 1;
2282 else
2283 max_speed = 0;
2284
2285 vp = &phba->vpd;
2286
2287 switch (dev_id) {
2288 case PCI_DEVICE_ID_FIREFLY:
2289 m = (typeof(m)){"LP6000", "PCI",
2290 "Obsolete, Unsupported Fibre Channel Adapter"};
2291 break;
2292 case PCI_DEVICE_ID_SUPERFLY:
2293 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
2294 m = (typeof(m)){"LP7000", "PCI", ""};
2295 else
2296 m = (typeof(m)){"LP7000E", "PCI", ""};
2297 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
2298 break;
2299 case PCI_DEVICE_ID_DRAGONFLY:
2300 m = (typeof(m)){"LP8000", "PCI",
2301 "Obsolete, Unsupported Fibre Channel Adapter"};
2302 break;
2303 case PCI_DEVICE_ID_CENTAUR:
2304 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
2305 m = (typeof(m)){"LP9002", "PCI", ""};
2306 else
2307 m = (typeof(m)){"LP9000", "PCI", ""};
2308 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
2309 break;
2310 case PCI_DEVICE_ID_RFLY:
2311 m = (typeof(m)){"LP952", "PCI",
2312 "Obsolete, Unsupported Fibre Channel Adapter"};
2313 break;
2314 case PCI_DEVICE_ID_PEGASUS:
2315 m = (typeof(m)){"LP9802", "PCI-X",
2316 "Obsolete, Unsupported Fibre Channel Adapter"};
2317 break;
2318 case PCI_DEVICE_ID_THOR:
2319 m = (typeof(m)){"LP10000", "PCI-X",
2320 "Obsolete, Unsupported Fibre Channel Adapter"};
2321 break;
2322 case PCI_DEVICE_ID_VIPER:
2323 m = (typeof(m)){"LPX1000", "PCI-X",
2324 "Obsolete, Unsupported Fibre Channel Adapter"};
2325 break;
2326 case PCI_DEVICE_ID_PFLY:
2327 m = (typeof(m)){"LP982", "PCI-X",
2328 "Obsolete, Unsupported Fibre Channel Adapter"};
2329 break;
2330 case PCI_DEVICE_ID_TFLY:
2331 m = (typeof(m)){"LP1050", "PCI-X",
2332 "Obsolete, Unsupported Fibre Channel Adapter"};
2333 break;
2334 case PCI_DEVICE_ID_HELIOS:
2335 m = (typeof(m)){"LP11000", "PCI-X2",
2336 "Obsolete, Unsupported Fibre Channel Adapter"};
2337 break;
2338 case PCI_DEVICE_ID_HELIOS_SCSP:
2339 m = (typeof(m)){"LP11000-SP", "PCI-X2",
2340 "Obsolete, Unsupported Fibre Channel Adapter"};
2341 break;
2342 case PCI_DEVICE_ID_HELIOS_DCSP:
2343 m = (typeof(m)){"LP11002-SP", "PCI-X2",
2344 "Obsolete, Unsupported Fibre Channel Adapter"};
2345 break;
2346 case PCI_DEVICE_ID_NEPTUNE:
2347 m = (typeof(m)){"LPe1000", "PCIe",
2348 "Obsolete, Unsupported Fibre Channel Adapter"};
2349 break;
2350 case PCI_DEVICE_ID_NEPTUNE_SCSP:
2351 m = (typeof(m)){"LPe1000-SP", "PCIe",
2352 "Obsolete, Unsupported Fibre Channel Adapter"};
2353 break;
2354 case PCI_DEVICE_ID_NEPTUNE_DCSP:
2355 m = (typeof(m)){"LPe1002-SP", "PCIe",
2356 "Obsolete, Unsupported Fibre Channel Adapter"};
2357 break;
2358 case PCI_DEVICE_ID_BMID:
2359 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
2360 break;
2361 case PCI_DEVICE_ID_BSMB:
2362 m = (typeof(m)){"LP111", "PCI-X2",
2363 "Obsolete, Unsupported Fibre Channel Adapter"};
2364 break;
2365 case PCI_DEVICE_ID_ZEPHYR:
2366 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
2367 break;
2368 case PCI_DEVICE_ID_ZEPHYR_SCSP:
2369 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
2370 break;
2371 case PCI_DEVICE_ID_ZEPHYR_DCSP:
2372 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
2373 GE = 1;
2374 break;
2375 case PCI_DEVICE_ID_ZMID:
2376 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
2377 break;
2378 case PCI_DEVICE_ID_ZSMB:
2379 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
2380 break;
2381 case PCI_DEVICE_ID_LP101:
2382 m = (typeof(m)){"LP101", "PCI-X",
2383 "Obsolete, Unsupported Fibre Channel Adapter"};
2384 break;
2385 case PCI_DEVICE_ID_LP10000S:
2386 m = (typeof(m)){"LP10000-S", "PCI",
2387 "Obsolete, Unsupported Fibre Channel Adapter"};
2388 break;
2389 case PCI_DEVICE_ID_LP11000S:
2390 m = (typeof(m)){"LP11000-S", "PCI-X2",
2391 "Obsolete, Unsupported Fibre Channel Adapter"};
2392 break;
2393 case PCI_DEVICE_ID_LPE11000S:
2394 m = (typeof(m)){"LPe11000-S", "PCIe",
2395 "Obsolete, Unsupported Fibre Channel Adapter"};
2396 break;
2397 case PCI_DEVICE_ID_SAT:
2398 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
2399 break;
2400 case PCI_DEVICE_ID_SAT_MID:
2401 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
2402 break;
2403 case PCI_DEVICE_ID_SAT_SMB:
2404 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
2405 break;
2406 case PCI_DEVICE_ID_SAT_DCSP:
2407 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
2408 break;
2409 case PCI_DEVICE_ID_SAT_SCSP:
2410 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
2411 break;
2412 case PCI_DEVICE_ID_SAT_S:
2413 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
2414 break;
2415 case PCI_DEVICE_ID_HORNET:
2416 m = (typeof(m)){"LP21000", "PCIe",
2417 "Obsolete, Unsupported FCoE Adapter"};
2418 GE = 1;
2419 break;
2420 case PCI_DEVICE_ID_PROTEUS_VF:
2421 m = (typeof(m)){"LPev12000", "PCIe IOV",
2422 "Obsolete, Unsupported Fibre Channel Adapter"};
2423 break;
2424 case PCI_DEVICE_ID_PROTEUS_PF:
2425 m = (typeof(m)){"LPev12000", "PCIe IOV",
2426 "Obsolete, Unsupported Fibre Channel Adapter"};
2427 break;
2428 case PCI_DEVICE_ID_PROTEUS_S:
2429 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
2430 "Obsolete, Unsupported Fibre Channel Adapter"};
2431 break;
2432 case PCI_DEVICE_ID_TIGERSHARK:
2433 oneConnect = 1;
2434 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
2435 break;
2436 case PCI_DEVICE_ID_TOMCAT:
2437 oneConnect = 1;
2438 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2439 break;
2440 case PCI_DEVICE_ID_FALCON:
2441 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2442 "EmulexSecure Fibre"};
2443 break;
2444 case PCI_DEVICE_ID_BALIUS:
2445 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
2446 "Obsolete, Unsupported Fibre Channel Adapter"};
2447 break;
2448 case PCI_DEVICE_ID_LANCER_FC:
2449 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
2450 break;
2451 case PCI_DEVICE_ID_LANCER_FC_VF:
2452 m = (typeof(m)){"LPe16000", "PCIe",
2453 "Obsolete, Unsupported Fibre Channel Adapter"};
2454 break;
2455 case PCI_DEVICE_ID_LANCER_FCOE:
2456 oneConnect = 1;
2457 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
2458 break;
2459 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2460 oneConnect = 1;
2461 m = (typeof(m)){"OCe15100", "PCIe",
2462 "Obsolete, Unsupported FCoE"};
2463 break;
2464 case PCI_DEVICE_ID_LANCER_G6_FC:
2465 m = (typeof(m)){"LPe32000", "PCIe", "Fibre Channel Adapter"};
2466 break;
2467 case PCI_DEVICE_ID_SKYHAWK:
2468 case PCI_DEVICE_ID_SKYHAWK_VF:
2469 oneConnect = 1;
2470 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2471 break;
2472 default:
2473 m = (typeof(m)){"Unknown", "", ""};
2474 break;
2475 }
2476
2477 if (mdp && mdp[0] == '\0')
2478 snprintf(mdp, 79,"%s", m.name);
2479
2480
2481
2482
2483 if (descp && descp[0] == '\0') {
2484 if (oneConnect)
2485 snprintf(descp, 255,
2486 "Emulex OneConnect %s, %s Initiator %s",
2487 m.name, m.function,
2488 phba->Port);
2489 else if (max_speed == 0)
2490 snprintf(descp, 255,
2491 "Emulex %s %s %s",
2492 m.name, m.bus, m.function);
2493 else
2494 snprintf(descp, 255,
2495 "Emulex %s %d%s %s %s",
2496 m.name, max_speed, (GE) ? "GE" : "Gb",
2497 m.bus, m.function);
2498 }
2499}
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513int
2514lpfc_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
2515{
2516 IOCB_t *icmd;
2517 struct lpfc_iocbq *iocb;
2518 struct lpfc_dmabuf *mp1, *mp2;
2519
2520 cnt += pring->missbufcnt;
2521
2522
2523 while (cnt > 0) {
2524
2525 iocb = lpfc_sli_get_iocbq(phba);
2526 if (iocb == NULL) {
2527 pring->missbufcnt = cnt;
2528 return cnt;
2529 }
2530 icmd = &iocb->iocb;
2531
2532
2533
2534 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2535 if (mp1)
2536 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2537 if (!mp1 || !mp1->virt) {
2538 kfree(mp1);
2539 lpfc_sli_release_iocbq(phba, iocb);
2540 pring->missbufcnt = cnt;
2541 return cnt;
2542 }
2543
2544 INIT_LIST_HEAD(&mp1->list);
2545
2546 if (cnt > 1) {
2547 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2548 if (mp2)
2549 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2550 &mp2->phys);
2551 if (!mp2 || !mp2->virt) {
2552 kfree(mp2);
2553 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2554 kfree(mp1);
2555 lpfc_sli_release_iocbq(phba, iocb);
2556 pring->missbufcnt = cnt;
2557 return cnt;
2558 }
2559
2560 INIT_LIST_HEAD(&mp2->list);
2561 } else {
2562 mp2 = NULL;
2563 }
2564
2565 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2566 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2567 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2568 icmd->ulpBdeCount = 1;
2569 cnt--;
2570 if (mp2) {
2571 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2572 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2573 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2574 cnt--;
2575 icmd->ulpBdeCount = 2;
2576 }
2577
2578 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2579 icmd->ulpLe = 1;
2580
2581 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2582 IOCB_ERROR) {
2583 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2584 kfree(mp1);
2585 cnt++;
2586 if (mp2) {
2587 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2588 kfree(mp2);
2589 cnt++;
2590 }
2591 lpfc_sli_release_iocbq(phba, iocb);
2592 pring->missbufcnt = cnt;
2593 return cnt;
2594 }
2595 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
2596 if (mp2)
2597 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
2598 }
2599 pring->missbufcnt = 0;
2600 return 0;
2601}
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614static int
2615lpfc_post_rcv_buf(struct lpfc_hba *phba)
2616{
2617 struct lpfc_sli *psli = &phba->sli;
2618
2619
2620 lpfc_post_buffer(phba, &psli->sli3_ring[LPFC_ELS_RING], LPFC_BUF_RING0);
2621
2622
2623 return 0;
2624}
2625
2626#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2627
2628
2629
2630
2631
2632
2633
2634
2635static void
2636lpfc_sha_init(uint32_t * HashResultPointer)
2637{
2638 HashResultPointer[0] = 0x67452301;
2639 HashResultPointer[1] = 0xEFCDAB89;
2640 HashResultPointer[2] = 0x98BADCFE;
2641 HashResultPointer[3] = 0x10325476;
2642 HashResultPointer[4] = 0xC3D2E1F0;
2643}
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655static void
2656lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2657{
2658 int t;
2659 uint32_t TEMP;
2660 uint32_t A, B, C, D, E;
2661 t = 16;
2662 do {
2663 HashWorkingPointer[t] =
2664 S(1,
2665 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2666 8] ^
2667 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2668 } while (++t <= 79);
2669 t = 0;
2670 A = HashResultPointer[0];
2671 B = HashResultPointer[1];
2672 C = HashResultPointer[2];
2673 D = HashResultPointer[3];
2674 E = HashResultPointer[4];
2675
2676 do {
2677 if (t < 20) {
2678 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2679 } else if (t < 40) {
2680 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2681 } else if (t < 60) {
2682 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2683 } else {
2684 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2685 }
2686 TEMP += S(5, A) + E + HashWorkingPointer[t];
2687 E = D;
2688 D = C;
2689 C = S(30, B);
2690 B = A;
2691 A = TEMP;
2692 } while (++t <= 79);
2693
2694 HashResultPointer[0] += A;
2695 HashResultPointer[1] += B;
2696 HashResultPointer[2] += C;
2697 HashResultPointer[3] += D;
2698 HashResultPointer[4] += E;
2699
2700}
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712static void
2713lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2714{
2715 *HashWorking = (*RandomChallenge ^ *HashWorking);
2716}
2717
2718
2719
2720
2721
2722
2723
2724
2725void
2726lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2727{
2728 int t;
2729 uint32_t *HashWorking;
2730 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
2731
2732 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
2733 if (!HashWorking)
2734 return;
2735
2736 HashWorking[0] = HashWorking[78] = *pwwnn++;
2737 HashWorking[1] = HashWorking[79] = *pwwnn;
2738
2739 for (t = 0; t < 7; t++)
2740 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2741
2742 lpfc_sha_init(hbainit);
2743 lpfc_sha_iterate(hbainit, HashWorking);
2744 kfree(HashWorking);
2745}
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756void
2757lpfc_cleanup(struct lpfc_vport *vport)
2758{
2759 struct lpfc_hba *phba = vport->phba;
2760 struct lpfc_nodelist *ndlp, *next_ndlp;
2761 int i = 0;
2762
2763 if (phba->link_state > LPFC_LINK_DOWN)
2764 lpfc_port_link_failure(vport);
2765
2766 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
2767 if (!NLP_CHK_NODE_ACT(ndlp)) {
2768 ndlp = lpfc_enable_node(vport, ndlp,
2769 NLP_STE_UNUSED_NODE);
2770 if (!ndlp)
2771 continue;
2772 spin_lock_irq(&phba->ndlp_lock);
2773 NLP_SET_FREE_REQ(ndlp);
2774 spin_unlock_irq(&phba->ndlp_lock);
2775
2776 lpfc_nlp_put(ndlp);
2777 continue;
2778 }
2779 spin_lock_irq(&phba->ndlp_lock);
2780 if (NLP_CHK_FREE_REQ(ndlp)) {
2781
2782 spin_unlock_irq(&phba->ndlp_lock);
2783 continue;
2784 } else
2785
2786 NLP_SET_FREE_REQ(ndlp);
2787 spin_unlock_irq(&phba->ndlp_lock);
2788
2789 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2790 ndlp->nlp_DID == Fabric_DID) {
2791
2792 lpfc_nlp_put(ndlp);
2793 continue;
2794 }
2795
2796
2797
2798
2799 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
2800 lpfc_nlp_put(ndlp);
2801 continue;
2802 }
2803
2804 if (ndlp->nlp_type & NLP_FABRIC)
2805 lpfc_disc_state_machine(vport, ndlp, NULL,
2806 NLP_EVT_DEVICE_RECOVERY);
2807
2808 lpfc_disc_state_machine(vport, ndlp, NULL,
2809 NLP_EVT_DEVICE_RM);
2810 }
2811
2812
2813
2814
2815
2816 while (!list_empty(&vport->fc_nodes)) {
2817 if (i++ > 3000) {
2818 lpfc_printf_vlog(vport, KERN_ERR, LOG_DISCOVERY,
2819 "0233 Nodelist not empty\n");
2820 list_for_each_entry_safe(ndlp, next_ndlp,
2821 &vport->fc_nodes, nlp_listp) {
2822 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
2823 LOG_NODE,
2824 "0282 did:x%x ndlp:x%p "
2825 "usgmap:x%x refcnt:%d\n",
2826 ndlp->nlp_DID, (void *)ndlp,
2827 ndlp->nlp_usg_map,
2828 kref_read(&ndlp->kref));
2829 }
2830 break;
2831 }
2832
2833
2834 msleep(10);
2835 }
2836 lpfc_cleanup_vports_rrqs(vport, NULL);
2837}
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847void
2848lpfc_stop_vport_timers(struct lpfc_vport *vport)
2849{
2850 del_timer_sync(&vport->els_tmofunc);
2851 del_timer_sync(&vport->delayed_disc_tmo);
2852 lpfc_can_disctmo(vport);
2853 return;
2854}
2855
2856
2857
2858
2859
2860
2861
2862
2863void
2864__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2865{
2866
2867 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
2868
2869
2870 del_timer(&phba->fcf.redisc_wait);
2871}
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882void
2883lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2884{
2885 spin_lock_irq(&phba->hbalock);
2886 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
2887
2888 spin_unlock_irq(&phba->hbalock);
2889 return;
2890 }
2891 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
2892
2893 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
2894 spin_unlock_irq(&phba->hbalock);
2895}
2896
2897
2898
2899
2900
2901
2902
2903
2904void
2905lpfc_stop_hba_timers(struct lpfc_hba *phba)
2906{
2907 lpfc_stop_vport_timers(phba->pport);
2908 del_timer_sync(&phba->sli.mbox_tmo);
2909 del_timer_sync(&phba->fabric_block_timer);
2910 del_timer_sync(&phba->eratt_poll);
2911 del_timer_sync(&phba->hb_tmofunc);
2912 if (phba->sli_rev == LPFC_SLI_REV4) {
2913 del_timer_sync(&phba->rrq_tmr);
2914 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
2915 }
2916 phba->hb_outstanding = 0;
2917
2918 switch (phba->pci_dev_grp) {
2919 case LPFC_PCI_DEV_LP:
2920
2921 del_timer_sync(&phba->fcp_poll_timer);
2922 break;
2923 case LPFC_PCI_DEV_OC:
2924
2925 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
2926 break;
2927 default:
2928 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2929 "0297 Invalid device group (x%x)\n",
2930 phba->pci_dev_grp);
2931 break;
2932 }
2933 return;
2934}
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946static void
2947lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
2948{
2949 unsigned long iflag;
2950 uint8_t actcmd = MBX_HEARTBEAT;
2951 unsigned long timeout;
2952
2953 spin_lock_irqsave(&phba->hbalock, iflag);
2954 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
2955 spin_unlock_irqrestore(&phba->hbalock, iflag);
2956 if (mbx_action == LPFC_MBX_NO_WAIT)
2957 return;
2958 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
2959 spin_lock_irqsave(&phba->hbalock, iflag);
2960 if (phba->sli.mbox_active) {
2961 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
2962
2963
2964
2965 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
2966 phba->sli.mbox_active) * 1000) + jiffies;
2967 }
2968 spin_unlock_irqrestore(&phba->hbalock, iflag);
2969
2970
2971 while (phba->sli.mbox_active) {
2972
2973 msleep(2);
2974 if (time_after(jiffies, timeout)) {
2975 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
2976 "2813 Mgmt IO is Blocked %x "
2977 "- mbox cmd %x still active\n",
2978 phba->sli.sli_flag, actcmd);
2979 break;
2980 }
2981 }
2982}
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992void
2993lpfc_sli4_node_prep(struct lpfc_hba *phba)
2994{
2995 struct lpfc_nodelist *ndlp, *next_ndlp;
2996 struct lpfc_vport **vports;
2997 int i, rpi;
2998 unsigned long flags;
2999
3000 if (phba->sli_rev != LPFC_SLI_REV4)
3001 return;
3002
3003 vports = lpfc_create_vport_work_array(phba);
3004 if (vports == NULL)
3005 return;
3006
3007 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3008 if (vports[i]->load_flag & FC_UNLOADING)
3009 continue;
3010
3011 list_for_each_entry_safe(ndlp, next_ndlp,
3012 &vports[i]->fc_nodes,
3013 nlp_listp) {
3014 if (!NLP_CHK_NODE_ACT(ndlp))
3015 continue;
3016 rpi = lpfc_sli4_alloc_rpi(phba);
3017 if (rpi == LPFC_RPI_ALLOC_ERROR) {
3018 spin_lock_irqsave(&phba->ndlp_lock, flags);
3019 NLP_CLR_NODE_ACT(ndlp);
3020 spin_unlock_irqrestore(&phba->ndlp_lock, flags);
3021 continue;
3022 }
3023 ndlp->nlp_rpi = rpi;
3024 lpfc_printf_vlog(ndlp->vport, KERN_INFO, LOG_NODE,
3025 "0009 rpi:%x DID:%x "
3026 "flg:%x map:%x %p\n", ndlp->nlp_rpi,
3027 ndlp->nlp_DID, ndlp->nlp_flag,
3028 ndlp->nlp_usg_map, ndlp);
3029 }
3030 }
3031 lpfc_destroy_vport_work_array(phba, vports);
3032}
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046int
3047lpfc_online(struct lpfc_hba *phba)
3048{
3049 struct lpfc_vport *vport;
3050 struct lpfc_vport **vports;
3051 int i, error = 0;
3052 bool vpis_cleared = false;
3053
3054 if (!phba)
3055 return 0;
3056 vport = phba->pport;
3057
3058 if (!(vport->fc_flag & FC_OFFLINE_MODE))
3059 return 0;
3060
3061 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
3062 "0458 Bring Adapter online\n");
3063
3064 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
3065
3066 if (phba->sli_rev == LPFC_SLI_REV4) {
3067 if (lpfc_sli4_hba_setup(phba)) {
3068 lpfc_unblock_mgmt_io(phba);
3069 return 1;
3070 }
3071 spin_lock_irq(&phba->hbalock);
3072 if (!phba->sli4_hba.max_cfg_param.vpi_used)
3073 vpis_cleared = true;
3074 spin_unlock_irq(&phba->hbalock);
3075
3076
3077
3078
3079 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME &&
3080 !phba->nvmet_support) {
3081 error = lpfc_nvme_create_localport(phba->pport);
3082 if (error)
3083 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3084 "6132 NVME restore reg failed "
3085 "on nvmei error x%x\n", error);
3086 }
3087 } else {
3088 lpfc_sli_queue_init(phba);
3089 if (lpfc_sli_hba_setup(phba)) {
3090 lpfc_unblock_mgmt_io(phba);
3091 return 1;
3092 }
3093 }
3094
3095 vports = lpfc_create_vport_work_array(phba);
3096 if (vports != NULL) {
3097 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3098 struct Scsi_Host *shost;
3099 shost = lpfc_shost_from_vport(vports[i]);
3100 spin_lock_irq(shost->host_lock);
3101 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
3102 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
3103 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3104 if (phba->sli_rev == LPFC_SLI_REV4) {
3105 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
3106 if ((vpis_cleared) &&
3107 (vports[i]->port_type !=
3108 LPFC_PHYSICAL_PORT))
3109 vports[i]->vpi = 0;
3110 }
3111 spin_unlock_irq(shost->host_lock);
3112 }
3113 }
3114 lpfc_destroy_vport_work_array(phba, vports);
3115
3116 lpfc_unblock_mgmt_io(phba);
3117 return 0;
3118}
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131void
3132lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
3133{
3134 unsigned long iflag;
3135
3136 spin_lock_irqsave(&phba->hbalock, iflag);
3137 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
3138 spin_unlock_irqrestore(&phba->hbalock, iflag);
3139}
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149void
3150lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
3151{
3152 struct lpfc_vport *vport = phba->pport;
3153 struct lpfc_nodelist *ndlp, *next_ndlp;
3154 struct lpfc_vport **vports;
3155 struct Scsi_Host *shost;
3156 int i;
3157
3158 if (vport->fc_flag & FC_OFFLINE_MODE)
3159 return;
3160
3161 lpfc_block_mgmt_io(phba, mbx_action);
3162
3163 lpfc_linkdown(phba);
3164
3165
3166 vports = lpfc_create_vport_work_array(phba);
3167 if (vports != NULL) {
3168 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3169 if (vports[i]->load_flag & FC_UNLOADING)
3170 continue;
3171 shost = lpfc_shost_from_vport(vports[i]);
3172 spin_lock_irq(shost->host_lock);
3173 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
3174 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3175 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
3176 spin_unlock_irq(shost->host_lock);
3177
3178 shost = lpfc_shost_from_vport(vports[i]);
3179 list_for_each_entry_safe(ndlp, next_ndlp,
3180 &vports[i]->fc_nodes,
3181 nlp_listp) {
3182 if (!NLP_CHK_NODE_ACT(ndlp))
3183 continue;
3184 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE)
3185 continue;
3186 if (ndlp->nlp_type & NLP_FABRIC) {
3187 lpfc_disc_state_machine(vports[i], ndlp,
3188 NULL, NLP_EVT_DEVICE_RECOVERY);
3189 lpfc_disc_state_machine(vports[i], ndlp,
3190 NULL, NLP_EVT_DEVICE_RM);
3191 }
3192 spin_lock_irq(shost->host_lock);
3193 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
3194 spin_unlock_irq(shost->host_lock);
3195
3196
3197
3198
3199
3200 if (phba->sli_rev == LPFC_SLI_REV4) {
3201 lpfc_printf_vlog(ndlp->vport,
3202 KERN_INFO, LOG_NODE,
3203 "0011 lpfc_offline: "
3204 "ndlp:x%p did %x "
3205 "usgmap:x%x rpi:%x\n",
3206 ndlp, ndlp->nlp_DID,
3207 ndlp->nlp_usg_map,
3208 ndlp->nlp_rpi);
3209
3210 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
3211 }
3212 lpfc_unreg_rpi(vports[i], ndlp);
3213 }
3214 }
3215 }
3216 lpfc_destroy_vport_work_array(phba, vports);
3217
3218 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
3219
3220 if (phba->wq)
3221 flush_workqueue(phba->wq);
3222}
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232void
3233lpfc_offline(struct lpfc_hba *phba)
3234{
3235 struct Scsi_Host *shost;
3236 struct lpfc_vport **vports;
3237 int i;
3238
3239 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
3240 return;
3241
3242
3243 lpfc_stop_port(phba);
3244
3245
3246
3247
3248 lpfc_nvmet_destroy_targetport(phba);
3249 lpfc_nvme_destroy_localport(phba->pport);
3250
3251 vports = lpfc_create_vport_work_array(phba);
3252 if (vports != NULL)
3253 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
3254 lpfc_stop_vport_timers(vports[i]);
3255 lpfc_destroy_vport_work_array(phba, vports);
3256 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
3257 "0460 Bring Adapter offline\n");
3258
3259
3260 lpfc_sli_hba_down(phba);
3261 spin_lock_irq(&phba->hbalock);
3262 phba->work_ha = 0;
3263 spin_unlock_irq(&phba->hbalock);
3264 vports = lpfc_create_vport_work_array(phba);
3265 if (vports != NULL)
3266 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3267 shost = lpfc_shost_from_vport(vports[i]);
3268 spin_lock_irq(shost->host_lock);
3269 vports[i]->work_port_events = 0;
3270 vports[i]->fc_flag |= FC_OFFLINE_MODE;
3271 spin_unlock_irq(shost->host_lock);
3272 }
3273 lpfc_destroy_vport_work_array(phba, vports);
3274}
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284static void
3285lpfc_scsi_free(struct lpfc_hba *phba)
3286{
3287 struct lpfc_scsi_buf *sb, *sb_next;
3288
3289 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
3290 return;
3291
3292 spin_lock_irq(&phba->hbalock);
3293
3294
3295
3296 spin_lock(&phba->scsi_buf_list_put_lock);
3297 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
3298 list) {
3299 list_del(&sb->list);
3300 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
3301 sb->dma_handle);
3302 kfree(sb);
3303 phba->total_scsi_bufs--;
3304 }
3305 spin_unlock(&phba->scsi_buf_list_put_lock);
3306
3307 spin_lock(&phba->scsi_buf_list_get_lock);
3308 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
3309 list) {
3310 list_del(&sb->list);
3311 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
3312 sb->dma_handle);
3313 kfree(sb);
3314 phba->total_scsi_bufs--;
3315 }
3316 spin_unlock(&phba->scsi_buf_list_get_lock);
3317 spin_unlock_irq(&phba->hbalock);
3318}
3319
3320
3321
3322
3323
3324
3325
3326
3327static void
3328lpfc_nvme_free(struct lpfc_hba *phba)
3329{
3330 struct lpfc_nvme_buf *lpfc_ncmd, *lpfc_ncmd_next;
3331
3332 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME))
3333 return;
3334
3335 spin_lock_irq(&phba->hbalock);
3336
3337
3338 spin_lock(&phba->nvme_buf_list_put_lock);
3339 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3340 &phba->lpfc_nvme_buf_list_put, list) {
3341 list_del(&lpfc_ncmd->list);
3342 dma_pool_free(phba->lpfc_sg_dma_buf_pool, lpfc_ncmd->data,
3343 lpfc_ncmd->dma_handle);
3344 kfree(lpfc_ncmd);
3345 phba->total_nvme_bufs--;
3346 }
3347 spin_unlock(&phba->nvme_buf_list_put_lock);
3348
3349 spin_lock(&phba->nvme_buf_list_get_lock);
3350 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3351 &phba->lpfc_nvme_buf_list_get, list) {
3352 list_del(&lpfc_ncmd->list);
3353 dma_pool_free(phba->lpfc_sg_dma_buf_pool, lpfc_ncmd->data,
3354 lpfc_ncmd->dma_handle);
3355 kfree(lpfc_ncmd);
3356 phba->total_nvme_bufs--;
3357 }
3358 spin_unlock(&phba->nvme_buf_list_get_lock);
3359 spin_unlock_irq(&phba->hbalock);
3360}
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373int
3374lpfc_sli4_els_sgl_update(struct lpfc_hba *phba)
3375{
3376 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3377 uint16_t i, lxri, xri_cnt, els_xri_cnt;
3378 LIST_HEAD(els_sgl_list);
3379 int rc;
3380
3381
3382
3383
3384 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
3385
3386 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
3387
3388 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
3389 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3390 "3157 ELS xri-sgl count increased from "
3391 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3392 els_xri_cnt);
3393
3394 for (i = 0; i < xri_cnt; i++) {
3395 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3396 GFP_KERNEL);
3397 if (sglq_entry == NULL) {
3398 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3399 "2562 Failure to allocate an "
3400 "ELS sgl entry:%d\n", i);
3401 rc = -ENOMEM;
3402 goto out_free_mem;
3403 }
3404 sglq_entry->buff_type = GEN_BUFF_TYPE;
3405 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
3406 &sglq_entry->phys);
3407 if (sglq_entry->virt == NULL) {
3408 kfree(sglq_entry);
3409 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3410 "2563 Failure to allocate an "
3411 "ELS mbuf:%d\n", i);
3412 rc = -ENOMEM;
3413 goto out_free_mem;
3414 }
3415 sglq_entry->sgl = sglq_entry->virt;
3416 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
3417 sglq_entry->state = SGL_FREED;
3418 list_add_tail(&sglq_entry->list, &els_sgl_list);
3419 }
3420 spin_lock_irq(&phba->hbalock);
3421 spin_lock(&phba->sli4_hba.sgl_list_lock);
3422 list_splice_init(&els_sgl_list,
3423 &phba->sli4_hba.lpfc_els_sgl_list);
3424 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3425 spin_unlock_irq(&phba->hbalock);
3426 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
3427
3428 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
3429 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3430 "3158 ELS xri-sgl count decreased from "
3431 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3432 els_xri_cnt);
3433 spin_lock_irq(&phba->hbalock);
3434 spin_lock(&phba->sli4_hba.sgl_list_lock);
3435 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list,
3436 &els_sgl_list);
3437
3438 for (i = 0; i < xri_cnt; i++) {
3439 list_remove_head(&els_sgl_list,
3440 sglq_entry, struct lpfc_sglq, list);
3441 if (sglq_entry) {
3442 __lpfc_mbuf_free(phba, sglq_entry->virt,
3443 sglq_entry->phys);
3444 kfree(sglq_entry);
3445 }
3446 }
3447 list_splice_init(&els_sgl_list,
3448 &phba->sli4_hba.lpfc_els_sgl_list);
3449 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3450 spin_unlock_irq(&phba->hbalock);
3451 } else
3452 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3453 "3163 ELS xri-sgl count unchanged: %d\n",
3454 els_xri_cnt);
3455 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
3456
3457
3458 sglq_entry = NULL;
3459 sglq_entry_next = NULL;
3460 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3461 &phba->sli4_hba.lpfc_els_sgl_list, list) {
3462 lxri = lpfc_sli4_next_xritag(phba);
3463 if (lxri == NO_XRI) {
3464 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3465 "2400 Failed to allocate xri for "
3466 "ELS sgl\n");
3467 rc = -ENOMEM;
3468 goto out_free_mem;
3469 }
3470 sglq_entry->sli4_lxritag = lxri;
3471 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3472 }
3473 return 0;
3474
3475out_free_mem:
3476 lpfc_free_els_sgl_list(phba);
3477 return rc;
3478}
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492int
3493lpfc_sli4_nvmet_sgl_update(struct lpfc_hba *phba)
3494{
3495 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3496 uint16_t i, lxri, xri_cnt, els_xri_cnt;
3497 uint16_t nvmet_xri_cnt;
3498 LIST_HEAD(nvmet_sgl_list);
3499 int rc;
3500
3501
3502
3503
3504 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
3505
3506
3507 nvmet_xri_cnt = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
3508 if (nvmet_xri_cnt > phba->sli4_hba.nvmet_xri_cnt) {
3509
3510 xri_cnt = nvmet_xri_cnt - phba->sli4_hba.nvmet_xri_cnt;
3511 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3512 "6302 NVMET xri-sgl cnt grew from %d to %d\n",
3513 phba->sli4_hba.nvmet_xri_cnt, nvmet_xri_cnt);
3514
3515 for (i = 0; i < xri_cnt; i++) {
3516 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3517 GFP_KERNEL);
3518 if (sglq_entry == NULL) {
3519 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3520 "6303 Failure to allocate an "
3521 "NVMET sgl entry:%d\n", i);
3522 rc = -ENOMEM;
3523 goto out_free_mem;
3524 }
3525 sglq_entry->buff_type = NVMET_BUFF_TYPE;
3526 sglq_entry->virt = lpfc_nvmet_buf_alloc(phba, 0,
3527 &sglq_entry->phys);
3528 if (sglq_entry->virt == NULL) {
3529 kfree(sglq_entry);
3530 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3531 "6304 Failure to allocate an "
3532 "NVMET buf:%d\n", i);
3533 rc = -ENOMEM;
3534 goto out_free_mem;
3535 }
3536 sglq_entry->sgl = sglq_entry->virt;
3537 memset(sglq_entry->sgl, 0,
3538 phba->cfg_sg_dma_buf_size);
3539 sglq_entry->state = SGL_FREED;
3540 list_add_tail(&sglq_entry->list, &nvmet_sgl_list);
3541 }
3542 spin_lock_irq(&phba->hbalock);
3543 spin_lock(&phba->sli4_hba.sgl_list_lock);
3544 list_splice_init(&nvmet_sgl_list,
3545 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3546 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3547 spin_unlock_irq(&phba->hbalock);
3548 } else if (nvmet_xri_cnt < phba->sli4_hba.nvmet_xri_cnt) {
3549
3550 xri_cnt = phba->sli4_hba.nvmet_xri_cnt - nvmet_xri_cnt;
3551 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3552 "6305 NVMET xri-sgl count decreased from "
3553 "%d to %d\n", phba->sli4_hba.nvmet_xri_cnt,
3554 nvmet_xri_cnt);
3555 spin_lock_irq(&phba->hbalock);
3556 spin_lock(&phba->sli4_hba.sgl_list_lock);
3557 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list,
3558 &nvmet_sgl_list);
3559
3560 for (i = 0; i < xri_cnt; i++) {
3561 list_remove_head(&nvmet_sgl_list,
3562 sglq_entry, struct lpfc_sglq, list);
3563 if (sglq_entry) {
3564 lpfc_nvmet_buf_free(phba, sglq_entry->virt,
3565 sglq_entry->phys);
3566 kfree(sglq_entry);
3567 }
3568 }
3569 list_splice_init(&nvmet_sgl_list,
3570 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3571 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3572 spin_unlock_irq(&phba->hbalock);
3573 } else
3574 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3575 "6306 NVMET xri-sgl count unchanged: %d\n",
3576 nvmet_xri_cnt);
3577 phba->sli4_hba.nvmet_xri_cnt = nvmet_xri_cnt;
3578
3579
3580 sglq_entry = NULL;
3581 sglq_entry_next = NULL;
3582 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3583 &phba->sli4_hba.lpfc_nvmet_sgl_list, list) {
3584 lxri = lpfc_sli4_next_xritag(phba);
3585 if (lxri == NO_XRI) {
3586 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3587 "6307 Failed to allocate xri for "
3588 "NVMET sgl\n");
3589 rc = -ENOMEM;
3590 goto out_free_mem;
3591 }
3592 sglq_entry->sli4_lxritag = lxri;
3593 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3594 }
3595 return 0;
3596
3597out_free_mem:
3598 lpfc_free_nvmet_sgl_list(phba);
3599 return rc;
3600}
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614int
3615lpfc_sli4_scsi_sgl_update(struct lpfc_hba *phba)
3616{
3617 struct lpfc_scsi_buf *psb, *psb_next;
3618 uint16_t i, lxri, els_xri_cnt, scsi_xri_cnt;
3619 LIST_HEAD(scsi_sgl_list);
3620 int rc;
3621
3622
3623
3624
3625 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
3626 phba->total_scsi_bufs = 0;
3627
3628
3629
3630
3631
3632 phba->sli4_hba.scsi_xri_max = phba->sli4_hba.max_cfg_param.max_xri -
3633 els_xri_cnt;
3634
3635 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
3636 return 0;
3637
3638 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3639 phba->sli4_hba.scsi_xri_max =
3640 (phba->sli4_hba.scsi_xri_max *
3641 phba->cfg_xri_split) / 100;
3642
3643 spin_lock_irq(&phba->scsi_buf_list_get_lock);
3644 spin_lock(&phba->scsi_buf_list_put_lock);
3645 list_splice_init(&phba->lpfc_scsi_buf_list_get, &scsi_sgl_list);
3646 list_splice(&phba->lpfc_scsi_buf_list_put, &scsi_sgl_list);
3647 spin_unlock(&phba->scsi_buf_list_put_lock);
3648 spin_unlock_irq(&phba->scsi_buf_list_get_lock);
3649
3650 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3651 "6060 Current allocated SCSI xri-sgl count:%d, "
3652 "maximum SCSI xri count:%d (split:%d)\n",
3653 phba->sli4_hba.scsi_xri_cnt,
3654 phba->sli4_hba.scsi_xri_max, phba->cfg_xri_split);
3655
3656 if (phba->sli4_hba.scsi_xri_cnt > phba->sli4_hba.scsi_xri_max) {
3657
3658 scsi_xri_cnt = phba->sli4_hba.scsi_xri_cnt -
3659 phba->sli4_hba.scsi_xri_max;
3660
3661 for (i = 0; i < scsi_xri_cnt; i++) {
3662 list_remove_head(&scsi_sgl_list, psb,
3663 struct lpfc_scsi_buf, list);
3664 if (psb) {
3665 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3666 psb->data, psb->dma_handle);
3667 kfree(psb);
3668 }
3669 }
3670 spin_lock_irq(&phba->scsi_buf_list_get_lock);
3671 phba->sli4_hba.scsi_xri_cnt -= scsi_xri_cnt;
3672 spin_unlock_irq(&phba->scsi_buf_list_get_lock);
3673 }
3674
3675
3676 psb = NULL;
3677 psb_next = NULL;
3678 list_for_each_entry_safe(psb, psb_next, &scsi_sgl_list, list) {
3679 lxri = lpfc_sli4_next_xritag(phba);
3680 if (lxri == NO_XRI) {
3681 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3682 "2560 Failed to allocate xri for "
3683 "scsi buffer\n");
3684 rc = -ENOMEM;
3685 goto out_free_mem;
3686 }
3687 psb->cur_iocbq.sli4_lxritag = lxri;
3688 psb->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3689 }
3690 spin_lock_irq(&phba->scsi_buf_list_get_lock);
3691 spin_lock(&phba->scsi_buf_list_put_lock);
3692 list_splice_init(&scsi_sgl_list, &phba->lpfc_scsi_buf_list_get);
3693 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
3694 spin_unlock(&phba->scsi_buf_list_put_lock);
3695 spin_unlock_irq(&phba->scsi_buf_list_get_lock);
3696 return 0;
3697
3698out_free_mem:
3699 lpfc_scsi_free(phba);
3700 return rc;
3701}
3702
3703static uint64_t
3704lpfc_get_wwpn(struct lpfc_hba *phba)
3705{
3706 uint64_t wwn;
3707 int rc;
3708 LPFC_MBOXQ_t *mboxq;
3709 MAILBOX_t *mb;
3710
3711 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
3712 GFP_KERNEL);
3713 if (!mboxq)
3714 return (uint64_t)-1;
3715
3716
3717 lpfc_read_nv(phba, mboxq);
3718 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
3719 if (rc != MBX_SUCCESS) {
3720 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3721 "6019 Mailbox failed , mbxCmd x%x "
3722 "READ_NV, mbxStatus x%x\n",
3723 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
3724 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
3725 mempool_free(mboxq, phba->mbox_mem_pool);
3726 return (uint64_t) -1;
3727 }
3728 mb = &mboxq->u.mb;
3729 memcpy(&wwn, (char *)mb->un.varRDnvp.portname, sizeof(uint64_t));
3730
3731 mempool_free(mboxq, phba->mbox_mem_pool);
3732 if (phba->sli_rev == LPFC_SLI_REV4)
3733 return be64_to_cpu(wwn);
3734 else
3735 return rol64(wwn, 32);
3736}
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750int
3751lpfc_sli4_nvme_sgl_update(struct lpfc_hba *phba)
3752{
3753 struct lpfc_nvme_buf *lpfc_ncmd = NULL, *lpfc_ncmd_next = NULL;
3754 uint16_t i, lxri, els_xri_cnt;
3755 uint16_t nvme_xri_cnt, nvme_xri_max;
3756 LIST_HEAD(nvme_sgl_list);
3757 int rc;
3758
3759 phba->total_nvme_bufs = 0;
3760
3761 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME))
3762 return 0;
3763
3764
3765
3766
3767
3768 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
3769 nvme_xri_max = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
3770 phba->sli4_hba.nvme_xri_max = nvme_xri_max;
3771 phba->sli4_hba.nvme_xri_max -= phba->sli4_hba.scsi_xri_max;
3772
3773 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3774 "6074 Current allocated NVME xri-sgl count:%d, "
3775 "maximum NVME xri count:%d\n",
3776 phba->sli4_hba.nvme_xri_cnt,
3777 phba->sli4_hba.nvme_xri_max);
3778
3779 spin_lock_irq(&phba->nvme_buf_list_get_lock);
3780 spin_lock(&phba->nvme_buf_list_put_lock);
3781 list_splice_init(&phba->lpfc_nvme_buf_list_get, &nvme_sgl_list);
3782 list_splice(&phba->lpfc_nvme_buf_list_put, &nvme_sgl_list);
3783 spin_unlock(&phba->nvme_buf_list_put_lock);
3784 spin_unlock_irq(&phba->nvme_buf_list_get_lock);
3785
3786 if (phba->sli4_hba.nvme_xri_cnt > phba->sli4_hba.nvme_xri_max) {
3787
3788 spin_lock_irq(&phba->nvme_buf_list_get_lock);
3789 nvme_xri_cnt = phba->sli4_hba.nvme_xri_cnt -
3790 phba->sli4_hba.nvme_xri_max;
3791 spin_unlock_irq(&phba->nvme_buf_list_get_lock);
3792
3793 for (i = 0; i < nvme_xri_cnt; i++) {
3794 list_remove_head(&nvme_sgl_list, lpfc_ncmd,
3795 struct lpfc_nvme_buf, list);
3796 if (lpfc_ncmd) {
3797 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3798 lpfc_ncmd->data,
3799 lpfc_ncmd->dma_handle);
3800 kfree(lpfc_ncmd);
3801 }
3802 }
3803 spin_lock_irq(&phba->nvme_buf_list_get_lock);
3804 phba->sli4_hba.nvme_xri_cnt -= nvme_xri_cnt;
3805 spin_unlock_irq(&phba->nvme_buf_list_get_lock);
3806 }
3807
3808
3809 lpfc_ncmd = NULL;
3810 lpfc_ncmd_next = NULL;
3811 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3812 &nvme_sgl_list, list) {
3813 lxri = lpfc_sli4_next_xritag(phba);
3814 if (lxri == NO_XRI) {
3815 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3816 "6075 Failed to allocate xri for "
3817 "nvme buffer\n");
3818 rc = -ENOMEM;
3819 goto out_free_mem;
3820 }
3821 lpfc_ncmd->cur_iocbq.sli4_lxritag = lxri;
3822 lpfc_ncmd->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3823 }
3824 spin_lock_irq(&phba->nvme_buf_list_get_lock);
3825 spin_lock(&phba->nvme_buf_list_put_lock);
3826 list_splice_init(&nvme_sgl_list, &phba->lpfc_nvme_buf_list_get);
3827 INIT_LIST_HEAD(&phba->lpfc_nvme_buf_list_put);
3828 spin_unlock(&phba->nvme_buf_list_put_lock);
3829 spin_unlock_irq(&phba->nvme_buf_list_get_lock);
3830 return 0;
3831
3832out_free_mem:
3833 lpfc_nvme_free(phba);
3834 return rc;
3835}
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853struct lpfc_vport *
3854lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
3855{
3856 struct lpfc_vport *vport;
3857 struct Scsi_Host *shost = NULL;
3858 int error = 0;
3859 int i;
3860 uint64_t wwn;
3861 bool use_no_reset_hba = false;
3862 int rc;
3863
3864 if (lpfc_no_hba_reset_cnt) {
3865 if (phba->sli_rev < LPFC_SLI_REV4 &&
3866 dev == &phba->pcidev->dev) {
3867
3868 lpfc_sli_brdrestart(phba);
3869 rc = lpfc_sli_chipset_init(phba);
3870 if (rc)
3871 return NULL;
3872 }
3873 wwn = lpfc_get_wwpn(phba);
3874 }
3875
3876 for (i = 0; i < lpfc_no_hba_reset_cnt; i++) {
3877 if (wwn == lpfc_no_hba_reset[i]) {
3878 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3879 "6020 Setting use_no_reset port=%llx\n",
3880 wwn);
3881 use_no_reset_hba = true;
3882 break;
3883 }
3884 }
3885
3886 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
3887 if (dev != &phba->pcidev->dev) {
3888 shost = scsi_host_alloc(&lpfc_vport_template,
3889 sizeof(struct lpfc_vport));
3890 } else {
3891 if (!use_no_reset_hba)
3892 shost = scsi_host_alloc(&lpfc_template,
3893 sizeof(struct lpfc_vport));
3894 else
3895 shost = scsi_host_alloc(&lpfc_template_no_hr,
3896 sizeof(struct lpfc_vport));
3897 }
3898 } else if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
3899 shost = scsi_host_alloc(&lpfc_template_nvme,
3900 sizeof(struct lpfc_vport));
3901 }
3902 if (!shost)
3903 goto out;
3904
3905 vport = (struct lpfc_vport *) shost->hostdata;
3906 vport->phba = phba;
3907 vport->load_flag |= FC_LOADING;
3908 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3909 vport->fc_rscn_flush = 0;
3910 lpfc_get_vport_cfgparam(vport);
3911
3912 shost->unique_id = instance;
3913 shost->max_id = LPFC_MAX_TARGET;
3914 shost->max_lun = vport->cfg_max_luns;
3915 shost->this_id = -1;
3916 shost->max_cmd_len = 16;
3917 shost->nr_hw_queues = phba->cfg_fcp_io_channel;
3918 if (phba->sli_rev == LPFC_SLI_REV4) {
3919 shost->dma_boundary =
3920 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
3921 shost->sg_tablesize = phba->cfg_sg_seg_cnt;
3922 }
3923
3924
3925
3926
3927
3928
3929 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3930 if (dev != &phba->pcidev->dev) {
3931 shost->transportt = lpfc_vport_transport_template;
3932 vport->port_type = LPFC_NPIV_PORT;
3933 } else {
3934 shost->transportt = lpfc_transport_template;
3935 vport->port_type = LPFC_PHYSICAL_PORT;
3936 }
3937
3938
3939 INIT_LIST_HEAD(&vport->fc_nodes);
3940 INIT_LIST_HEAD(&vport->rcv_buffer_list);
3941 spin_lock_init(&vport->work_port_lock);
3942
3943 timer_setup(&vport->fc_disctmo, lpfc_disc_timeout, 0);
3944
3945 timer_setup(&vport->els_tmofunc, lpfc_els_timeout, 0);
3946
3947 timer_setup(&vport->delayed_disc_tmo, lpfc_delayed_disc_tmo, 0);
3948
3949 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
3950 if (error)
3951 goto out_put_shost;
3952
3953 spin_lock_irq(&phba->hbalock);
3954 list_add_tail(&vport->listentry, &phba->port_list);
3955 spin_unlock_irq(&phba->hbalock);
3956 return vport;
3957
3958out_put_shost:
3959 scsi_host_put(shost);
3960out:
3961 return NULL;
3962}
3963
3964
3965
3966
3967
3968
3969
3970
3971void
3972destroy_port(struct lpfc_vport *vport)
3973{
3974 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
3975 struct lpfc_hba *phba = vport->phba;
3976
3977 lpfc_debugfs_terminate(vport);
3978 fc_remove_host(shost);
3979 scsi_remove_host(shost);
3980
3981 spin_lock_irq(&phba->hbalock);
3982 list_del_init(&vport->listentry);
3983 spin_unlock_irq(&phba->hbalock);
3984
3985 lpfc_cleanup(vport);
3986 return;
3987}
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999int
4000lpfc_get_instance(void)
4001{
4002 int ret;
4003
4004 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
4005 return ret < 0 ? -1 : ret;
4006}
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
4024{
4025 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4026 struct lpfc_hba *phba = vport->phba;
4027 int stat = 0;
4028
4029 spin_lock_irq(shost->host_lock);
4030
4031 if (vport->load_flag & FC_UNLOADING) {
4032 stat = 1;
4033 goto finished;
4034 }
4035 if (time >= msecs_to_jiffies(30 * 1000)) {
4036 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
4037 "0461 Scanning longer than 30 "
4038 "seconds. Continuing initialization\n");
4039 stat = 1;
4040 goto finished;
4041 }
4042 if (time >= msecs_to_jiffies(15 * 1000) &&
4043 phba->link_state <= LPFC_LINK_DOWN) {
4044 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
4045 "0465 Link down longer than 15 "
4046 "seconds. Continuing initialization\n");
4047 stat = 1;
4048 goto finished;
4049 }
4050
4051 if (vport->port_state != LPFC_VPORT_READY)
4052 goto finished;
4053 if (vport->num_disc_nodes || vport->fc_prli_sent)
4054 goto finished;
4055 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
4056 goto finished;
4057 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
4058 goto finished;
4059
4060 stat = 1;
4061
4062finished:
4063 spin_unlock_irq(shost->host_lock);
4064 return stat;
4065}
4066
4067
4068
4069
4070
4071
4072
4073
4074void lpfc_host_attrib_init(struct Scsi_Host *shost)
4075{
4076 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4077 struct lpfc_hba *phba = vport->phba;
4078
4079
4080
4081
4082 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
4083 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
4084 fc_host_supported_classes(shost) = FC_COS_CLASS3;
4085
4086 memset(fc_host_supported_fc4s(shost), 0,
4087 sizeof(fc_host_supported_fc4s(shost)));
4088 fc_host_supported_fc4s(shost)[2] = 1;
4089 fc_host_supported_fc4s(shost)[7] = 1;
4090
4091 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
4092 sizeof fc_host_symbolic_name(shost));
4093
4094 fc_host_supported_speeds(shost) = 0;
4095 if (phba->lmt & LMT_32Gb)
4096 fc_host_supported_speeds(shost) |= FC_PORTSPEED_32GBIT;
4097 if (phba->lmt & LMT_16Gb)
4098 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
4099 if (phba->lmt & LMT_10Gb)
4100 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
4101 if (phba->lmt & LMT_8Gb)
4102 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
4103 if (phba->lmt & LMT_4Gb)
4104 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
4105 if (phba->lmt & LMT_2Gb)
4106 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
4107 if (phba->lmt & LMT_1Gb)
4108 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
4109
4110 fc_host_maxframe_size(shost) =
4111 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
4112 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
4113
4114 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
4115
4116
4117 memset(fc_host_active_fc4s(shost), 0,
4118 sizeof(fc_host_active_fc4s(shost)));
4119 fc_host_active_fc4s(shost)[2] = 1;
4120 fc_host_active_fc4s(shost)[7] = 1;
4121
4122 fc_host_max_npiv_vports(shost) = phba->max_vpi;
4123 spin_lock_irq(shost->host_lock);
4124 vport->load_flag &= ~FC_LOADING;
4125 spin_unlock_irq(shost->host_lock);
4126}
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136static void
4137lpfc_stop_port_s3(struct lpfc_hba *phba)
4138{
4139
4140 writel(0, phba->HCregaddr);
4141 readl(phba->HCregaddr);
4142
4143 writel(0xffffffff, phba->HAregaddr);
4144 readl(phba->HAregaddr);
4145
4146
4147 lpfc_stop_hba_timers(phba);
4148 phba->pport->work_port_events = 0;
4149}
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159static void
4160lpfc_stop_port_s4(struct lpfc_hba *phba)
4161{
4162
4163 lpfc_stop_hba_timers(phba);
4164 phba->pport->work_port_events = 0;
4165 phba->sli4_hba.intr_enable = 0;
4166}
4167
4168
4169
4170
4171
4172
4173
4174
4175void
4176lpfc_stop_port(struct lpfc_hba *phba)
4177{
4178 phba->lpfc_stop_port(phba);
4179
4180 if (phba->wq)
4181 flush_workqueue(phba->wq);
4182}
4183
4184
4185
4186
4187
4188
4189
4190void
4191lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
4192{
4193 unsigned long fcf_redisc_wait_tmo =
4194 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
4195
4196 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
4197 spin_lock_irq(&phba->hbalock);
4198
4199 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
4200
4201 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
4202 spin_unlock_irq(&phba->hbalock);
4203}
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215static void
4216lpfc_sli4_fcf_redisc_wait_tmo(struct timer_list *t)
4217{
4218 struct lpfc_hba *phba = from_timer(phba, t, fcf.redisc_wait);
4219
4220
4221 spin_lock_irq(&phba->hbalock);
4222 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
4223 spin_unlock_irq(&phba->hbalock);
4224 return;
4225 }
4226
4227 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
4228
4229 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
4230 spin_unlock_irq(&phba->hbalock);
4231 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
4232 "2776 FCF rediscover quiescent timer expired\n");
4233
4234 lpfc_worker_wake_up(phba);
4235}
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248static uint16_t
4249lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
4250 struct lpfc_acqe_link *acqe_link)
4251{
4252 uint16_t latt_fault;
4253
4254 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
4255 case LPFC_ASYNC_LINK_FAULT_NONE:
4256 case LPFC_ASYNC_LINK_FAULT_LOCAL:
4257 case LPFC_ASYNC_LINK_FAULT_REMOTE:
4258 latt_fault = 0;
4259 break;
4260 default:
4261 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4262 "0398 Invalid link fault code: x%x\n",
4263 bf_get(lpfc_acqe_link_fault, acqe_link));
4264 latt_fault = MBXERR_ERROR;
4265 break;
4266 }
4267 return latt_fault;
4268}
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280static uint8_t
4281lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
4282 struct lpfc_acqe_link *acqe_link)
4283{
4284 uint8_t att_type;
4285
4286 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
4287 case LPFC_ASYNC_LINK_STATUS_DOWN:
4288 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
4289 att_type = LPFC_ATT_LINK_DOWN;
4290 break;
4291 case LPFC_ASYNC_LINK_STATUS_UP:
4292
4293 att_type = LPFC_ATT_RESERVED;
4294 break;
4295 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
4296 att_type = LPFC_ATT_LINK_UP;
4297 break;
4298 default:
4299 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4300 "0399 Invalid link attention type: x%x\n",
4301 bf_get(lpfc_acqe_link_status, acqe_link));
4302 att_type = LPFC_ATT_RESERVED;
4303 break;
4304 }
4305 return att_type;
4306}
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316uint32_t
4317lpfc_sli_port_speed_get(struct lpfc_hba *phba)
4318{
4319 uint32_t link_speed;
4320
4321 if (!lpfc_is_link_up(phba))
4322 return 0;
4323
4324 if (phba->sli_rev <= LPFC_SLI_REV3) {
4325 switch (phba->fc_linkspeed) {
4326 case LPFC_LINK_SPEED_1GHZ:
4327 link_speed = 1000;
4328 break;
4329 case LPFC_LINK_SPEED_2GHZ:
4330 link_speed = 2000;
4331 break;
4332 case LPFC_LINK_SPEED_4GHZ:
4333 link_speed = 4000;
4334 break;
4335 case LPFC_LINK_SPEED_8GHZ:
4336 link_speed = 8000;
4337 break;
4338 case LPFC_LINK_SPEED_10GHZ:
4339 link_speed = 10000;
4340 break;
4341 case LPFC_LINK_SPEED_16GHZ:
4342 link_speed = 16000;
4343 break;
4344 default:
4345 link_speed = 0;
4346 }
4347 } else {
4348 if (phba->sli4_hba.link_state.logical_speed)
4349 link_speed =
4350 phba->sli4_hba.link_state.logical_speed;
4351 else
4352 link_speed = phba->sli4_hba.link_state.speed;
4353 }
4354 return link_speed;
4355}
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368static uint32_t
4369lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
4370 uint8_t speed_code)
4371{
4372 uint32_t port_speed;
4373
4374 switch (evt_code) {
4375 case LPFC_TRAILER_CODE_LINK:
4376 switch (speed_code) {
4377 case LPFC_ASYNC_LINK_SPEED_ZERO:
4378 port_speed = 0;
4379 break;
4380 case LPFC_ASYNC_LINK_SPEED_10MBPS:
4381 port_speed = 10;
4382 break;
4383 case LPFC_ASYNC_LINK_SPEED_100MBPS:
4384 port_speed = 100;
4385 break;
4386 case LPFC_ASYNC_LINK_SPEED_1GBPS:
4387 port_speed = 1000;
4388 break;
4389 case LPFC_ASYNC_LINK_SPEED_10GBPS:
4390 port_speed = 10000;
4391 break;
4392 case LPFC_ASYNC_LINK_SPEED_20GBPS:
4393 port_speed = 20000;
4394 break;
4395 case LPFC_ASYNC_LINK_SPEED_25GBPS:
4396 port_speed = 25000;
4397 break;
4398 case LPFC_ASYNC_LINK_SPEED_40GBPS:
4399 port_speed = 40000;
4400 break;
4401 default:
4402 port_speed = 0;
4403 }
4404 break;
4405 case LPFC_TRAILER_CODE_FC:
4406 switch (speed_code) {
4407 case LPFC_FC_LA_SPEED_UNKNOWN:
4408 port_speed = 0;
4409 break;
4410 case LPFC_FC_LA_SPEED_1G:
4411 port_speed = 1000;
4412 break;
4413 case LPFC_FC_LA_SPEED_2G:
4414 port_speed = 2000;
4415 break;
4416 case LPFC_FC_LA_SPEED_4G:
4417 port_speed = 4000;
4418 break;
4419 case LPFC_FC_LA_SPEED_8G:
4420 port_speed = 8000;
4421 break;
4422 case LPFC_FC_LA_SPEED_10G:
4423 port_speed = 10000;
4424 break;
4425 case LPFC_FC_LA_SPEED_16G:
4426 port_speed = 16000;
4427 break;
4428 case LPFC_FC_LA_SPEED_32G:
4429 port_speed = 32000;
4430 break;
4431 default:
4432 port_speed = 0;
4433 }
4434 break;
4435 default:
4436 port_speed = 0;
4437 }
4438 return port_speed;
4439}
4440
4441
4442
4443
4444
4445
4446
4447
4448static void
4449lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
4450 struct lpfc_acqe_link *acqe_link)
4451{
4452 struct lpfc_dmabuf *mp;
4453 LPFC_MBOXQ_t *pmb;
4454 MAILBOX_t *mb;
4455 struct lpfc_mbx_read_top *la;
4456 uint8_t att_type;
4457 int rc;
4458
4459 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
4460 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
4461 return;
4462 phba->fcoe_eventtag = acqe_link->event_tag;
4463 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
4464 if (!pmb) {
4465 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4466 "0395 The mboxq allocation failed\n");
4467 return;
4468 }
4469 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
4470 if (!mp) {
4471 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4472 "0396 The lpfc_dmabuf allocation failed\n");
4473 goto out_free_pmb;
4474 }
4475 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
4476 if (!mp->virt) {
4477 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4478 "0397 The mbuf allocation failed\n");
4479 goto out_free_dmabuf;
4480 }
4481
4482
4483 lpfc_els_flush_all_cmd(phba);
4484
4485
4486 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
4487
4488
4489 phba->sli.slistat.link_event++;
4490
4491
4492 lpfc_read_topology(phba, pmb, mp);
4493 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
4494 pmb->vport = phba->pport;
4495
4496
4497 phba->sli4_hba.link_state.speed =
4498 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
4499 bf_get(lpfc_acqe_link_speed, acqe_link));
4500 phba->sli4_hba.link_state.duplex =
4501 bf_get(lpfc_acqe_link_duplex, acqe_link);
4502 phba->sli4_hba.link_state.status =
4503 bf_get(lpfc_acqe_link_status, acqe_link);
4504 phba->sli4_hba.link_state.type =
4505 bf_get(lpfc_acqe_link_type, acqe_link);
4506 phba->sli4_hba.link_state.number =
4507 bf_get(lpfc_acqe_link_number, acqe_link);
4508 phba->sli4_hba.link_state.fault =
4509 bf_get(lpfc_acqe_link_fault, acqe_link);
4510 phba->sli4_hba.link_state.logical_speed =
4511 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
4512
4513 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4514 "2900 Async FC/FCoE Link event - Speed:%dGBit "
4515 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
4516 "Logical speed:%dMbps Fault:%d\n",
4517 phba->sli4_hba.link_state.speed,
4518 phba->sli4_hba.link_state.topology,
4519 phba->sli4_hba.link_state.status,
4520 phba->sli4_hba.link_state.type,
4521 phba->sli4_hba.link_state.number,
4522 phba->sli4_hba.link_state.logical_speed,
4523 phba->sli4_hba.link_state.fault);
4524
4525
4526
4527
4528 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
4529 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
4530 if (rc == MBX_NOT_FINISHED)
4531 goto out_free_dmabuf;
4532 return;
4533 }
4534
4535
4536
4537
4538
4539
4540 mb = &pmb->u.mb;
4541 mb->mbxStatus = lpfc_sli4_parse_latt_fault(phba, acqe_link);
4542
4543
4544 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
4545 la->eventTag = acqe_link->event_tag;
4546 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
4547 bf_set(lpfc_mbx_read_top_link_spd, la,
4548 (bf_get(lpfc_acqe_link_speed, acqe_link)));
4549
4550
4551 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
4552 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
4553 bf_set(lpfc_mbx_read_top_il, la, 0);
4554 bf_set(lpfc_mbx_read_top_pb, la, 0);
4555 bf_set(lpfc_mbx_read_top_fa, la, 0);
4556 bf_set(lpfc_mbx_read_top_mm, la, 0);
4557
4558
4559 lpfc_mbx_cmpl_read_topology(phba, pmb);
4560
4561 return;
4562
4563out_free_dmabuf:
4564 kfree(mp);
4565out_free_pmb:
4566 mempool_free(pmb, phba->mbox_mem_pool);
4567}
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578static void
4579lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
4580{
4581 struct lpfc_dmabuf *mp;
4582 LPFC_MBOXQ_t *pmb;
4583 MAILBOX_t *mb;
4584 struct lpfc_mbx_read_top *la;
4585 int rc;
4586
4587 if (bf_get(lpfc_trailer_type, acqe_fc) !=
4588 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
4589 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4590 "2895 Non FC link Event detected.(%d)\n",
4591 bf_get(lpfc_trailer_type, acqe_fc));
4592 return;
4593 }
4594
4595 phba->sli4_hba.link_state.speed =
4596 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
4597 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
4598 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
4599 phba->sli4_hba.link_state.topology =
4600 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
4601 phba->sli4_hba.link_state.status =
4602 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
4603 phba->sli4_hba.link_state.type =
4604 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
4605 phba->sli4_hba.link_state.number =
4606 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
4607 phba->sli4_hba.link_state.fault =
4608 bf_get(lpfc_acqe_link_fault, acqe_fc);
4609 phba->sli4_hba.link_state.logical_speed =
4610 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
4611 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4612 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
4613 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
4614 "%dMbps Fault:%d\n",
4615 phba->sli4_hba.link_state.speed,
4616 phba->sli4_hba.link_state.topology,
4617 phba->sli4_hba.link_state.status,
4618 phba->sli4_hba.link_state.type,
4619 phba->sli4_hba.link_state.number,
4620 phba->sli4_hba.link_state.logical_speed,
4621 phba->sli4_hba.link_state.fault);
4622 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
4623 if (!pmb) {
4624 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4625 "2897 The mboxq allocation failed\n");
4626 return;
4627 }
4628 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
4629 if (!mp) {
4630 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4631 "2898 The lpfc_dmabuf allocation failed\n");
4632 goto out_free_pmb;
4633 }
4634 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
4635 if (!mp->virt) {
4636 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4637 "2899 The mbuf allocation failed\n");
4638 goto out_free_dmabuf;
4639 }
4640
4641
4642 lpfc_els_flush_all_cmd(phba);
4643
4644
4645 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
4646
4647
4648 phba->sli.slistat.link_event++;
4649
4650
4651 lpfc_read_topology(phba, pmb, mp);
4652 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
4653 pmb->vport = phba->pport;
4654
4655 if (phba->sli4_hba.link_state.status != LPFC_FC_LA_TYPE_LINK_UP) {
4656 phba->link_flag &= ~(LS_MDS_LINK_DOWN | LS_MDS_LOOPBACK);
4657
4658 switch (phba->sli4_hba.link_state.status) {
4659 case LPFC_FC_LA_TYPE_MDS_LINK_DOWN:
4660 phba->link_flag |= LS_MDS_LINK_DOWN;
4661 break;
4662 case LPFC_FC_LA_TYPE_MDS_LOOPBACK:
4663 phba->link_flag |= LS_MDS_LOOPBACK;
4664 break;
4665 default:
4666 break;
4667 }
4668
4669
4670 mb = &pmb->u.mb;
4671 mb->mbxStatus = lpfc_sli4_parse_latt_fault(phba,
4672 (void *)acqe_fc);
4673
4674
4675 la = (struct lpfc_mbx_read_top *)&pmb->u.mb.un.varReadTop;
4676 la->eventTag = acqe_fc->event_tag;
4677
4678 if (phba->sli4_hba.link_state.status ==
4679 LPFC_FC_LA_TYPE_UNEXP_WWPN) {
4680 bf_set(lpfc_mbx_read_top_att_type, la,
4681 LPFC_FC_LA_TYPE_UNEXP_WWPN);
4682 } else {
4683 bf_set(lpfc_mbx_read_top_att_type, la,
4684 LPFC_FC_LA_TYPE_LINK_DOWN);
4685 }
4686
4687 lpfc_mbx_cmpl_read_topology(phba, pmb);
4688
4689 return;
4690 }
4691
4692 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
4693 if (rc == MBX_NOT_FINISHED)
4694 goto out_free_dmabuf;
4695 return;
4696
4697out_free_dmabuf:
4698 kfree(mp);
4699out_free_pmb:
4700 mempool_free(pmb, phba->mbox_mem_pool);
4701}
4702
4703
4704
4705
4706
4707
4708
4709
4710static void
4711lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
4712{
4713 char port_name;
4714 char message[128];
4715 uint8_t status;
4716 uint8_t evt_type;
4717 uint8_t operational = 0;
4718 struct temp_event temp_event_data;
4719 struct lpfc_acqe_misconfigured_event *misconfigured;
4720 struct Scsi_Host *shost;
4721
4722 evt_type = bf_get(lpfc_trailer_type, acqe_sli);
4723
4724 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4725 "2901 Async SLI event - Event Data1:x%08x Event Data2:"
4726 "x%08x SLI Event Type:%d\n",
4727 acqe_sli->event_data1, acqe_sli->event_data2,
4728 evt_type);
4729
4730 port_name = phba->Port[0];
4731 if (port_name == 0x00)
4732 port_name = '?';
4733
4734 switch (evt_type) {
4735 case LPFC_SLI_EVENT_TYPE_OVER_TEMP:
4736 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
4737 temp_event_data.event_code = LPFC_THRESHOLD_TEMP;
4738 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
4739
4740 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
4741 "3190 Over Temperature:%d Celsius- Port Name %c\n",
4742 acqe_sli->event_data1, port_name);
4743
4744 phba->sfp_warning |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
4745 shost = lpfc_shost_from_vport(phba->pport);
4746 fc_host_post_vendor_event(shost, fc_get_event_number(),
4747 sizeof(temp_event_data),
4748 (char *)&temp_event_data,
4749 SCSI_NL_VID_TYPE_PCI
4750 | PCI_VENDOR_ID_EMULEX);
4751 break;
4752 case LPFC_SLI_EVENT_TYPE_NORM_TEMP:
4753 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
4754 temp_event_data.event_code = LPFC_NORMAL_TEMP;
4755 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
4756
4757 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4758 "3191 Normal Temperature:%d Celsius - Port Name %c\n",
4759 acqe_sli->event_data1, port_name);
4760
4761 shost = lpfc_shost_from_vport(phba->pport);
4762 fc_host_post_vendor_event(shost, fc_get_event_number(),
4763 sizeof(temp_event_data),
4764 (char *)&temp_event_data,
4765 SCSI_NL_VID_TYPE_PCI
4766 | PCI_VENDOR_ID_EMULEX);
4767 break;
4768 case LPFC_SLI_EVENT_TYPE_MISCONFIGURED:
4769 misconfigured = (struct lpfc_acqe_misconfigured_event *)
4770 &acqe_sli->event_data1;
4771
4772
4773 switch (phba->sli4_hba.lnk_info.lnk_no) {
4774 case LPFC_LINK_NUMBER_0:
4775 status = bf_get(lpfc_sli_misconfigured_port0_state,
4776 &misconfigured->theEvent);
4777 operational = bf_get(lpfc_sli_misconfigured_port0_op,
4778 &misconfigured->theEvent);
4779 break;
4780 case LPFC_LINK_NUMBER_1:
4781 status = bf_get(lpfc_sli_misconfigured_port1_state,
4782 &misconfigured->theEvent);
4783 operational = bf_get(lpfc_sli_misconfigured_port1_op,
4784 &misconfigured->theEvent);
4785 break;
4786 case LPFC_LINK_NUMBER_2:
4787 status = bf_get(lpfc_sli_misconfigured_port2_state,
4788 &misconfigured->theEvent);
4789 operational = bf_get(lpfc_sli_misconfigured_port2_op,
4790 &misconfigured->theEvent);
4791 break;
4792 case LPFC_LINK_NUMBER_3:
4793 status = bf_get(lpfc_sli_misconfigured_port3_state,
4794 &misconfigured->theEvent);
4795 operational = bf_get(lpfc_sli_misconfigured_port3_op,
4796 &misconfigured->theEvent);
4797 break;
4798 default:
4799 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4800 "3296 "
4801 "LPFC_SLI_EVENT_TYPE_MISCONFIGURED "
4802 "event: Invalid link %d",
4803 phba->sli4_hba.lnk_info.lnk_no);
4804 return;
4805 }
4806
4807
4808 if (phba->sli4_hba.lnk_info.optic_state == status)
4809 return;
4810
4811 switch (status) {
4812 case LPFC_SLI_EVENT_STATUS_VALID:
4813 sprintf(message, "Physical Link is functional");
4814 break;
4815 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
4816 sprintf(message, "Optics faulted/incorrectly "
4817 "installed/not installed - Reseat optics, "
4818 "if issue not resolved, replace.");
4819 break;
4820 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
4821 sprintf(message,
4822 "Optics of two types installed - Remove one "
4823 "optic or install matching pair of optics.");
4824 break;
4825 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
4826 sprintf(message, "Incompatible optics - Replace with "
4827 "compatible optics for card to function.");
4828 break;
4829 case LPFC_SLI_EVENT_STATUS_UNQUALIFIED:
4830 sprintf(message, "Unqualified optics - Replace with "
4831 "Avago optics for Warranty and Technical "
4832 "Support - Link is%s operational",
4833 (operational) ? " not" : "");
4834 break;
4835 case LPFC_SLI_EVENT_STATUS_UNCERTIFIED:
4836 sprintf(message, "Uncertified optics - Replace with "
4837 "Avago-certified optics to enable link "
4838 "operation - Link is%s operational",
4839 (operational) ? " not" : "");
4840 break;
4841 default:
4842
4843 sprintf(message, "Unknown event status x%02x", status);
4844 break;
4845 }
4846 phba->sli4_hba.lnk_info.optic_state = status;
4847 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4848 "3176 Port Name %c %s\n", port_name, message);
4849 break;
4850 case LPFC_SLI_EVENT_TYPE_REMOTE_DPORT:
4851 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4852 "3192 Remote DPort Test Initiated - "
4853 "Event Data1:x%08x Event Data2: x%08x\n",
4854 acqe_sli->event_data1, acqe_sli->event_data2);
4855 break;
4856 default:
4857 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4858 "3193 Async SLI event - Event Data1:x%08x Event Data2:"
4859 "x%08x SLI Event Type:%d\n",
4860 acqe_sli->event_data1, acqe_sli->event_data2,
4861 evt_type);
4862 break;
4863 }
4864}
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876static struct lpfc_nodelist *
4877lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
4878{
4879 struct lpfc_nodelist *ndlp;
4880 struct Scsi_Host *shost;
4881 struct lpfc_hba *phba;
4882
4883 if (!vport)
4884 return NULL;
4885 phba = vport->phba;
4886 if (!phba)
4887 return NULL;
4888 ndlp = lpfc_findnode_did(vport, Fabric_DID);
4889 if (!ndlp) {
4890
4891 ndlp = lpfc_nlp_init(vport, Fabric_DID);
4892 if (!ndlp)
4893 return 0;
4894
4895 ndlp->nlp_type |= NLP_FABRIC;
4896
4897 lpfc_enqueue_node(vport, ndlp);
4898 } else if (!NLP_CHK_NODE_ACT(ndlp)) {
4899
4900 ndlp = lpfc_enable_node(vport, ndlp, NLP_STE_UNUSED_NODE);
4901 if (!ndlp)
4902 return 0;
4903 }
4904 if ((phba->pport->port_state < LPFC_FLOGI) &&
4905 (phba->pport->port_state != LPFC_VPORT_FAILED))
4906 return NULL;
4907
4908 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
4909 && (vport->port_state != LPFC_VPORT_FAILED))
4910 return NULL;
4911 shost = lpfc_shost_from_vport(vport);
4912 if (!shost)
4913 return NULL;
4914 lpfc_linkdown_port(vport);
4915 lpfc_cleanup_pending_mbox(vport);
4916 spin_lock_irq(shost->host_lock);
4917 vport->fc_flag |= FC_VPORT_CVL_RCVD;
4918 spin_unlock_irq(shost->host_lock);
4919
4920 return ndlp;
4921}
4922
4923
4924
4925
4926
4927
4928
4929
4930static void
4931lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
4932{
4933 struct lpfc_vport **vports;
4934 int i;
4935
4936 vports = lpfc_create_vport_work_array(phba);
4937 if (vports)
4938 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
4939 lpfc_sli4_perform_vport_cvl(vports[i]);
4940 lpfc_destroy_vport_work_array(phba, vports);
4941}
4942
4943
4944
4945
4946
4947
4948
4949
4950static void
4951lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
4952 struct lpfc_acqe_fip *acqe_fip)
4953{
4954 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
4955 int rc;
4956 struct lpfc_vport *vport;
4957 struct lpfc_nodelist *ndlp;
4958 struct Scsi_Host *shost;
4959 int active_vlink_present;
4960 struct lpfc_vport **vports;
4961 int i;
4962
4963 phba->fc_eventTag = acqe_fip->event_tag;
4964 phba->fcoe_eventtag = acqe_fip->event_tag;
4965 switch (event_type) {
4966 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
4967 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
4968 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
4969 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
4970 LOG_DISCOVERY,
4971 "2546 New FCF event, evt_tag:x%x, "
4972 "index:x%x\n",
4973 acqe_fip->event_tag,
4974 acqe_fip->index);
4975 else
4976 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
4977 LOG_DISCOVERY,
4978 "2788 FCF param modified event, "
4979 "evt_tag:x%x, index:x%x\n",
4980 acqe_fip->event_tag,
4981 acqe_fip->index);
4982 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
4983
4984
4985
4986
4987
4988 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
4989 LOG_DISCOVERY,
4990 "2779 Read FCF (x%x) for updating "
4991 "roundrobin FCF failover bmask\n",
4992 acqe_fip->index);
4993 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
4994 }
4995
4996
4997 spin_lock_irq(&phba->hbalock);
4998 if (phba->hba_flag & FCF_TS_INPROG) {
4999 spin_unlock_irq(&phba->hbalock);
5000 break;
5001 }
5002
5003 if (phba->fcf.fcf_flag & FCF_REDISC_EVT) {
5004 spin_unlock_irq(&phba->hbalock);
5005 break;
5006 }
5007
5008
5009 if (phba->fcf.fcf_flag & FCF_SCAN_DONE) {
5010 spin_unlock_irq(&phba->hbalock);
5011 break;
5012 }
5013 spin_unlock_irq(&phba->hbalock);
5014
5015
5016 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5017 "2770 Start FCF table scan per async FCF "
5018 "event, evt_tag:x%x, index:x%x\n",
5019 acqe_fip->event_tag, acqe_fip->index);
5020 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
5021 LPFC_FCOE_FCF_GET_FIRST);
5022 if (rc)
5023 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5024 "2547 Issue FCF scan read FCF mailbox "
5025 "command failed (x%x)\n", rc);
5026 break;
5027
5028 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
5029 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5030 "2548 FCF Table full count 0x%x tag 0x%x\n",
5031 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
5032 acqe_fip->event_tag);
5033 break;
5034
5035 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
5036 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
5037 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5038 "2549 FCF (x%x) disconnected from network, "
5039 "tag:x%x\n", acqe_fip->index, acqe_fip->event_tag);
5040
5041
5042
5043
5044 spin_lock_irq(&phba->hbalock);
5045 if ((phba->fcf.fcf_flag & FCF_DISCOVERY) &&
5046 (phba->fcf.current_rec.fcf_indx != acqe_fip->index)) {
5047 spin_unlock_irq(&phba->hbalock);
5048
5049 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
5050 break;
5051 }
5052 spin_unlock_irq(&phba->hbalock);
5053
5054
5055 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
5056 break;
5057
5058
5059
5060
5061
5062
5063
5064 spin_lock_irq(&phba->hbalock);
5065
5066 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
5067 spin_unlock_irq(&phba->hbalock);
5068
5069 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5070 "2771 Start FCF fast failover process due to "
5071 "FCF DEAD event: evt_tag:x%x, fcf_index:x%x "
5072 "\n", acqe_fip->event_tag, acqe_fip->index);
5073 rc = lpfc_sli4_redisc_fcf_table(phba);
5074 if (rc) {
5075 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5076 LOG_DISCOVERY,
5077 "2772 Issue FCF rediscover mabilbox "
5078 "command failed, fail through to FCF "
5079 "dead event\n");
5080 spin_lock_irq(&phba->hbalock);
5081 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
5082 spin_unlock_irq(&phba->hbalock);
5083
5084
5085
5086
5087 lpfc_sli4_fcf_dead_failthrough(phba);
5088 } else {
5089
5090 lpfc_sli4_clear_fcf_rr_bmask(phba);
5091
5092
5093
5094
5095 lpfc_sli4_perform_all_vport_cvl(phba);
5096 }
5097 break;
5098 case LPFC_FIP_EVENT_TYPE_CVL:
5099 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
5100 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5101 "2718 Clear Virtual Link Received for VPI 0x%x"
5102 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
5103
5104 vport = lpfc_find_vport_by_vpid(phba,
5105 acqe_fip->index);
5106 ndlp = lpfc_sli4_perform_vport_cvl(vport);
5107 if (!ndlp)
5108 break;
5109 active_vlink_present = 0;
5110
5111 vports = lpfc_create_vport_work_array(phba);
5112 if (vports) {
5113 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5114 i++) {
5115 if ((!(vports[i]->fc_flag &
5116 FC_VPORT_CVL_RCVD)) &&
5117 (vports[i]->port_state > LPFC_FDISC)) {
5118 active_vlink_present = 1;
5119 break;
5120 }
5121 }
5122 lpfc_destroy_vport_work_array(phba, vports);
5123 }
5124
5125
5126
5127
5128
5129
5130 if (!(vport->load_flag & FC_UNLOADING) &&
5131 active_vlink_present) {
5132
5133
5134
5135
5136 mod_timer(&ndlp->nlp_delayfunc,
5137 jiffies + msecs_to_jiffies(1000));
5138 shost = lpfc_shost_from_vport(vport);
5139 spin_lock_irq(shost->host_lock);
5140 ndlp->nlp_flag |= NLP_DELAY_TMO;
5141 spin_unlock_irq(shost->host_lock);
5142 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
5143 vport->port_state = LPFC_FDISC;
5144 } else {
5145
5146
5147
5148
5149
5150
5151
5152 spin_lock_irq(&phba->hbalock);
5153 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
5154 spin_unlock_irq(&phba->hbalock);
5155 break;
5156 }
5157
5158 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
5159 spin_unlock_irq(&phba->hbalock);
5160 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5161 LOG_DISCOVERY,
5162 "2773 Start FCF failover per CVL, "
5163 "evt_tag:x%x\n", acqe_fip->event_tag);
5164 rc = lpfc_sli4_redisc_fcf_table(phba);
5165 if (rc) {
5166 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5167 LOG_DISCOVERY,
5168 "2774 Issue FCF rediscover "
5169 "mabilbox command failed, "
5170 "through to CVL event\n");
5171 spin_lock_irq(&phba->hbalock);
5172 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
5173 spin_unlock_irq(&phba->hbalock);
5174
5175
5176
5177
5178 lpfc_retry_pport_discovery(phba);
5179 } else
5180
5181
5182
5183
5184 lpfc_sli4_clear_fcf_rr_bmask(phba);
5185 }
5186 break;
5187 default:
5188 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5189 "0288 Unknown FCoE event type 0x%x event tag "
5190 "0x%x\n", event_type, acqe_fip->event_tag);
5191 break;
5192 }
5193}
5194
5195
5196
5197
5198
5199
5200
5201
5202static void
5203lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
5204 struct lpfc_acqe_dcbx *acqe_dcbx)
5205{
5206 phba->fc_eventTag = acqe_dcbx->event_tag;
5207 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5208 "0290 The SLI4 DCBX asynchronous event is not "
5209 "handled yet\n");
5210}
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221static void
5222lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
5223 struct lpfc_acqe_grp5 *acqe_grp5)
5224{
5225 uint16_t prev_ll_spd;
5226
5227 phba->fc_eventTag = acqe_grp5->event_tag;
5228 phba->fcoe_eventtag = acqe_grp5->event_tag;
5229 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
5230 phba->sli4_hba.link_state.logical_speed =
5231 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
5232 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5233 "2789 GRP5 Async Event: Updating logical link speed "
5234 "from %dMbps to %dMbps\n", prev_ll_spd,
5235 phba->sli4_hba.link_state.logical_speed);
5236}
5237
5238
5239
5240
5241
5242
5243
5244
5245void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
5246{
5247 struct lpfc_cq_event *cq_event;
5248
5249
5250 spin_lock_irq(&phba->hbalock);
5251 phba->hba_flag &= ~ASYNC_EVENT;
5252 spin_unlock_irq(&phba->hbalock);
5253
5254 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
5255
5256 spin_lock_irq(&phba->hbalock);
5257 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
5258 cq_event, struct lpfc_cq_event, list);
5259 spin_unlock_irq(&phba->hbalock);
5260
5261 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
5262 case LPFC_TRAILER_CODE_LINK:
5263 lpfc_sli4_async_link_evt(phba,
5264 &cq_event->cqe.acqe_link);
5265 break;
5266 case LPFC_TRAILER_CODE_FCOE:
5267 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
5268 break;
5269 case LPFC_TRAILER_CODE_DCBX:
5270 lpfc_sli4_async_dcbx_evt(phba,
5271 &cq_event->cqe.acqe_dcbx);
5272 break;
5273 case LPFC_TRAILER_CODE_GRP5:
5274 lpfc_sli4_async_grp5_evt(phba,
5275 &cq_event->cqe.acqe_grp5);
5276 break;
5277 case LPFC_TRAILER_CODE_FC:
5278 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
5279 break;
5280 case LPFC_TRAILER_CODE_SLI:
5281 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
5282 break;
5283 default:
5284 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5285 "1804 Invalid asynchrous event code: "
5286 "x%x\n", bf_get(lpfc_trailer_code,
5287 &cq_event->cqe.mcqe_cmpl));
5288 break;
5289 }
5290
5291 lpfc_sli4_cq_event_release(phba, cq_event);
5292 }
5293}
5294
5295
5296
5297
5298
5299
5300
5301
5302void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
5303{
5304 int rc;
5305
5306 spin_lock_irq(&phba->hbalock);
5307
5308 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
5309
5310 phba->fcf.failover_rec.flag = 0;
5311
5312 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
5313 spin_unlock_irq(&phba->hbalock);
5314
5315
5316 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5317 "2777 Start post-quiescent FCF table scan\n");
5318 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
5319 if (rc)
5320 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5321 "2747 Issue FCF scan read FCF mailbox "
5322 "command failed 0x%x\n", rc);
5323}
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335int
5336lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
5337{
5338 int rc;
5339
5340
5341 phba->pci_dev_grp = dev_grp;
5342
5343
5344 if (dev_grp == LPFC_PCI_DEV_OC)
5345 phba->sli_rev = LPFC_SLI_REV4;
5346
5347
5348 rc = lpfc_init_api_table_setup(phba, dev_grp);
5349 if (rc)
5350 return -ENODEV;
5351
5352 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
5353 if (rc)
5354 return -ENODEV;
5355
5356 rc = lpfc_sli_api_table_setup(phba, dev_grp);
5357 if (rc)
5358 return -ENODEV;
5359
5360 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
5361 if (rc)
5362 return -ENODEV;
5363
5364 return 0;
5365}
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
5376{
5377 switch (intr_mode) {
5378 case 0:
5379 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5380 "0470 Enable INTx interrupt mode.\n");
5381 break;
5382 case 1:
5383 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5384 "0481 Enabled MSI interrupt mode.\n");
5385 break;
5386 case 2:
5387 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5388 "0480 Enabled MSI-X interrupt mode.\n");
5389 break;
5390 default:
5391 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5392 "0482 Illegal interrupt mode.\n");
5393 break;
5394 }
5395 return;
5396}
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409static int
5410lpfc_enable_pci_dev(struct lpfc_hba *phba)
5411{
5412 struct pci_dev *pdev;
5413
5414
5415 if (!phba->pcidev)
5416 goto out_error;
5417 else
5418 pdev = phba->pcidev;
5419
5420 if (pci_enable_device_mem(pdev))
5421 goto out_error;
5422
5423 if (pci_request_mem_regions(pdev, LPFC_DRIVER_NAME))
5424 goto out_disable_device;
5425
5426 pci_set_master(pdev);
5427 pci_try_set_mwi(pdev);
5428 pci_save_state(pdev);
5429
5430
5431 if (pci_is_pcie(pdev))
5432 pdev->needs_freset = 1;
5433
5434 return 0;
5435
5436out_disable_device:
5437 pci_disable_device(pdev);
5438out_error:
5439 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5440 "1401 Failed to enable pci device\n");
5441 return -ENODEV;
5442}
5443
5444
5445
5446
5447
5448
5449
5450
5451static void
5452lpfc_disable_pci_dev(struct lpfc_hba *phba)
5453{
5454 struct pci_dev *pdev;
5455
5456
5457 if (!phba->pcidev)
5458 return;
5459 else
5460 pdev = phba->pcidev;
5461
5462 pci_release_mem_regions(pdev);
5463 pci_disable_device(pdev);
5464
5465 return;
5466}
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477void
5478lpfc_reset_hba(struct lpfc_hba *phba)
5479{
5480
5481 if (!phba->cfg_enable_hba_reset) {
5482 phba->link_state = LPFC_HBA_ERROR;
5483 return;
5484 }
5485 if (phba->sli.sli_flag & LPFC_SLI_ACTIVE)
5486 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
5487 else
5488 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
5489 lpfc_offline(phba);
5490 lpfc_sli_brdrestart(phba);
5491 lpfc_online(phba);
5492 lpfc_unblock_mgmt_io(phba);
5493}
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505uint16_t
5506lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
5507{
5508 struct pci_dev *pdev = phba->pcidev;
5509 uint16_t nr_virtfn;
5510 int pos;
5511
5512 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
5513 if (pos == 0)
5514 return 0;
5515
5516 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
5517 return nr_virtfn;
5518}
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531int
5532lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
5533{
5534 struct pci_dev *pdev = phba->pcidev;
5535 uint16_t max_nr_vfn;
5536 int rc;
5537
5538 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
5539 if (nr_vfn > max_nr_vfn) {
5540 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5541 "3057 Requested vfs (%d) greater than "
5542 "supported vfs (%d)", nr_vfn, max_nr_vfn);
5543 return -EINVAL;
5544 }
5545
5546 rc = pci_enable_sriov(pdev, nr_vfn);
5547 if (rc) {
5548 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
5549 "2806 Failed to enable sriov on this device "
5550 "with vfn number nr_vf:%d, rc:%d\n",
5551 nr_vfn, rc);
5552 } else
5553 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
5554 "2807 Successful enable sriov on this device "
5555 "with vfn number nr_vf:%d\n", nr_vfn);
5556 return rc;
5557}
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570static int
5571lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
5572{
5573 struct lpfc_sli *psli = &phba->sli;
5574
5575
5576
5577
5578 atomic_set(&phba->fast_event_count, 0);
5579 spin_lock_init(&phba->hbalock);
5580
5581
5582 spin_lock_init(&phba->ndlp_lock);
5583
5584 INIT_LIST_HEAD(&phba->port_list);
5585 INIT_LIST_HEAD(&phba->work_list);
5586 init_waitqueue_head(&phba->wait_4_mlo_m_q);
5587
5588
5589 init_waitqueue_head(&phba->work_waitq);
5590
5591 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5592 "1403 Protocols supported %s %s %s\n",
5593 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) ?
5594 "SCSI" : " "),
5595 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) ?
5596 "NVME" : " "),
5597 (phba->nvmet_support ? "NVMET" : " "));
5598
5599 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
5600
5601 spin_lock_init(&phba->scsi_buf_list_get_lock);
5602 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
5603 spin_lock_init(&phba->scsi_buf_list_put_lock);
5604 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
5605 }
5606
5607 if ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) &&
5608 (phba->nvmet_support == 0)) {
5609
5610 spin_lock_init(&phba->nvme_buf_list_get_lock);
5611 INIT_LIST_HEAD(&phba->lpfc_nvme_buf_list_get);
5612 spin_lock_init(&phba->nvme_buf_list_put_lock);
5613 INIT_LIST_HEAD(&phba->lpfc_nvme_buf_list_put);
5614 }
5615
5616
5617 INIT_LIST_HEAD(&phba->fabric_iocb_list);
5618
5619
5620 INIT_LIST_HEAD(&phba->elsbuf);
5621
5622
5623 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
5624
5625
5626 spin_lock_init(&phba->devicelock);
5627 INIT_LIST_HEAD(&phba->luns);
5628
5629
5630 timer_setup(&psli->mbox_tmo, lpfc_mbox_timeout, 0);
5631
5632 timer_setup(&phba->fabric_block_timer, lpfc_fabric_block_timeout, 0);
5633
5634 timer_setup(&phba->eratt_poll, lpfc_poll_eratt, 0);
5635
5636 timer_setup(&phba->hb_tmofunc, lpfc_hb_timeout, 0);
5637
5638 return 0;
5639}
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652static int
5653lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
5654{
5655 int rc;
5656
5657
5658
5659
5660
5661
5662 timer_setup(&phba->fcp_poll_timer, lpfc_poll_timeout, 0);
5663
5664
5665 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
5666 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
5667
5668
5669 lpfc_get_cfgparam(phba);
5670
5671
5672 rc = lpfc_setup_driver_resource_phase1(phba);
5673 if (rc)
5674 return -ENODEV;
5675
5676 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
5677 phba->menlo_flag |= HBA_MENLO_SUPPORT;
5678
5679 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
5680 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
5681 }
5682
5683 if (!phba->sli.sli3_ring)
5684 phba->sli.sli3_ring = kzalloc(LPFC_SLI3_MAX_RING *
5685 sizeof(struct lpfc_sli_ring), GFP_KERNEL);
5686 if (!phba->sli.sli3_ring)
5687 return -ENOMEM;
5688
5689
5690
5691
5692
5693
5694
5695 lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
5696 lpfc_template_no_hr.sg_tablesize = phba->cfg_sg_seg_cnt;
5697 lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
5698
5699
5700 if (phba->cfg_enable_bg) {
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
5711 sizeof(struct fcp_rsp) +
5712 (LPFC_MAX_SG_SEG_CNT * sizeof(struct ulp_bde64));
5713
5714 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
5715 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
5716
5717
5718 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
5719 } else {
5720
5721
5722
5723
5724
5725 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
5726 sizeof(struct fcp_rsp) +
5727 ((phba->cfg_sg_seg_cnt + 2) * sizeof(struct ulp_bde64));
5728
5729
5730 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
5731 }
5732
5733 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
5734 "9088 sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
5735 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
5736 phba->cfg_total_seg_cnt);
5737
5738 phba->max_vpi = LPFC_MAX_VPI;
5739
5740 phba->max_vports = 0;
5741
5742
5743
5744
5745 lpfc_sli_setup(phba);
5746 lpfc_sli_queue_init(phba);
5747
5748
5749 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
5750 return -ENOMEM;
5751
5752
5753
5754
5755
5756 if (phba->cfg_sriov_nr_virtfn > 0) {
5757 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
5758 phba->cfg_sriov_nr_virtfn);
5759 if (rc) {
5760 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
5761 "2808 Requested number of SR-IOV "
5762 "virtual functions (%d) is not "
5763 "supported\n",
5764 phba->cfg_sriov_nr_virtfn);
5765 phba->cfg_sriov_nr_virtfn = 0;
5766 }
5767 }
5768
5769 return 0;
5770}
5771
5772
5773
5774
5775
5776
5777
5778
5779static void
5780lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
5781{
5782
5783 lpfc_mem_free_all(phba);
5784
5785 return;
5786}
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799static int
5800lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
5801{
5802 LPFC_MBOXQ_t *mboxq;
5803 MAILBOX_t *mb;
5804 int rc, i, max_buf_size;
5805 uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
5806 struct lpfc_mqe *mqe;
5807 int longs;
5808 int fof_vectors = 0;
5809 uint64_t wwn;
5810
5811 phba->sli4_hba.num_online_cpu = num_online_cpus();
5812 phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
5813 phba->sli4_hba.curr_disp_cpu = 0;
5814
5815
5816 lpfc_get_cfgparam(phba);
5817
5818
5819 rc = lpfc_setup_driver_resource_phase1(phba);
5820 if (rc)
5821 return -ENODEV;
5822
5823
5824 rc = lpfc_sli4_post_status_check(phba);
5825 if (rc)
5826 return -ENODEV;
5827
5828
5829
5830
5831
5832 timer_setup(&phba->rrq_tmr, lpfc_rrq_timeout, 0);
5833
5834
5835 timer_setup(&phba->fcf.redisc_wait, lpfc_sli4_fcf_redisc_wait_tmo, 0);
5836
5837
5838
5839
5840
5841 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
5842 sizeof(struct lpfc_mbox_ext_buf_ctx));
5843 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
5844
5845 phba->max_vpi = LPFC_MAX_VPI;
5846
5847
5848 phba->max_vports = 0;
5849
5850
5851 phba->valid_vlan = 0;
5852 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
5853 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
5854 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867 max_buf_size = (2 * SLI4_PAGE_SIZE);
5868 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SGL_SEG_CNT - 2)
5869 phba->cfg_sg_seg_cnt = LPFC_MAX_SGL_SEG_CNT - 2;
5870
5871
5872
5873
5874
5875 if (phba->cfg_enable_bg) {
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
5886 sizeof(struct fcp_rsp) + max_buf_size;
5887
5888
5889 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
5890
5891 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SLI4_SEG_CNT_DIF)
5892 phba->cfg_sg_seg_cnt =
5893 LPFC_MAX_SG_SLI4_SEG_CNT_DIF;
5894 } else {
5895
5896
5897
5898
5899
5900 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
5901 sizeof(struct fcp_rsp) +
5902 ((phba->cfg_sg_seg_cnt + 2) *
5903 sizeof(struct sli4_sge));
5904
5905
5906 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
5907
5908
5909
5910
5911
5912 }
5913
5914
5915 lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
5916 lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
5917 lpfc_template_no_hr.sg_tablesize = phba->cfg_sg_seg_cnt;
5918
5919 if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
5920 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
5921 else
5922 phba->cfg_sg_dma_buf_size =
5923 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
5924
5925 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
5926 "9087 sg_tablesize:%d dmabuf_size:%d total_sge:%d\n",
5927 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
5928 phba->cfg_total_seg_cnt);
5929
5930
5931 INIT_LIST_HEAD(&phba->hbqs[LPFC_ELS_HBQ].hbq_buffer_list);
5932 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
5933 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
5934
5935
5936
5937
5938 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
5939
5940 spin_lock_init(&phba->sli4_hba.abts_scsi_buf_list_lock);
5941 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_scsi_buf_list);
5942 }
5943
5944 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
5945
5946 spin_lock_init(&phba->sli4_hba.abts_nvme_buf_list_lock);
5947 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvme_buf_list);
5948 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
5949 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_io_wait_list);
5950
5951
5952 INIT_LIST_HEAD(&phba->sli4_hba.sp_nvme_xri_aborted_work_queue);
5953 }
5954
5955
5956 spin_lock_init(&phba->sli4_hba.sgl_list_lock);
5957 spin_lock_init(&phba->sli4_hba.nvmet_io_wait_lock);
5958
5959
5960
5961
5962
5963
5964 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
5965
5966 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
5967
5968 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
5969
5970 INIT_LIST_HEAD(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue);
5971
5972 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
5973
5974 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
5975
5976
5977 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
5978 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
5979 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
5980 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
5981
5982
5983
5984
5985 INIT_LIST_HEAD(&phba->sli.mboxq);
5986 INIT_LIST_HEAD(&phba->sli.mboxq_cmpl);
5987
5988
5989 phba->sli4_hba.lnk_info.optic_state = 0xff;
5990
5991
5992 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
5993 if (rc)
5994 return -ENOMEM;
5995
5996
5997 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
5998 LPFC_SLI_INTF_IF_TYPE_2) {
5999 rc = lpfc_pci_function_reset(phba);
6000 if (unlikely(rc)) {
6001 rc = -ENODEV;
6002 goto out_free_mem;
6003 }
6004 phba->temp_sensor_support = 1;
6005 }
6006
6007
6008 rc = lpfc_create_bootstrap_mbox(phba);
6009 if (unlikely(rc))
6010 goto out_free_mem;
6011
6012
6013 rc = lpfc_setup_endian_order(phba);
6014 if (unlikely(rc))
6015 goto out_free_bsmbx;
6016
6017
6018 rc = lpfc_sli4_read_config(phba);
6019 if (unlikely(rc))
6020 goto out_free_bsmbx;
6021 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
6022 if (unlikely(rc))
6023 goto out_free_bsmbx;
6024
6025
6026 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
6027 LPFC_SLI_INTF_IF_TYPE_0) {
6028 rc = lpfc_pci_function_reset(phba);
6029 if (unlikely(rc))
6030 goto out_free_bsmbx;
6031 }
6032
6033 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
6034 GFP_KERNEL);
6035 if (!mboxq) {
6036 rc = -ENOMEM;
6037 goto out_free_bsmbx;
6038 }
6039
6040
6041 phba->nvmet_support = 0;
6042 if (lpfc_enable_nvmet_cnt) {
6043
6044
6045 lpfc_read_nv(phba, mboxq);
6046 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6047 if (rc != MBX_SUCCESS) {
6048 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6049 "6016 Mailbox failed , mbxCmd x%x "
6050 "READ_NV, mbxStatus x%x\n",
6051 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
6052 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
6053 mempool_free(mboxq, phba->mbox_mem_pool);
6054 rc = -EIO;
6055 goto out_free_bsmbx;
6056 }
6057 mb = &mboxq->u.mb;
6058 memcpy(&wwn, (char *)mb->un.varRDnvp.nodename,
6059 sizeof(uint64_t));
6060 wwn = cpu_to_be64(wwn);
6061 phba->sli4_hba.wwnn.u.name = wwn;
6062 memcpy(&wwn, (char *)mb->un.varRDnvp.portname,
6063 sizeof(uint64_t));
6064
6065 wwn = cpu_to_be64(wwn);
6066 phba->sli4_hba.wwpn.u.name = wwn;
6067
6068
6069 for (i = 0; i < lpfc_enable_nvmet_cnt; i++) {
6070 if (wwn == lpfc_enable_nvmet[i]) {
6071#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
6072 if (lpfc_nvmet_mem_alloc(phba))
6073 break;
6074
6075 phba->nvmet_support = 1;
6076
6077 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6078 "6017 NVME Target %016llx\n",
6079 wwn);
6080#else
6081 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6082 "6021 Can't enable NVME Target."
6083 " NVME_TARGET_FC infrastructure"
6084 " is not in kernel\n");
6085#endif
6086 break;
6087 }
6088 }
6089 }
6090
6091 lpfc_nvme_mod_param_dep(phba);
6092
6093
6094 lpfc_supported_pages(mboxq);
6095 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6096 if (!rc) {
6097 mqe = &mboxq->u.mqe;
6098 memcpy(&pn_page[0], ((uint8_t *)&mqe->un.supp_pages.word3),
6099 LPFC_MAX_SUPPORTED_PAGES);
6100 for (i = 0; i < LPFC_MAX_SUPPORTED_PAGES; i++) {
6101 switch (pn_page[i]) {
6102 case LPFC_SLI4_PARAMETERS:
6103 phba->sli4_hba.pc_sli4_params.supported = 1;
6104 break;
6105 default:
6106 break;
6107 }
6108 }
6109
6110 if (phba->sli4_hba.pc_sli4_params.supported)
6111 rc = lpfc_pc_sli4_params_get(phba, mboxq);
6112 if (rc) {
6113 mempool_free(mboxq, phba->mbox_mem_pool);
6114 rc = -EIO;
6115 goto out_free_bsmbx;
6116 }
6117 }
6118
6119
6120
6121
6122
6123
6124 rc = lpfc_get_sli4_parameters(phba, mboxq);
6125 if (rc) {
6126 if (phba->sli4_hba.extents_in_use &&
6127 phba->sli4_hba.rpi_hdrs_in_use) {
6128 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6129 "2999 Unsupported SLI4 Parameters "
6130 "Extents and RPI headers enabled.\n");
6131 }
6132 mempool_free(mboxq, phba->mbox_mem_pool);
6133 rc = -EIO;
6134 goto out_free_bsmbx;
6135 }
6136
6137 mempool_free(mboxq, phba->mbox_mem_pool);
6138
6139
6140 lpfc_sli4_oas_verify(phba);
6141 if (phba->cfg_fof)
6142 fof_vectors = 1;
6143
6144
6145 rc = lpfc_sli4_queue_verify(phba);
6146 if (rc)
6147 goto out_free_bsmbx;
6148
6149
6150 rc = lpfc_sli4_cq_event_pool_create(phba);
6151 if (rc)
6152 goto out_free_bsmbx;
6153
6154
6155 lpfc_init_sgl_list(phba);
6156
6157
6158 rc = lpfc_init_active_sgl_array(phba);
6159 if (rc) {
6160 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6161 "1430 Failed to initialize sgl list.\n");
6162 goto out_destroy_cq_event_pool;
6163 }
6164 rc = lpfc_sli4_init_rpi_hdrs(phba);
6165 if (rc) {
6166 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6167 "1432 Failed to initialize rpi headers.\n");
6168 goto out_free_active_sgl;
6169 }
6170
6171
6172 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
6173 phba->fcf.fcf_rr_bmask = kzalloc(longs * sizeof(unsigned long),
6174 GFP_KERNEL);
6175 if (!phba->fcf.fcf_rr_bmask) {
6176 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6177 "2759 Failed allocate memory for FCF round "
6178 "robin failover bmask\n");
6179 rc = -ENOMEM;
6180 goto out_remove_rpi_hdrs;
6181 }
6182
6183 phba->sli4_hba.hba_eq_hdl = kcalloc(fof_vectors + phba->io_channel_irqs,
6184 sizeof(struct lpfc_hba_eq_hdl),
6185 GFP_KERNEL);
6186 if (!phba->sli4_hba.hba_eq_hdl) {
6187 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6188 "2572 Failed allocate memory for "
6189 "fast-path per-EQ handle array\n");
6190 rc = -ENOMEM;
6191 goto out_free_fcf_rr_bmask;
6192 }
6193
6194 phba->sli4_hba.cpu_map = kcalloc(phba->sli4_hba.num_present_cpu,
6195 sizeof(struct lpfc_vector_map_info),
6196 GFP_KERNEL);
6197 if (!phba->sli4_hba.cpu_map) {
6198 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6199 "3327 Failed allocate memory for msi-x "
6200 "interrupt vector mapping\n");
6201 rc = -ENOMEM;
6202 goto out_free_hba_eq_hdl;
6203 }
6204 if (lpfc_used_cpu == NULL) {
6205 lpfc_used_cpu = kcalloc(lpfc_present_cpu, sizeof(uint16_t),
6206 GFP_KERNEL);
6207 if (!lpfc_used_cpu) {
6208 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6209 "3335 Failed allocate memory for msi-x "
6210 "interrupt vector mapping\n");
6211 kfree(phba->sli4_hba.cpu_map);
6212 rc = -ENOMEM;
6213 goto out_free_hba_eq_hdl;
6214 }
6215 for (i = 0; i < lpfc_present_cpu; i++)
6216 lpfc_used_cpu[i] = LPFC_VECTOR_MAP_EMPTY;
6217 }
6218
6219
6220
6221
6222
6223 if (phba->cfg_sriov_nr_virtfn > 0) {
6224 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6225 phba->cfg_sriov_nr_virtfn);
6226 if (rc) {
6227 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6228 "3020 Requested number of SR-IOV "
6229 "virtual functions (%d) is not "
6230 "supported\n",
6231 phba->cfg_sriov_nr_virtfn);
6232 phba->cfg_sriov_nr_virtfn = 0;
6233 }
6234 }
6235
6236 return 0;
6237
6238out_free_hba_eq_hdl:
6239 kfree(phba->sli4_hba.hba_eq_hdl);
6240out_free_fcf_rr_bmask:
6241 kfree(phba->fcf.fcf_rr_bmask);
6242out_remove_rpi_hdrs:
6243 lpfc_sli4_remove_rpi_hdrs(phba);
6244out_free_active_sgl:
6245 lpfc_free_active_sgl(phba);
6246out_destroy_cq_event_pool:
6247 lpfc_sli4_cq_event_pool_destroy(phba);
6248out_free_bsmbx:
6249 lpfc_destroy_bootstrap_mbox(phba);
6250out_free_mem:
6251 lpfc_mem_free(phba);
6252 return rc;
6253}
6254
6255
6256
6257
6258
6259
6260
6261
6262static void
6263lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
6264{
6265 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
6266
6267
6268 kfree(phba->sli4_hba.cpu_map);
6269 phba->sli4_hba.num_present_cpu = 0;
6270 phba->sli4_hba.num_online_cpu = 0;
6271 phba->sli4_hba.curr_disp_cpu = 0;
6272
6273
6274 kfree(phba->sli4_hba.hba_eq_hdl);
6275
6276
6277 lpfc_sli4_remove_rpi_hdrs(phba);
6278 lpfc_sli4_remove_rpis(phba);
6279
6280
6281 kfree(phba->fcf.fcf_rr_bmask);
6282
6283
6284 lpfc_free_active_sgl(phba);
6285 lpfc_free_els_sgl_list(phba);
6286 lpfc_free_nvmet_sgl_list(phba);
6287
6288
6289 lpfc_sli4_cq_event_release_all(phba);
6290 lpfc_sli4_cq_event_pool_destroy(phba);
6291
6292
6293 lpfc_sli4_dealloc_resource_identifiers(phba);
6294
6295
6296 lpfc_destroy_bootstrap_mbox(phba);
6297
6298
6299 lpfc_mem_free_all(phba);
6300
6301
6302 list_for_each_entry_safe(conn_entry, next_conn_entry,
6303 &phba->fcf_conn_rec_list, list) {
6304 list_del_init(&conn_entry->list);
6305 kfree(conn_entry);
6306 }
6307
6308 return;
6309}
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321int
6322lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
6323{
6324 phba->lpfc_hba_init_link = lpfc_hba_init_link;
6325 phba->lpfc_hba_down_link = lpfc_hba_down_link;
6326 phba->lpfc_selective_reset = lpfc_selective_reset;
6327 switch (dev_grp) {
6328 case LPFC_PCI_DEV_LP:
6329 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
6330 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
6331 phba->lpfc_stop_port = lpfc_stop_port_s3;
6332 break;
6333 case LPFC_PCI_DEV_OC:
6334 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
6335 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
6336 phba->lpfc_stop_port = lpfc_stop_port_s4;
6337 break;
6338 default:
6339 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6340 "1431 Invalid HBA PCI-device group: 0x%x\n",
6341 dev_grp);
6342 return -ENODEV;
6343 break;
6344 }
6345 return 0;
6346}
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359static int
6360lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
6361{
6362 int error;
6363
6364
6365 phba->worker_thread = kthread_run(lpfc_do_work, phba,
6366 "lpfc_worker_%d", phba->brd_no);
6367 if (IS_ERR(phba->worker_thread)) {
6368 error = PTR_ERR(phba->worker_thread);
6369 return error;
6370 }
6371
6372
6373 phba->wq = alloc_workqueue("lpfc_wq", WQ_MEM_RECLAIM, 0);
6374
6375 return 0;
6376}
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386static void
6387lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
6388{
6389 if (phba->wq) {
6390 flush_workqueue(phba->wq);
6391 destroy_workqueue(phba->wq);
6392 phba->wq = NULL;
6393 }
6394
6395
6396 kthread_stop(phba->worker_thread);
6397}
6398
6399
6400
6401
6402
6403
6404
6405void
6406lpfc_free_iocb_list(struct lpfc_hba *phba)
6407{
6408 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
6409
6410 spin_lock_irq(&phba->hbalock);
6411 list_for_each_entry_safe(iocbq_entry, iocbq_next,
6412 &phba->lpfc_iocb_list, list) {
6413 list_del(&iocbq_entry->list);
6414 kfree(iocbq_entry);
6415 phba->total_iocbq_bufs--;
6416 }
6417 spin_unlock_irq(&phba->hbalock);
6418
6419 return;
6420}
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433int
6434lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
6435{
6436 struct lpfc_iocbq *iocbq_entry = NULL;
6437 uint16_t iotag;
6438 int i;
6439
6440
6441 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
6442 for (i = 0; i < iocb_count; i++) {
6443 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
6444 if (iocbq_entry == NULL) {
6445 printk(KERN_ERR "%s: only allocated %d iocbs of "
6446 "expected %d count. Unloading driver.\n",
6447 __func__, i, LPFC_IOCB_LIST_CNT);
6448 goto out_free_iocbq;
6449 }
6450
6451 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
6452 if (iotag == 0) {
6453 kfree(iocbq_entry);
6454 printk(KERN_ERR "%s: failed to allocate IOTAG. "
6455 "Unloading driver.\n", __func__);
6456 goto out_free_iocbq;
6457 }
6458 iocbq_entry->sli4_lxritag = NO_XRI;
6459 iocbq_entry->sli4_xritag = NO_XRI;
6460
6461 spin_lock_irq(&phba->hbalock);
6462 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
6463 phba->total_iocbq_bufs++;
6464 spin_unlock_irq(&phba->hbalock);
6465 }
6466
6467 return 0;
6468
6469out_free_iocbq:
6470 lpfc_free_iocb_list(phba);
6471
6472 return -ENOMEM;
6473}
6474
6475
6476
6477
6478
6479
6480
6481
6482void
6483lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
6484{
6485 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
6486
6487 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
6488 list_del(&sglq_entry->list);
6489 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
6490 kfree(sglq_entry);
6491 }
6492}
6493
6494
6495
6496
6497
6498
6499
6500static void
6501lpfc_free_els_sgl_list(struct lpfc_hba *phba)
6502{
6503 LIST_HEAD(sglq_list);
6504
6505
6506 spin_lock_irq(&phba->hbalock);
6507 spin_lock(&phba->sli4_hba.sgl_list_lock);
6508 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list, &sglq_list);
6509 spin_unlock(&phba->sli4_hba.sgl_list_lock);
6510 spin_unlock_irq(&phba->hbalock);
6511
6512
6513 lpfc_free_sgl_list(phba, &sglq_list);
6514}
6515
6516
6517
6518
6519
6520
6521
6522static void
6523lpfc_free_nvmet_sgl_list(struct lpfc_hba *phba)
6524{
6525 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
6526 LIST_HEAD(sglq_list);
6527
6528
6529 spin_lock_irq(&phba->hbalock);
6530 spin_lock(&phba->sli4_hba.sgl_list_lock);
6531 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list, &sglq_list);
6532 spin_unlock(&phba->sli4_hba.sgl_list_lock);
6533 spin_unlock_irq(&phba->hbalock);
6534
6535
6536 list_for_each_entry_safe(sglq_entry, sglq_next, &sglq_list, list) {
6537 list_del(&sglq_entry->list);
6538 lpfc_nvmet_buf_free(phba, sglq_entry->virt, sglq_entry->phys);
6539 kfree(sglq_entry);
6540 }
6541
6542
6543
6544
6545
6546 phba->sli4_hba.nvmet_xri_cnt = 0;
6547}
6548
6549
6550
6551
6552
6553
6554
6555
6556static int
6557lpfc_init_active_sgl_array(struct lpfc_hba *phba)
6558{
6559 int size;
6560 size = sizeof(struct lpfc_sglq *);
6561 size *= phba->sli4_hba.max_cfg_param.max_xri;
6562
6563 phba->sli4_hba.lpfc_sglq_active_list =
6564 kzalloc(size, GFP_KERNEL);
6565 if (!phba->sli4_hba.lpfc_sglq_active_list)
6566 return -ENOMEM;
6567 return 0;
6568}
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578static void
6579lpfc_free_active_sgl(struct lpfc_hba *phba)
6580{
6581 kfree(phba->sli4_hba.lpfc_sglq_active_list);
6582}
6583
6584
6585
6586
6587
6588
6589
6590
6591
6592static void
6593lpfc_init_sgl_list(struct lpfc_hba *phba)
6594{
6595
6596 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_els_sgl_list);
6597 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
6598 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_sgl_list);
6599 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
6600
6601
6602 phba->sli4_hba.els_xri_cnt = 0;
6603
6604
6605 phba->sli4_hba.scsi_xri_cnt = 0;
6606
6607
6608 phba->sli4_hba.nvme_xri_cnt = 0;
6609}
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621
6622
6623
6624
6625int
6626lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
6627{
6628 int rc = 0;
6629 struct lpfc_rpi_hdr *rpi_hdr;
6630
6631 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
6632 if (!phba->sli4_hba.rpi_hdrs_in_use)
6633 return rc;
6634 if (phba->sli4_hba.extents_in_use)
6635 return -EIO;
6636
6637 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
6638 if (!rpi_hdr) {
6639 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
6640 "0391 Error during rpi post operation\n");
6641 lpfc_sli4_remove_rpis(phba);
6642 rc = -ENODEV;
6643 }
6644
6645 return rc;
6646}
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657
6658
6659
6660
6661struct lpfc_rpi_hdr *
6662lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
6663{
6664 uint16_t rpi_limit, curr_rpi_range;
6665 struct lpfc_dmabuf *dmabuf;
6666 struct lpfc_rpi_hdr *rpi_hdr;
6667
6668
6669
6670
6671
6672
6673 if (!phba->sli4_hba.rpi_hdrs_in_use)
6674 return NULL;
6675 if (phba->sli4_hba.extents_in_use)
6676 return NULL;
6677
6678
6679 rpi_limit = phba->sli4_hba.max_cfg_param.max_rpi;
6680
6681 spin_lock_irq(&phba->hbalock);
6682
6683
6684
6685
6686
6687 curr_rpi_range = phba->sli4_hba.next_rpi;
6688 spin_unlock_irq(&phba->hbalock);
6689
6690
6691 if (curr_rpi_range == rpi_limit)
6692 return NULL;
6693
6694
6695
6696
6697
6698 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
6699 if (!dmabuf)
6700 return NULL;
6701
6702 dmabuf->virt = dma_zalloc_coherent(&phba->pcidev->dev,
6703 LPFC_HDR_TEMPLATE_SIZE,
6704 &dmabuf->phys, GFP_KERNEL);
6705 if (!dmabuf->virt) {
6706 rpi_hdr = NULL;
6707 goto err_free_dmabuf;
6708 }
6709
6710 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
6711 rpi_hdr = NULL;
6712 goto err_free_coherent;
6713 }
6714
6715
6716 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
6717 if (!rpi_hdr)
6718 goto err_free_coherent;
6719
6720 rpi_hdr->dmabuf = dmabuf;
6721 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
6722 rpi_hdr->page_count = 1;
6723 spin_lock_irq(&phba->hbalock);
6724
6725
6726 rpi_hdr->start_rpi = curr_rpi_range;
6727 rpi_hdr->next_rpi = phba->sli4_hba.next_rpi + LPFC_RPI_HDR_COUNT;
6728 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
6729
6730 spin_unlock_irq(&phba->hbalock);
6731 return rpi_hdr;
6732
6733 err_free_coherent:
6734 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
6735 dmabuf->virt, dmabuf->phys);
6736 err_free_dmabuf:
6737 kfree(dmabuf);
6738 return NULL;
6739}
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749
6750void
6751lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
6752{
6753 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
6754
6755 if (!phba->sli4_hba.rpi_hdrs_in_use)
6756 goto exit;
6757
6758 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
6759 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
6760 list_del(&rpi_hdr->list);
6761 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
6762 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
6763 kfree(rpi_hdr->dmabuf);
6764 kfree(rpi_hdr);
6765 }
6766 exit:
6767
6768 phba->sli4_hba.next_rpi = 0;
6769}
6770
6771
6772
6773
6774
6775
6776
6777
6778
6779
6780
6781
6782
6783static struct lpfc_hba *
6784lpfc_hba_alloc(struct pci_dev *pdev)
6785{
6786 struct lpfc_hba *phba;
6787
6788
6789 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
6790 if (!phba) {
6791 dev_err(&pdev->dev, "failed to allocate hba struct\n");
6792 return NULL;
6793 }
6794
6795
6796 phba->pcidev = pdev;
6797
6798
6799 phba->brd_no = lpfc_get_instance();
6800 if (phba->brd_no < 0) {
6801 kfree(phba);
6802 return NULL;
6803 }
6804 phba->eratt_poll_interval = LPFC_ERATT_POLL_INTERVAL;
6805
6806 spin_lock_init(&phba->ct_ev_lock);
6807 INIT_LIST_HEAD(&phba->ct_ev_waiters);
6808
6809 return phba;
6810}
6811
6812
6813
6814
6815
6816
6817
6818
6819static void
6820lpfc_hba_free(struct lpfc_hba *phba)
6821{
6822
6823 idr_remove(&lpfc_hba_index, phba->brd_no);
6824
6825
6826 kfree(phba->sli.sli3_ring);
6827 phba->sli.sli3_ring = NULL;
6828
6829 kfree(phba);
6830 return;
6831}
6832
6833
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844static int
6845lpfc_create_shost(struct lpfc_hba *phba)
6846{
6847 struct lpfc_vport *vport;
6848 struct Scsi_Host *shost;
6849
6850
6851 phba->fc_edtov = FF_DEF_EDTOV;
6852 phba->fc_ratov = FF_DEF_RATOV;
6853 phba->fc_altov = FF_DEF_ALTOV;
6854 phba->fc_arbtov = FF_DEF_ARBTOV;
6855
6856 atomic_set(&phba->sdev_cnt, 0);
6857 atomic_set(&phba->fc4ScsiInputRequests, 0);
6858 atomic_set(&phba->fc4ScsiOutputRequests, 0);
6859 atomic_set(&phba->fc4ScsiControlRequests, 0);
6860 atomic_set(&phba->fc4ScsiIoCmpls, 0);
6861 atomic_set(&phba->fc4NvmeInputRequests, 0);
6862 atomic_set(&phba->fc4NvmeOutputRequests, 0);
6863 atomic_set(&phba->fc4NvmeControlRequests, 0);
6864 atomic_set(&phba->fc4NvmeIoCmpls, 0);
6865 atomic_set(&phba->fc4NvmeLsRequests, 0);
6866 atomic_set(&phba->fc4NvmeLsCmpls, 0);
6867 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
6868 if (!vport)
6869 return -ENODEV;
6870
6871 shost = lpfc_shost_from_vport(vport);
6872 phba->pport = vport;
6873
6874 if (phba->nvmet_support) {
6875
6876 if (phba->txrdy_payload_pool == NULL) {
6877 phba->txrdy_payload_pool = dma_pool_create(
6878 "txrdy_pool", &phba->pcidev->dev,
6879 TXRDY_PAYLOAD_LEN, 16, 0);
6880 if (phba->txrdy_payload_pool) {
6881 phba->targetport = NULL;
6882 phba->cfg_enable_fc4_type = LPFC_ENABLE_NVME;
6883 lpfc_printf_log(phba, KERN_INFO,
6884 LOG_INIT | LOG_NVME_DISC,
6885 "6076 NVME Target Found\n");
6886 }
6887 }
6888 }
6889
6890 lpfc_debugfs_initialize(vport);
6891
6892 pci_set_drvdata(phba->pcidev, shost);
6893
6894
6895
6896
6897
6898 vport->load_flag |= FC_ALLOW_FDMI;
6899 if (phba->cfg_enable_SmartSAN ||
6900 (phba->cfg_fdmi_on == LPFC_FDMI_SUPPORT)) {
6901
6902
6903 vport->fdmi_hba_mask = LPFC_FDMI2_HBA_ATTR;
6904 if (phba->cfg_enable_SmartSAN)
6905 vport->fdmi_port_mask = LPFC_FDMI2_SMART_ATTR;
6906 else
6907 vport->fdmi_port_mask = LPFC_FDMI2_PORT_ATTR;
6908 }
6909 return 0;
6910}
6911
6912
6913
6914
6915
6916
6917
6918
6919static void
6920lpfc_destroy_shost(struct lpfc_hba *phba)
6921{
6922 struct lpfc_vport *vport = phba->pport;
6923
6924
6925 destroy_port(vport);
6926
6927 return;
6928}
6929
6930
6931
6932
6933
6934
6935
6936
6937
6938static void
6939lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
6940{
6941 uint32_t old_mask;
6942 uint32_t old_guard;
6943
6944 int pagecnt = 10;
6945 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
6946 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6947 "1478 Registering BlockGuard with the "
6948 "SCSI layer\n");
6949
6950 old_mask = phba->cfg_prot_mask;
6951 old_guard = phba->cfg_prot_guard;
6952
6953
6954 phba->cfg_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
6955 SHOST_DIX_TYPE0_PROTECTION |
6956 SHOST_DIX_TYPE1_PROTECTION);
6957 phba->cfg_prot_guard &= (SHOST_DIX_GUARD_IP |
6958 SHOST_DIX_GUARD_CRC);
6959
6960
6961 if (phba->cfg_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
6962 phba->cfg_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
6963
6964 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
6965 if ((old_mask != phba->cfg_prot_mask) ||
6966 (old_guard != phba->cfg_prot_guard))
6967 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6968 "1475 Registering BlockGuard with the "
6969 "SCSI layer: mask %d guard %d\n",
6970 phba->cfg_prot_mask,
6971 phba->cfg_prot_guard);
6972
6973 scsi_host_set_prot(shost, phba->cfg_prot_mask);
6974 scsi_host_set_guard(shost, phba->cfg_prot_guard);
6975 } else
6976 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6977 "1479 Not Registering BlockGuard with the SCSI "
6978 "layer, Bad protection parameters: %d %d\n",
6979 old_mask, old_guard);
6980 }
6981
6982 if (!_dump_buf_data) {
6983 while (pagecnt) {
6984 spin_lock_init(&_dump_buf_lock);
6985 _dump_buf_data =
6986 (char *) __get_free_pages(GFP_KERNEL, pagecnt);
6987 if (_dump_buf_data) {
6988 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
6989 "9043 BLKGRD: allocated %d pages for "
6990 "_dump_buf_data at 0x%p\n",
6991 (1 << pagecnt), _dump_buf_data);
6992 _dump_buf_data_order = pagecnt;
6993 memset(_dump_buf_data, 0,
6994 ((1 << PAGE_SHIFT) << pagecnt));
6995 break;
6996 } else
6997 --pagecnt;
6998 }
6999 if (!_dump_buf_data_order)
7000 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7001 "9044 BLKGRD: ERROR unable to allocate "
7002 "memory for hexdump\n");
7003 } else
7004 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7005 "9045 BLKGRD: already allocated _dump_buf_data=0x%p"
7006 "\n", _dump_buf_data);
7007 if (!_dump_buf_dif) {
7008 while (pagecnt) {
7009 _dump_buf_dif =
7010 (char *) __get_free_pages(GFP_KERNEL, pagecnt);
7011 if (_dump_buf_dif) {
7012 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7013 "9046 BLKGRD: allocated %d pages for "
7014 "_dump_buf_dif at 0x%p\n",
7015 (1 << pagecnt), _dump_buf_dif);
7016 _dump_buf_dif_order = pagecnt;
7017 memset(_dump_buf_dif, 0,
7018 ((1 << PAGE_SHIFT) << pagecnt));
7019 break;
7020 } else
7021 --pagecnt;
7022 }
7023 if (!_dump_buf_dif_order)
7024 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7025 "9047 BLKGRD: ERROR unable to allocate "
7026 "memory for hexdump\n");
7027 } else
7028 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7029 "9048 BLKGRD: already allocated _dump_buf_dif=0x%p\n",
7030 _dump_buf_dif);
7031}
7032
7033
7034
7035
7036
7037
7038
7039
7040static void
7041lpfc_post_init_setup(struct lpfc_hba *phba)
7042{
7043 struct Scsi_Host *shost;
7044 struct lpfc_adapter_event_header adapter_event;
7045
7046
7047 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
7048
7049
7050
7051
7052
7053 shost = pci_get_drvdata(phba->pcidev);
7054 shost->can_queue = phba->cfg_hba_queue_depth - 10;
7055 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
7056 lpfc_setup_bg(phba, shost);
7057
7058 lpfc_host_attrib_init(shost);
7059
7060 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
7061 spin_lock_irq(shost->host_lock);
7062 lpfc_poll_start_timer(phba);
7063 spin_unlock_irq(shost->host_lock);
7064 }
7065
7066 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7067 "0428 Perform SCSI scan\n");
7068
7069 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
7070 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
7071 fc_host_post_vendor_event(shost, fc_get_event_number(),
7072 sizeof(adapter_event),
7073 (char *) &adapter_event,
7074 LPFC_NL_VENDOR_ID);
7075 return;
7076}
7077
7078
7079
7080
7081
7082
7083
7084
7085
7086
7087
7088
7089static int
7090lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
7091{
7092 struct pci_dev *pdev;
7093 unsigned long bar0map_len, bar2map_len;
7094 int i, hbq_count;
7095 void *ptr;
7096 int error = -ENODEV;
7097
7098
7099 if (!phba->pcidev)
7100 return error;
7101 else
7102 pdev = phba->pcidev;
7103
7104
7105 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0
7106 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(64)) != 0) {
7107 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0
7108 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(32)) != 0) {
7109 return error;
7110 }
7111 }
7112
7113
7114
7115
7116 phba->pci_bar0_map = pci_resource_start(pdev, 0);
7117 bar0map_len = pci_resource_len(pdev, 0);
7118
7119 phba->pci_bar2_map = pci_resource_start(pdev, 2);
7120 bar2map_len = pci_resource_len(pdev, 2);
7121
7122
7123 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
7124 if (!phba->slim_memmap_p) {
7125 dev_printk(KERN_ERR, &pdev->dev,
7126 "ioremap failed for SLIM memory.\n");
7127 goto out;
7128 }
7129
7130
7131 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
7132 if (!phba->ctrl_regs_memmap_p) {
7133 dev_printk(KERN_ERR, &pdev->dev,
7134 "ioremap failed for HBA control registers.\n");
7135 goto out_iounmap_slim;
7136 }
7137
7138
7139 phba->slim2p.virt = dma_zalloc_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7140 &phba->slim2p.phys, GFP_KERNEL);
7141 if (!phba->slim2p.virt)
7142 goto out_iounmap;
7143
7144 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
7145 phba->mbox_ext = (phba->slim2p.virt +
7146 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
7147 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
7148 phba->IOCBs = (phba->slim2p.virt +
7149 offsetof(struct lpfc_sli2_slim, IOCBs));
7150
7151 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
7152 lpfc_sli_hbq_size(),
7153 &phba->hbqslimp.phys,
7154 GFP_KERNEL);
7155 if (!phba->hbqslimp.virt)
7156 goto out_free_slim;
7157
7158 hbq_count = lpfc_sli_hbq_count();
7159 ptr = phba->hbqslimp.virt;
7160 for (i = 0; i < hbq_count; ++i) {
7161 phba->hbqs[i].hbq_virt = ptr;
7162 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
7163 ptr += (lpfc_hbq_defs[i]->entry_count *
7164 sizeof(struct lpfc_hbq_entry));
7165 }
7166 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
7167 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
7168
7169 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
7170
7171 phba->MBslimaddr = phba->slim_memmap_p;
7172 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
7173 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
7174 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
7175 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
7176
7177 return 0;
7178
7179out_free_slim:
7180 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7181 phba->slim2p.virt, phba->slim2p.phys);
7182out_iounmap:
7183 iounmap(phba->ctrl_regs_memmap_p);
7184out_iounmap_slim:
7185 iounmap(phba->slim_memmap_p);
7186out:
7187 return error;
7188}
7189
7190
7191
7192
7193
7194
7195
7196
7197static void
7198lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
7199{
7200 struct pci_dev *pdev;
7201
7202
7203 if (!phba->pcidev)
7204 return;
7205 else
7206 pdev = phba->pcidev;
7207
7208
7209 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
7210 phba->hbqslimp.virt, phba->hbqslimp.phys);
7211 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7212 phba->slim2p.virt, phba->slim2p.phys);
7213
7214
7215 iounmap(phba->ctrl_regs_memmap_p);
7216 iounmap(phba->slim_memmap_p);
7217
7218 return;
7219}
7220
7221
7222
7223
7224
7225
7226
7227
7228
7229
7230int
7231lpfc_sli4_post_status_check(struct lpfc_hba *phba)
7232{
7233 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
7234 struct lpfc_register reg_data;
7235 int i, port_error = 0;
7236 uint32_t if_type;
7237
7238 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
7239 memset(®_data, 0, sizeof(reg_data));
7240 if (!phba->sli4_hba.PSMPHRregaddr)
7241 return -ENODEV;
7242
7243
7244 for (i = 0; i < 3000; i++) {
7245 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
7246 &portsmphr_reg.word0) ||
7247 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
7248
7249 port_error = -ENODEV;
7250 break;
7251 }
7252 if (LPFC_POST_STAGE_PORT_READY ==
7253 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
7254 break;
7255 msleep(10);
7256 }
7257
7258
7259
7260
7261
7262 if (port_error) {
7263 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7264 "1408 Port Failed POST - portsmphr=0x%x, "
7265 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
7266 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
7267 portsmphr_reg.word0,
7268 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
7269 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
7270 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
7271 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
7272 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
7273 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
7274 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
7275 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
7276 } else {
7277 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7278 "2534 Device Info: SLIFamily=0x%x, "
7279 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
7280 "SLIHint_2=0x%x, FT=0x%x\n",
7281 bf_get(lpfc_sli_intf_sli_family,
7282 &phba->sli4_hba.sli_intf),
7283 bf_get(lpfc_sli_intf_slirev,
7284 &phba->sli4_hba.sli_intf),
7285 bf_get(lpfc_sli_intf_if_type,
7286 &phba->sli4_hba.sli_intf),
7287 bf_get(lpfc_sli_intf_sli_hint1,
7288 &phba->sli4_hba.sli_intf),
7289 bf_get(lpfc_sli_intf_sli_hint2,
7290 &phba->sli4_hba.sli_intf),
7291 bf_get(lpfc_sli_intf_func_type,
7292 &phba->sli4_hba.sli_intf));
7293
7294
7295
7296
7297
7298 if_type = bf_get(lpfc_sli_intf_if_type,
7299 &phba->sli4_hba.sli_intf);
7300 switch (if_type) {
7301 case LPFC_SLI_INTF_IF_TYPE_0:
7302 phba->sli4_hba.ue_mask_lo =
7303 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
7304 phba->sli4_hba.ue_mask_hi =
7305 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
7306 uerrlo_reg.word0 =
7307 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
7308 uerrhi_reg.word0 =
7309 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
7310 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
7311 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
7312 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7313 "1422 Unrecoverable Error "
7314 "Detected during POST "
7315 "uerr_lo_reg=0x%x, "
7316 "uerr_hi_reg=0x%x, "
7317 "ue_mask_lo_reg=0x%x, "
7318 "ue_mask_hi_reg=0x%x\n",
7319 uerrlo_reg.word0,
7320 uerrhi_reg.word0,
7321 phba->sli4_hba.ue_mask_lo,
7322 phba->sli4_hba.ue_mask_hi);
7323 port_error = -ENODEV;
7324 }
7325 break;
7326 case LPFC_SLI_INTF_IF_TYPE_2:
7327
7328 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
7329 ®_data.word0) ||
7330 (bf_get(lpfc_sliport_status_err, ®_data) &&
7331 !bf_get(lpfc_sliport_status_rn, ®_data))) {
7332 phba->work_status[0] =
7333 readl(phba->sli4_hba.u.if_type2.
7334 ERR1regaddr);
7335 phba->work_status[1] =
7336 readl(phba->sli4_hba.u.if_type2.
7337 ERR2regaddr);
7338 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7339 "2888 Unrecoverable port error "
7340 "following POST: port status reg "
7341 "0x%x, port_smphr reg 0x%x, "
7342 "error 1=0x%x, error 2=0x%x\n",
7343 reg_data.word0,
7344 portsmphr_reg.word0,
7345 phba->work_status[0],
7346 phba->work_status[1]);
7347 port_error = -ENODEV;
7348 }
7349 break;
7350 case LPFC_SLI_INTF_IF_TYPE_1:
7351 default:
7352 break;
7353 }
7354 }
7355 return port_error;
7356}
7357
7358
7359
7360
7361
7362
7363
7364
7365
7366static void
7367lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
7368{
7369 switch (if_type) {
7370 case LPFC_SLI_INTF_IF_TYPE_0:
7371 phba->sli4_hba.u.if_type0.UERRLOregaddr =
7372 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
7373 phba->sli4_hba.u.if_type0.UERRHIregaddr =
7374 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
7375 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
7376 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
7377 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
7378 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
7379 phba->sli4_hba.SLIINTFregaddr =
7380 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
7381 break;
7382 case LPFC_SLI_INTF_IF_TYPE_2:
7383 phba->sli4_hba.u.if_type2.EQDregaddr =
7384 phba->sli4_hba.conf_regs_memmap_p +
7385 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
7386 phba->sli4_hba.u.if_type2.ERR1regaddr =
7387 phba->sli4_hba.conf_regs_memmap_p +
7388 LPFC_CTL_PORT_ER1_OFFSET;
7389 phba->sli4_hba.u.if_type2.ERR2regaddr =
7390 phba->sli4_hba.conf_regs_memmap_p +
7391 LPFC_CTL_PORT_ER2_OFFSET;
7392 phba->sli4_hba.u.if_type2.CTRLregaddr =
7393 phba->sli4_hba.conf_regs_memmap_p +
7394 LPFC_CTL_PORT_CTL_OFFSET;
7395 phba->sli4_hba.u.if_type2.STATUSregaddr =
7396 phba->sli4_hba.conf_regs_memmap_p +
7397 LPFC_CTL_PORT_STA_OFFSET;
7398 phba->sli4_hba.SLIINTFregaddr =
7399 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
7400 phba->sli4_hba.PSMPHRregaddr =
7401 phba->sli4_hba.conf_regs_memmap_p +
7402 LPFC_CTL_PORT_SEM_OFFSET;
7403 phba->sli4_hba.RQDBregaddr =
7404 phba->sli4_hba.conf_regs_memmap_p +
7405 LPFC_ULP0_RQ_DOORBELL;
7406 phba->sli4_hba.WQDBregaddr =
7407 phba->sli4_hba.conf_regs_memmap_p +
7408 LPFC_ULP0_WQ_DOORBELL;
7409 phba->sli4_hba.EQCQDBregaddr =
7410 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
7411 phba->sli4_hba.MQDBregaddr =
7412 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
7413 phba->sli4_hba.BMBXregaddr =
7414 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
7415 break;
7416 case LPFC_SLI_INTF_IF_TYPE_1:
7417 default:
7418 dev_printk(KERN_ERR, &phba->pcidev->dev,
7419 "FATAL - unsupported SLI4 interface type - %d\n",
7420 if_type);
7421 break;
7422 }
7423}
7424
7425
7426
7427
7428
7429
7430
7431
7432static void
7433lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba)
7434{
7435 phba->sli4_hba.PSMPHRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
7436 LPFC_SLIPORT_IF0_SMPHR;
7437 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
7438 LPFC_HST_ISR0;
7439 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
7440 LPFC_HST_IMR0;
7441 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
7442 LPFC_HST_ISCR0;
7443}
7444
7445
7446
7447
7448
7449
7450
7451
7452
7453
7454
7455static int
7456lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
7457{
7458 if (vf > LPFC_VIR_FUNC_MAX)
7459 return -ENODEV;
7460
7461 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
7462 vf * LPFC_VFR_PAGE_SIZE +
7463 LPFC_ULP0_RQ_DOORBELL);
7464 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
7465 vf * LPFC_VFR_PAGE_SIZE +
7466 LPFC_ULP0_WQ_DOORBELL);
7467 phba->sli4_hba.EQCQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
7468 vf * LPFC_VFR_PAGE_SIZE + LPFC_EQCQ_DOORBELL);
7469 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
7470 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
7471 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
7472 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
7473 return 0;
7474}
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484
7485
7486
7487
7488
7489
7490
7491static int
7492lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
7493{
7494 uint32_t bmbx_size;
7495 struct lpfc_dmabuf *dmabuf;
7496 struct dma_address *dma_address;
7497 uint32_t pa_addr;
7498 uint64_t phys_addr;
7499
7500 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
7501 if (!dmabuf)
7502 return -ENOMEM;
7503
7504
7505
7506
7507
7508 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
7509 dmabuf->virt = dma_zalloc_coherent(&phba->pcidev->dev, bmbx_size,
7510 &dmabuf->phys, GFP_KERNEL);
7511 if (!dmabuf->virt) {
7512 kfree(dmabuf);
7513 return -ENOMEM;
7514 }
7515
7516
7517
7518
7519
7520
7521
7522
7523 phba->sli4_hba.bmbx.dmabuf = dmabuf;
7524 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
7525
7526 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
7527 LPFC_ALIGN_16_BYTE);
7528 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
7529 LPFC_ALIGN_16_BYTE);
7530
7531
7532
7533
7534
7535
7536
7537
7538
7539 dma_address = &phba->sli4_hba.bmbx.dma_address;
7540 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
7541 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
7542 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
7543 LPFC_BMBX_BIT1_ADDR_HI);
7544
7545 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
7546 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
7547 LPFC_BMBX_BIT1_ADDR_LO);
7548 return 0;
7549}
7550
7551
7552
7553
7554
7555
7556
7557
7558
7559
7560
7561
7562static void
7563lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
7564{
7565 dma_free_coherent(&phba->pcidev->dev,
7566 phba->sli4_hba.bmbx.bmbx_size,
7567 phba->sli4_hba.bmbx.dmabuf->virt,
7568 phba->sli4_hba.bmbx.dmabuf->phys);
7569
7570 kfree(phba->sli4_hba.bmbx.dmabuf);
7571 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
7572}
7573
7574
7575
7576
7577
7578
7579
7580
7581
7582
7583
7584
7585
7586
7587
7588int
7589lpfc_sli4_read_config(struct lpfc_hba *phba)
7590{
7591 LPFC_MBOXQ_t *pmb;
7592 struct lpfc_mbx_read_config *rd_config;
7593 union lpfc_sli4_cfg_shdr *shdr;
7594 uint32_t shdr_status, shdr_add_status;
7595 struct lpfc_mbx_get_func_cfg *get_func_cfg;
7596 struct lpfc_rsrc_desc_fcfcoe *desc;
7597 char *pdesc_0;
7598 uint16_t forced_link_speed;
7599 uint32_t if_type;
7600 int length, i, rc = 0, rc2;
7601
7602 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
7603 if (!pmb) {
7604 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
7605 "2011 Unable to allocate memory for issuing "
7606 "SLI_CONFIG_SPECIAL mailbox command\n");
7607 return -ENOMEM;
7608 }
7609
7610 lpfc_read_config(phba, pmb);
7611
7612 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
7613 if (rc != MBX_SUCCESS) {
7614 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
7615 "2012 Mailbox failed , mbxCmd x%x "
7616 "READ_CONFIG, mbxStatus x%x\n",
7617 bf_get(lpfc_mqe_command, &pmb->u.mqe),
7618 bf_get(lpfc_mqe_status, &pmb->u.mqe));
7619 rc = -EIO;
7620 } else {
7621 rd_config = &pmb->u.mqe.un.rd_config;
7622 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
7623 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
7624 phba->sli4_hba.lnk_info.lnk_tp =
7625 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
7626 phba->sli4_hba.lnk_info.lnk_no =
7627 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
7628 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
7629 "3081 lnk_type:%d, lnk_numb:%d\n",
7630 phba->sli4_hba.lnk_info.lnk_tp,
7631 phba->sli4_hba.lnk_info.lnk_no);
7632 } else
7633 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
7634 "3082 Mailbox (x%x) returned ldv:x0\n",
7635 bf_get(lpfc_mqe_command, &pmb->u.mqe));
7636 if (bf_get(lpfc_mbx_rd_conf_bbscn_def, rd_config)) {
7637 phba->bbcredit_support = 1;
7638 phba->sli4_hba.bbscn_params.word0 = rd_config->word8;
7639 }
7640
7641 phba->sli4_hba.extents_in_use =
7642 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
7643 phba->sli4_hba.max_cfg_param.max_xri =
7644 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
7645 phba->sli4_hba.max_cfg_param.xri_base =
7646 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
7647 phba->sli4_hba.max_cfg_param.max_vpi =
7648 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
7649 phba->sli4_hba.max_cfg_param.vpi_base =
7650 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
7651 phba->sli4_hba.max_cfg_param.max_rpi =
7652 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
7653 phba->sli4_hba.max_cfg_param.rpi_base =
7654 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
7655 phba->sli4_hba.max_cfg_param.max_vfi =
7656 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
7657 phba->sli4_hba.max_cfg_param.vfi_base =
7658 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
7659 phba->sli4_hba.max_cfg_param.max_fcfi =
7660 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
7661 phba->sli4_hba.max_cfg_param.max_eq =
7662 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
7663 phba->sli4_hba.max_cfg_param.max_rq =
7664 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
7665 phba->sli4_hba.max_cfg_param.max_wq =
7666 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
7667 phba->sli4_hba.max_cfg_param.max_cq =
7668 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
7669 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
7670 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
7671 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
7672 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
7673 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
7674 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
7675 phba->max_vports = phba->max_vpi;
7676 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
7677 "2003 cfg params Extents? %d "
7678 "XRI(B:%d M:%d), "
7679 "VPI(B:%d M:%d) "
7680 "VFI(B:%d M:%d) "
7681 "RPI(B:%d M:%d) "
7682 "FCFI:%d EQ:%d CQ:%d WQ:%d RQ:%d\n",
7683 phba->sli4_hba.extents_in_use,
7684 phba->sli4_hba.max_cfg_param.xri_base,
7685 phba->sli4_hba.max_cfg_param.max_xri,
7686 phba->sli4_hba.max_cfg_param.vpi_base,
7687 phba->sli4_hba.max_cfg_param.max_vpi,
7688 phba->sli4_hba.max_cfg_param.vfi_base,
7689 phba->sli4_hba.max_cfg_param.max_vfi,
7690 phba->sli4_hba.max_cfg_param.rpi_base,
7691 phba->sli4_hba.max_cfg_param.max_rpi,
7692 phba->sli4_hba.max_cfg_param.max_fcfi,
7693 phba->sli4_hba.max_cfg_param.max_eq,
7694 phba->sli4_hba.max_cfg_param.max_cq,
7695 phba->sli4_hba.max_cfg_param.max_wq,
7696 phba->sli4_hba.max_cfg_param.max_rq);
7697
7698 }
7699
7700 if (rc)
7701 goto read_cfg_out;
7702
7703
7704 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
7705 if (if_type == LPFC_SLI_INTF_IF_TYPE_2) {
7706 forced_link_speed =
7707 bf_get(lpfc_mbx_rd_conf_link_speed, rd_config);
7708 if (forced_link_speed) {
7709 phba->hba_flag |= HBA_FORCED_LINK_SPEED;
7710
7711 switch (forced_link_speed) {
7712 case LINK_SPEED_1G:
7713 phba->cfg_link_speed =
7714 LPFC_USER_LINK_SPEED_1G;
7715 break;
7716 case LINK_SPEED_2G:
7717 phba->cfg_link_speed =
7718 LPFC_USER_LINK_SPEED_2G;
7719 break;
7720 case LINK_SPEED_4G:
7721 phba->cfg_link_speed =
7722 LPFC_USER_LINK_SPEED_4G;
7723 break;
7724 case LINK_SPEED_8G:
7725 phba->cfg_link_speed =
7726 LPFC_USER_LINK_SPEED_8G;
7727 break;
7728 case LINK_SPEED_10G:
7729 phba->cfg_link_speed =
7730 LPFC_USER_LINK_SPEED_10G;
7731 break;
7732 case LINK_SPEED_16G:
7733 phba->cfg_link_speed =
7734 LPFC_USER_LINK_SPEED_16G;
7735 break;
7736 case LINK_SPEED_32G:
7737 phba->cfg_link_speed =
7738 LPFC_USER_LINK_SPEED_32G;
7739 break;
7740 case 0xffff:
7741 phba->cfg_link_speed =
7742 LPFC_USER_LINK_SPEED_AUTO;
7743 break;
7744 default:
7745 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
7746 "0047 Unrecognized link "
7747 "speed : %d\n",
7748 forced_link_speed);
7749 phba->cfg_link_speed =
7750 LPFC_USER_LINK_SPEED_AUTO;
7751 }
7752 }
7753 }
7754
7755
7756 length = phba->sli4_hba.max_cfg_param.max_xri -
7757 lpfc_sli4_get_els_iocb_cnt(phba);
7758 if (phba->cfg_hba_queue_depth > length) {
7759 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
7760 "3361 HBA queue depth changed from %d to %d\n",
7761 phba->cfg_hba_queue_depth, length);
7762 phba->cfg_hba_queue_depth = length;
7763 }
7764
7765 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
7766 LPFC_SLI_INTF_IF_TYPE_2)
7767 goto read_cfg_out;
7768
7769
7770 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
7771 sizeof(struct lpfc_sli4_cfg_mhdr));
7772 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
7773 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
7774 length, LPFC_SLI4_MBX_EMBED);
7775
7776 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
7777 shdr = (union lpfc_sli4_cfg_shdr *)
7778 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
7779 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
7780 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
7781 if (rc2 || shdr_status || shdr_add_status) {
7782 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
7783 "3026 Mailbox failed , mbxCmd x%x "
7784 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
7785 bf_get(lpfc_mqe_command, &pmb->u.mqe),
7786 bf_get(lpfc_mqe_status, &pmb->u.mqe));
7787 goto read_cfg_out;
7788 }
7789
7790
7791 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
7792
7793 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
7794 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
7795 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
7796 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
7797 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
7798 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
7799 goto read_cfg_out;
7800
7801 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
7802 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
7803 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
7804 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
7805 phba->sli4_hba.iov.pf_number =
7806 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
7807 phba->sli4_hba.iov.vf_number =
7808 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
7809 break;
7810 }
7811 }
7812
7813 if (i < LPFC_RSRC_DESC_MAX_NUM)
7814 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
7815 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
7816 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
7817 phba->sli4_hba.iov.vf_number);
7818 else
7819 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
7820 "3028 GET_FUNCTION_CONFIG: failed to find "
7821 "Resrouce Descriptor:x%x\n",
7822 LPFC_RSRC_DESC_TYPE_FCFCOE);
7823
7824read_cfg_out:
7825 mempool_free(pmb, phba->mbox_mem_pool);
7826 return rc;
7827}
7828
7829
7830
7831
7832
7833
7834
7835
7836
7837
7838
7839
7840
7841
7842static int
7843lpfc_setup_endian_order(struct lpfc_hba *phba)
7844{
7845 LPFC_MBOXQ_t *mboxq;
7846 uint32_t if_type, rc = 0;
7847 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
7848 HOST_ENDIAN_HIGH_WORD1};
7849
7850 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
7851 switch (if_type) {
7852 case LPFC_SLI_INTF_IF_TYPE_0:
7853 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
7854 GFP_KERNEL);
7855 if (!mboxq) {
7856 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7857 "0492 Unable to allocate memory for "
7858 "issuing SLI_CONFIG_SPECIAL mailbox "
7859 "command\n");
7860 return -ENOMEM;
7861 }
7862
7863
7864
7865
7866
7867 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
7868 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
7869 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
7870 if (rc != MBX_SUCCESS) {
7871 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7872 "0493 SLI_CONFIG_SPECIAL mailbox "
7873 "failed with status x%x\n",
7874 rc);
7875 rc = -EIO;
7876 }
7877 mempool_free(mboxq, phba->mbox_mem_pool);
7878 break;
7879 case LPFC_SLI_INTF_IF_TYPE_2:
7880 case LPFC_SLI_INTF_IF_TYPE_1:
7881 default:
7882 break;
7883 }
7884 return rc;
7885}
7886
7887
7888
7889
7890
7891
7892
7893
7894
7895
7896
7897
7898
7899
7900static int
7901lpfc_sli4_queue_verify(struct lpfc_hba *phba)
7902{
7903 int io_channel;
7904 int fof_vectors = phba->cfg_fof ? 1 : 0;
7905
7906
7907
7908
7909
7910
7911
7912 io_channel = phba->io_channel_irqs;
7913
7914 if (phba->sli4_hba.num_online_cpu < io_channel) {
7915 lpfc_printf_log(phba,
7916 KERN_ERR, LOG_INIT,
7917 "3188 Reducing IO channels to match number of "
7918 "online CPUs: from %d to %d\n",
7919 io_channel, phba->sli4_hba.num_online_cpu);
7920 io_channel = phba->sli4_hba.num_online_cpu;
7921 }
7922
7923 if (io_channel + fof_vectors > phba->sli4_hba.max_cfg_param.max_eq) {
7924 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7925 "2575 Reducing IO channels to match number of "
7926 "available EQs: from %d to %d\n",
7927 io_channel,
7928 phba->sli4_hba.max_cfg_param.max_eq);
7929 io_channel = phba->sli4_hba.max_cfg_param.max_eq - fof_vectors;
7930 }
7931
7932
7933 if (io_channel != phba->io_channel_irqs)
7934 phba->io_channel_irqs = io_channel;
7935 if (phba->cfg_fcp_io_channel > io_channel)
7936 phba->cfg_fcp_io_channel = io_channel;
7937 if (phba->cfg_nvme_io_channel > io_channel)
7938 phba->cfg_nvme_io_channel = io_channel;
7939 if (phba->cfg_nvme_io_channel < phba->cfg_nvmet_mrq)
7940 phba->cfg_nvmet_mrq = phba->cfg_nvme_io_channel;
7941
7942 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7943 "2574 IO channels: irqs %d fcp %d nvme %d MRQ: %d\n",
7944 phba->io_channel_irqs, phba->cfg_fcp_io_channel,
7945 phba->cfg_nvme_io_channel, phba->cfg_nvmet_mrq);
7946
7947
7948 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
7949 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
7950
7951
7952 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
7953 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
7954 return 0;
7955}
7956
7957static int
7958lpfc_alloc_nvme_wq_cq(struct lpfc_hba *phba, int wqidx)
7959{
7960 struct lpfc_queue *qdesc;
7961 int cnt;
7962
7963 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
7964 phba->sli4_hba.cq_ecount);
7965 if (!qdesc) {
7966 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7967 "0508 Failed allocate fast-path NVME CQ (%d)\n",
7968 wqidx);
7969 return 1;
7970 }
7971 phba->sli4_hba.nvme_cq[wqidx] = qdesc;
7972
7973 cnt = LPFC_NVME_WQSIZE;
7974 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_WQE128_SIZE, cnt);
7975 if (!qdesc) {
7976 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7977 "0509 Failed allocate fast-path NVME WQ (%d)\n",
7978 wqidx);
7979 return 1;
7980 }
7981 phba->sli4_hba.nvme_wq[wqidx] = qdesc;
7982 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
7983 return 0;
7984}
7985
7986static int
7987lpfc_alloc_fcp_wq_cq(struct lpfc_hba *phba, int wqidx)
7988{
7989 struct lpfc_queue *qdesc;
7990 uint32_t wqesize;
7991
7992
7993 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
7994 phba->sli4_hba.cq_ecount);
7995 if (!qdesc) {
7996 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7997 "0499 Failed allocate fast-path FCP CQ (%d)\n", wqidx);
7998 return 1;
7999 }
8000 phba->sli4_hba.fcp_cq[wqidx] = qdesc;
8001
8002
8003 wqesize = (phba->fcp_embed_io) ?
8004 LPFC_WQE128_SIZE : phba->sli4_hba.wq_esize;
8005 qdesc = lpfc_sli4_queue_alloc(phba, wqesize, phba->sli4_hba.wq_ecount);
8006 if (!qdesc) {
8007 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8008 "0503 Failed allocate fast-path FCP WQ (%d)\n",
8009 wqidx);
8010 return 1;
8011 }
8012 phba->sli4_hba.fcp_wq[wqidx] = qdesc;
8013 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8014 return 0;
8015}
8016
8017
8018
8019
8020
8021
8022
8023
8024
8025
8026
8027
8028
8029
8030
8031int
8032lpfc_sli4_queue_create(struct lpfc_hba *phba)
8033{
8034 struct lpfc_queue *qdesc;
8035 int idx, io_channel;
8036
8037
8038
8039
8040
8041 io_channel = phba->io_channel_irqs;
8042 if (!io_channel)
8043 return -ERANGE;
8044
8045 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
8046 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
8047 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
8048 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
8049 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
8050 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
8051 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8052 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
8053 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8054 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
8055
8056 phba->sli4_hba.hba_eq = kcalloc(io_channel,
8057 sizeof(struct lpfc_queue *),
8058 GFP_KERNEL);
8059 if (!phba->sli4_hba.hba_eq) {
8060 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8061 "2576 Failed allocate memory for "
8062 "fast-path EQ record array\n");
8063 goto out_error;
8064 }
8065
8066 if (phba->cfg_fcp_io_channel) {
8067 phba->sli4_hba.fcp_cq = kcalloc(phba->cfg_fcp_io_channel,
8068 sizeof(struct lpfc_queue *),
8069 GFP_KERNEL);
8070 if (!phba->sli4_hba.fcp_cq) {
8071 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8072 "2577 Failed allocate memory for "
8073 "fast-path CQ record array\n");
8074 goto out_error;
8075 }
8076 phba->sli4_hba.fcp_wq = kcalloc(phba->cfg_fcp_io_channel,
8077 sizeof(struct lpfc_queue *),
8078 GFP_KERNEL);
8079 if (!phba->sli4_hba.fcp_wq) {
8080 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8081 "2578 Failed allocate memory for "
8082 "fast-path FCP WQ record array\n");
8083 goto out_error;
8084 }
8085
8086
8087
8088
8089
8090 phba->sli4_hba.fcp_cq_map = kcalloc(phba->cfg_fcp_io_channel,
8091 sizeof(uint16_t),
8092 GFP_KERNEL);
8093 if (!phba->sli4_hba.fcp_cq_map) {
8094 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8095 "2545 Failed allocate memory for "
8096 "fast-path CQ map\n");
8097 goto out_error;
8098 }
8099 }
8100
8101 if (phba->cfg_nvme_io_channel) {
8102 phba->sli4_hba.nvme_cq = kcalloc(phba->cfg_nvme_io_channel,
8103 sizeof(struct lpfc_queue *),
8104 GFP_KERNEL);
8105 if (!phba->sli4_hba.nvme_cq) {
8106 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8107 "6077 Failed allocate memory for "
8108 "fast-path CQ record array\n");
8109 goto out_error;
8110 }
8111
8112 phba->sli4_hba.nvme_wq = kcalloc(phba->cfg_nvme_io_channel,
8113 sizeof(struct lpfc_queue *),
8114 GFP_KERNEL);
8115 if (!phba->sli4_hba.nvme_wq) {
8116 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8117 "2581 Failed allocate memory for "
8118 "fast-path NVME WQ record array\n");
8119 goto out_error;
8120 }
8121
8122
8123
8124
8125
8126
8127 phba->sli4_hba.nvme_cq_map = kcalloc(phba->cfg_nvme_io_channel,
8128 sizeof(uint16_t),
8129 GFP_KERNEL);
8130 if (!phba->sli4_hba.nvme_cq_map) {
8131 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8132 "6078 Failed allocate memory for "
8133 "fast-path CQ map\n");
8134 goto out_error;
8135 }
8136
8137 if (phba->nvmet_support) {
8138 phba->sli4_hba.nvmet_cqset = kcalloc(
8139 phba->cfg_nvmet_mrq,
8140 sizeof(struct lpfc_queue *),
8141 GFP_KERNEL);
8142 if (!phba->sli4_hba.nvmet_cqset) {
8143 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8144 "3121 Fail allocate memory for "
8145 "fast-path CQ set array\n");
8146 goto out_error;
8147 }
8148 phba->sli4_hba.nvmet_mrq_hdr = kcalloc(
8149 phba->cfg_nvmet_mrq,
8150 sizeof(struct lpfc_queue *),
8151 GFP_KERNEL);
8152 if (!phba->sli4_hba.nvmet_mrq_hdr) {
8153 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8154 "3122 Fail allocate memory for "
8155 "fast-path RQ set hdr array\n");
8156 goto out_error;
8157 }
8158 phba->sli4_hba.nvmet_mrq_data = kcalloc(
8159 phba->cfg_nvmet_mrq,
8160 sizeof(struct lpfc_queue *),
8161 GFP_KERNEL);
8162 if (!phba->sli4_hba.nvmet_mrq_data) {
8163 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8164 "3124 Fail allocate memory for "
8165 "fast-path RQ set data array\n");
8166 goto out_error;
8167 }
8168 }
8169 }
8170
8171 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
8172
8173
8174 for (idx = 0; idx < io_channel; idx++) {
8175
8176 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.eq_esize,
8177 phba->sli4_hba.eq_ecount);
8178 if (!qdesc) {
8179 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8180 "0497 Failed allocate EQ (%d)\n", idx);
8181 goto out_error;
8182 }
8183 phba->sli4_hba.hba_eq[idx] = qdesc;
8184 }
8185
8186
8187
8188 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++)
8189 if (lpfc_alloc_fcp_wq_cq(phba, idx))
8190 goto out_error;
8191
8192 for (idx = 0; idx < phba->cfg_nvme_io_channel; idx++)
8193 if (lpfc_alloc_nvme_wq_cq(phba, idx))
8194 goto out_error;
8195
8196 if (phba->nvmet_support) {
8197 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
8198 qdesc = lpfc_sli4_queue_alloc(phba,
8199 phba->sli4_hba.cq_esize,
8200 phba->sli4_hba.cq_ecount);
8201 if (!qdesc) {
8202 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8203 "3142 Failed allocate NVME "
8204 "CQ Set (%d)\n", idx);
8205 goto out_error;
8206 }
8207 phba->sli4_hba.nvmet_cqset[idx] = qdesc;
8208 }
8209 }
8210
8211
8212
8213
8214
8215
8216 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
8217 phba->sli4_hba.cq_ecount);
8218 if (!qdesc) {
8219 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8220 "0500 Failed allocate slow-path mailbox CQ\n");
8221 goto out_error;
8222 }
8223 phba->sli4_hba.mbx_cq = qdesc;
8224
8225
8226 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
8227 phba->sli4_hba.cq_ecount);
8228 if (!qdesc) {
8229 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8230 "0501 Failed allocate slow-path ELS CQ\n");
8231 goto out_error;
8232 }
8233 phba->sli4_hba.els_cq = qdesc;
8234
8235
8236
8237
8238
8239
8240
8241
8242 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.mq_esize,
8243 phba->sli4_hba.mq_ecount);
8244 if (!qdesc) {
8245 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8246 "0505 Failed allocate slow-path MQ\n");
8247 goto out_error;
8248 }
8249 phba->sli4_hba.mbx_wq = qdesc;
8250
8251
8252
8253
8254
8255
8256 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.wq_esize,
8257 phba->sli4_hba.wq_ecount);
8258 if (!qdesc) {
8259 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8260 "0504 Failed allocate slow-path ELS WQ\n");
8261 goto out_error;
8262 }
8263 phba->sli4_hba.els_wq = qdesc;
8264 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8265
8266 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
8267
8268 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
8269 phba->sli4_hba.cq_ecount);
8270 if (!qdesc) {
8271 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8272 "6079 Failed allocate NVME LS CQ\n");
8273 goto out_error;
8274 }
8275 phba->sli4_hba.nvmels_cq = qdesc;
8276
8277
8278 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.wq_esize,
8279 phba->sli4_hba.wq_ecount);
8280 if (!qdesc) {
8281 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8282 "6080 Failed allocate NVME LS WQ\n");
8283 goto out_error;
8284 }
8285 phba->sli4_hba.nvmels_wq = qdesc;
8286 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8287 }
8288
8289
8290
8291
8292
8293
8294 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.rq_esize,
8295 phba->sli4_hba.rq_ecount);
8296 if (!qdesc) {
8297 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8298 "0506 Failed allocate receive HRQ\n");
8299 goto out_error;
8300 }
8301 phba->sli4_hba.hdr_rq = qdesc;
8302
8303
8304 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.rq_esize,
8305 phba->sli4_hba.rq_ecount);
8306 if (!qdesc) {
8307 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8308 "0507 Failed allocate receive DRQ\n");
8309 goto out_error;
8310 }
8311 phba->sli4_hba.dat_rq = qdesc;
8312
8313 if (phba->nvmet_support) {
8314 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
8315
8316 qdesc = lpfc_sli4_queue_alloc(phba,
8317 phba->sli4_hba.rq_esize,
8318 LPFC_NVMET_RQE_DEF_COUNT);
8319 if (!qdesc) {
8320 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8321 "3146 Failed allocate "
8322 "receive HRQ\n");
8323 goto out_error;
8324 }
8325 phba->sli4_hba.nvmet_mrq_hdr[idx] = qdesc;
8326
8327
8328 qdesc->rqbp = kzalloc(sizeof(struct lpfc_rqb),
8329 GFP_KERNEL);
8330 if (qdesc->rqbp == NULL) {
8331 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8332 "6131 Failed allocate "
8333 "Header RQBP\n");
8334 goto out_error;
8335 }
8336
8337
8338 INIT_LIST_HEAD(&qdesc->rqbp->rqb_buffer_list);
8339
8340
8341 qdesc = lpfc_sli4_queue_alloc(phba,
8342 phba->sli4_hba.rq_esize,
8343 LPFC_NVMET_RQE_DEF_COUNT);
8344 if (!qdesc) {
8345 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8346 "3156 Failed allocate "
8347 "receive DRQ\n");
8348 goto out_error;
8349 }
8350 phba->sli4_hba.nvmet_mrq_data[idx] = qdesc;
8351 }
8352 }
8353
8354
8355 if (phba->cfg_fof)
8356 lpfc_fof_queue_create(phba);
8357 return 0;
8358
8359out_error:
8360 lpfc_sli4_queue_destroy(phba);
8361 return -ENOMEM;
8362}
8363
8364static inline void
8365__lpfc_sli4_release_queue(struct lpfc_queue **qp)
8366{
8367 if (*qp != NULL) {
8368 lpfc_sli4_queue_free(*qp);
8369 *qp = NULL;
8370 }
8371}
8372
8373static inline void
8374lpfc_sli4_release_queues(struct lpfc_queue ***qs, int max)
8375{
8376 int idx;
8377
8378 if (*qs == NULL)
8379 return;
8380
8381 for (idx = 0; idx < max; idx++)
8382 __lpfc_sli4_release_queue(&(*qs)[idx]);
8383
8384 kfree(*qs);
8385 *qs = NULL;
8386}
8387
8388static inline void
8389lpfc_sli4_release_queue_map(uint16_t **qmap)
8390{
8391 if (*qmap != NULL) {
8392 kfree(*qmap);
8393 *qmap = NULL;
8394 }
8395}
8396
8397
8398
8399
8400
8401
8402
8403
8404
8405
8406
8407
8408
8409void
8410lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
8411{
8412 if (phba->cfg_fof)
8413 lpfc_fof_queue_destroy(phba);
8414
8415
8416 lpfc_sli4_release_queues(&phba->sli4_hba.hba_eq, phba->io_channel_irqs);
8417
8418
8419 lpfc_sli4_release_queues(&phba->sli4_hba.fcp_cq,
8420 phba->cfg_fcp_io_channel);
8421
8422
8423 lpfc_sli4_release_queues(&phba->sli4_hba.fcp_wq,
8424 phba->cfg_fcp_io_channel);
8425
8426
8427 lpfc_sli4_release_queue_map(&phba->sli4_hba.fcp_cq_map);
8428
8429
8430 lpfc_sli4_release_queues(&phba->sli4_hba.nvme_cq,
8431 phba->cfg_nvme_io_channel);
8432
8433
8434 lpfc_sli4_release_queues(&phba->sli4_hba.nvme_wq,
8435 phba->cfg_nvme_io_channel);
8436
8437
8438 lpfc_sli4_release_queue_map(&phba->sli4_hba.nvme_cq_map);
8439
8440 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
8441 phba->cfg_nvmet_mrq);
8442
8443 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
8444 phba->cfg_nvmet_mrq);
8445 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
8446 phba->cfg_nvmet_mrq);
8447
8448
8449 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_wq);
8450
8451
8452 __lpfc_sli4_release_queue(&phba->sli4_hba.els_wq);
8453
8454
8455 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_wq);
8456
8457
8458 __lpfc_sli4_release_queue(&phba->sli4_hba.hdr_rq);
8459 __lpfc_sli4_release_queue(&phba->sli4_hba.dat_rq);
8460
8461
8462 __lpfc_sli4_release_queue(&phba->sli4_hba.els_cq);
8463
8464
8465 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_cq);
8466
8467
8468 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_cq);
8469
8470
8471 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
8472}
8473
8474int
8475lpfc_free_rq_buffer(struct lpfc_hba *phba, struct lpfc_queue *rq)
8476{
8477 struct lpfc_rqb *rqbp;
8478 struct lpfc_dmabuf *h_buf;
8479 struct rqb_dmabuf *rqb_buffer;
8480
8481 rqbp = rq->rqbp;
8482 while (!list_empty(&rqbp->rqb_buffer_list)) {
8483 list_remove_head(&rqbp->rqb_buffer_list, h_buf,
8484 struct lpfc_dmabuf, list);
8485
8486 rqb_buffer = container_of(h_buf, struct rqb_dmabuf, hbuf);
8487 (rqbp->rqb_free_buffer)(phba, rqb_buffer);
8488 rqbp->buffer_count--;
8489 }
8490 return 1;
8491}
8492
8493static int
8494lpfc_create_wq_cq(struct lpfc_hba *phba, struct lpfc_queue *eq,
8495 struct lpfc_queue *cq, struct lpfc_queue *wq, uint16_t *cq_map,
8496 int qidx, uint32_t qtype)
8497{
8498 struct lpfc_sli_ring *pring;
8499 int rc;
8500
8501 if (!eq || !cq || !wq) {
8502 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8503 "6085 Fast-path %s (%d) not allocated\n",
8504 ((eq) ? ((cq) ? "WQ" : "CQ") : "EQ"), qidx);
8505 return -ENOMEM;
8506 }
8507
8508
8509 rc = lpfc_cq_create(phba, cq, eq,
8510 (qtype == LPFC_MBOX) ? LPFC_MCQ : LPFC_WCQ, qtype);
8511 if (rc) {
8512 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8513 "6086 Failed setup of CQ (%d), rc = 0x%x\n",
8514 qidx, (uint32_t)rc);
8515 return rc;
8516 }
8517
8518 if (qtype != LPFC_MBOX) {
8519
8520 if (cq_map)
8521 *cq_map = cq->queue_id;
8522
8523 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8524 "6087 CQ setup: cq[%d]-id=%d, parent eq[%d]-id=%d\n",
8525 qidx, cq->queue_id, qidx, eq->queue_id);
8526
8527
8528 rc = lpfc_wq_create(phba, wq, cq, qtype);
8529 if (rc) {
8530 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8531 "6123 Fail setup fastpath WQ (%d), rc = 0x%x\n",
8532 qidx, (uint32_t)rc);
8533
8534 return rc;
8535 }
8536
8537
8538 pring = wq->pring;
8539 pring->sli.sli4.wqp = (void *)wq;
8540 cq->pring = pring;
8541
8542 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8543 "2593 WQ setup: wq[%d]-id=%d assoc=%d, cq[%d]-id=%d\n",
8544 qidx, wq->queue_id, wq->assoc_qid, qidx, cq->queue_id);
8545 } else {
8546 rc = lpfc_mq_create(phba, wq, cq, LPFC_MBOX);
8547 if (rc) {
8548 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8549 "0539 Failed setup of slow-path MQ: "
8550 "rc = 0x%x\n", rc);
8551
8552 return rc;
8553 }
8554
8555 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8556 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
8557 phba->sli4_hba.mbx_wq->queue_id,
8558 phba->sli4_hba.mbx_cq->queue_id);
8559 }
8560
8561 return 0;
8562}
8563
8564
8565
8566
8567
8568
8569
8570
8571
8572
8573
8574
8575
8576int
8577lpfc_sli4_queue_setup(struct lpfc_hba *phba)
8578{
8579 uint32_t shdr_status, shdr_add_status;
8580 union lpfc_sli4_cfg_shdr *shdr;
8581 LPFC_MBOXQ_t *mboxq;
8582 int qidx;
8583 uint32_t length, io_channel;
8584 int rc = -ENOMEM;
8585
8586
8587 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
8588 if (!mboxq) {
8589 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8590 "3249 Unable to allocate memory for "
8591 "QUERY_FW_CFG mailbox command\n");
8592 return -ENOMEM;
8593 }
8594 length = (sizeof(struct lpfc_mbx_query_fw_config) -
8595 sizeof(struct lpfc_sli4_cfg_mhdr));
8596 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
8597 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
8598 length, LPFC_SLI4_MBX_EMBED);
8599
8600 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8601
8602 shdr = (union lpfc_sli4_cfg_shdr *)
8603 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
8604 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
8605 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
8606 if (shdr_status || shdr_add_status || rc) {
8607 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8608 "3250 QUERY_FW_CFG mailbox failed with status "
8609 "x%x add_status x%x, mbx status x%x\n",
8610 shdr_status, shdr_add_status, rc);
8611 if (rc != MBX_TIMEOUT)
8612 mempool_free(mboxq, phba->mbox_mem_pool);
8613 rc = -ENXIO;
8614 goto out_error;
8615 }
8616
8617 phba->sli4_hba.fw_func_mode =
8618 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
8619 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
8620 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
8621 phba->sli4_hba.physical_port =
8622 mboxq->u.mqe.un.query_fw_cfg.rsp.physical_port;
8623 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8624 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
8625 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
8626 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
8627
8628 if (rc != MBX_TIMEOUT)
8629 mempool_free(mboxq, phba->mbox_mem_pool);
8630
8631
8632
8633
8634 io_channel = phba->io_channel_irqs;
8635
8636
8637 if (io_channel && !phba->sli4_hba.hba_eq) {
8638 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8639 "3147 Fast-path EQs not allocated\n");
8640 rc = -ENOMEM;
8641 goto out_error;
8642 }
8643 for (qidx = 0; qidx < io_channel; qidx++) {
8644 if (!phba->sli4_hba.hba_eq[qidx]) {
8645 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8646 "0522 Fast-path EQ (%d) not "
8647 "allocated\n", qidx);
8648 rc = -ENOMEM;
8649 goto out_destroy;
8650 }
8651 rc = lpfc_eq_create(phba, phba->sli4_hba.hba_eq[qidx],
8652 phba->cfg_fcp_imax);
8653 if (rc) {
8654 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8655 "0523 Failed setup of fast-path EQ "
8656 "(%d), rc = 0x%x\n", qidx,
8657 (uint32_t)rc);
8658 goto out_destroy;
8659 }
8660 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8661 "2584 HBA EQ setup: queue[%d]-id=%d\n",
8662 qidx, phba->sli4_hba.hba_eq[qidx]->queue_id);
8663 }
8664
8665 if (phba->cfg_nvme_io_channel) {
8666 if (!phba->sli4_hba.nvme_cq || !phba->sli4_hba.nvme_wq) {
8667 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8668 "6084 Fast-path NVME %s array not allocated\n",
8669 (phba->sli4_hba.nvme_cq) ? "CQ" : "WQ");
8670 rc = -ENOMEM;
8671 goto out_destroy;
8672 }
8673
8674 for (qidx = 0; qidx < phba->cfg_nvme_io_channel; qidx++) {
8675 rc = lpfc_create_wq_cq(phba,
8676 phba->sli4_hba.hba_eq[
8677 qidx % io_channel],
8678 phba->sli4_hba.nvme_cq[qidx],
8679 phba->sli4_hba.nvme_wq[qidx],
8680 &phba->sli4_hba.nvme_cq_map[qidx],
8681 qidx, LPFC_NVME);
8682 if (rc) {
8683 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8684 "6123 Failed to setup fastpath "
8685 "NVME WQ/CQ (%d), rc = 0x%x\n",
8686 qidx, (uint32_t)rc);
8687 goto out_destroy;
8688 }
8689 }
8690 }
8691
8692 if (phba->cfg_fcp_io_channel) {
8693
8694 if (!phba->sli4_hba.fcp_cq || !phba->sli4_hba.fcp_wq) {
8695 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8696 "3148 Fast-path FCP %s array not allocated\n",
8697 phba->sli4_hba.fcp_cq ? "WQ" : "CQ");
8698 rc = -ENOMEM;
8699 goto out_destroy;
8700 }
8701
8702 for (qidx = 0; qidx < phba->cfg_fcp_io_channel; qidx++) {
8703 rc = lpfc_create_wq_cq(phba,
8704 phba->sli4_hba.hba_eq[
8705 qidx % io_channel],
8706 phba->sli4_hba.fcp_cq[qidx],
8707 phba->sli4_hba.fcp_wq[qidx],
8708 &phba->sli4_hba.fcp_cq_map[qidx],
8709 qidx, LPFC_FCP);
8710 if (rc) {
8711 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8712 "0535 Failed to setup fastpath "
8713 "FCP WQ/CQ (%d), rc = 0x%x\n",
8714 qidx, (uint32_t)rc);
8715 goto out_destroy;
8716 }
8717 }
8718 }
8719
8720
8721
8722
8723
8724
8725
8726 if (!phba->sli4_hba.mbx_cq || !phba->sli4_hba.mbx_wq) {
8727 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8728 "0528 %s not allocated\n",
8729 phba->sli4_hba.mbx_cq ?
8730 "Mailbox WQ" : "Mailbox CQ");
8731 rc = -ENOMEM;
8732 goto out_destroy;
8733 }
8734
8735 rc = lpfc_create_wq_cq(phba, phba->sli4_hba.hba_eq[0],
8736 phba->sli4_hba.mbx_cq,
8737 phba->sli4_hba.mbx_wq,
8738 NULL, 0, LPFC_MBOX);
8739 if (rc) {
8740 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8741 "0529 Failed setup of mailbox WQ/CQ: rc = 0x%x\n",
8742 (uint32_t)rc);
8743 goto out_destroy;
8744 }
8745 if (phba->nvmet_support) {
8746 if (!phba->sli4_hba.nvmet_cqset) {
8747 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8748 "3165 Fast-path NVME CQ Set "
8749 "array not allocated\n");
8750 rc = -ENOMEM;
8751 goto out_destroy;
8752 }
8753 if (phba->cfg_nvmet_mrq > 1) {
8754 rc = lpfc_cq_create_set(phba,
8755 phba->sli4_hba.nvmet_cqset,
8756 phba->sli4_hba.hba_eq,
8757 LPFC_WCQ, LPFC_NVMET);
8758 if (rc) {
8759 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8760 "3164 Failed setup of NVME CQ "
8761 "Set, rc = 0x%x\n",
8762 (uint32_t)rc);
8763 goto out_destroy;
8764 }
8765 } else {
8766
8767 rc = lpfc_cq_create(phba, phba->sli4_hba.nvmet_cqset[0],
8768 phba->sli4_hba.hba_eq[0],
8769 LPFC_WCQ, LPFC_NVMET);
8770 if (rc) {
8771 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8772 "6089 Failed setup NVMET CQ: "
8773 "rc = 0x%x\n", (uint32_t)rc);
8774 goto out_destroy;
8775 }
8776 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8777 "6090 NVMET CQ setup: cq-id=%d, "
8778 "parent eq-id=%d\n",
8779 phba->sli4_hba.nvmet_cqset[0]->queue_id,
8780 phba->sli4_hba.hba_eq[0]->queue_id);
8781 }
8782 }
8783
8784
8785 if (!phba->sli4_hba.els_cq || !phba->sli4_hba.els_wq) {
8786 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8787 "0530 ELS %s not allocated\n",
8788 phba->sli4_hba.els_cq ? "WQ" : "CQ");
8789 rc = -ENOMEM;
8790 goto out_destroy;
8791 }
8792 rc = lpfc_create_wq_cq(phba, phba->sli4_hba.hba_eq[0],
8793 phba->sli4_hba.els_cq,
8794 phba->sli4_hba.els_wq,
8795 NULL, 0, LPFC_ELS);
8796 if (rc) {
8797 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8798 "0529 Failed setup of ELS WQ/CQ: rc = 0x%x\n",
8799 (uint32_t)rc);
8800 goto out_destroy;
8801 }
8802 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8803 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
8804 phba->sli4_hba.els_wq->queue_id,
8805 phba->sli4_hba.els_cq->queue_id);
8806
8807 if (phba->cfg_nvme_io_channel) {
8808
8809 if (!phba->sli4_hba.nvmels_cq || !phba->sli4_hba.nvmels_wq) {
8810 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8811 "6091 LS %s not allocated\n",
8812 phba->sli4_hba.nvmels_cq ? "WQ" : "CQ");
8813 rc = -ENOMEM;
8814 goto out_destroy;
8815 }
8816 rc = lpfc_create_wq_cq(phba, phba->sli4_hba.hba_eq[0],
8817 phba->sli4_hba.nvmels_cq,
8818 phba->sli4_hba.nvmels_wq,
8819 NULL, 0, LPFC_NVME_LS);
8820 if (rc) {
8821 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8822 "0529 Failed setup of NVVME LS WQ/CQ: "
8823 "rc = 0x%x\n", (uint32_t)rc);
8824 goto out_destroy;
8825 }
8826
8827 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8828 "6096 ELS WQ setup: wq-id=%d, "
8829 "parent cq-id=%d\n",
8830 phba->sli4_hba.nvmels_wq->queue_id,
8831 phba->sli4_hba.nvmels_cq->queue_id);
8832 }
8833
8834
8835
8836
8837 if (phba->nvmet_support) {
8838 if ((!phba->sli4_hba.nvmet_cqset) ||
8839 (!phba->sli4_hba.nvmet_mrq_hdr) ||
8840 (!phba->sli4_hba.nvmet_mrq_data)) {
8841 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8842 "6130 MRQ CQ Queues not "
8843 "allocated\n");
8844 rc = -ENOMEM;
8845 goto out_destroy;
8846 }
8847 if (phba->cfg_nvmet_mrq > 1) {
8848 rc = lpfc_mrq_create(phba,
8849 phba->sli4_hba.nvmet_mrq_hdr,
8850 phba->sli4_hba.nvmet_mrq_data,
8851 phba->sli4_hba.nvmet_cqset,
8852 LPFC_NVMET);
8853 if (rc) {
8854 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8855 "6098 Failed setup of NVMET "
8856 "MRQ: rc = 0x%x\n",
8857 (uint32_t)rc);
8858 goto out_destroy;
8859 }
8860
8861 } else {
8862 rc = lpfc_rq_create(phba,
8863 phba->sli4_hba.nvmet_mrq_hdr[0],
8864 phba->sli4_hba.nvmet_mrq_data[0],
8865 phba->sli4_hba.nvmet_cqset[0],
8866 LPFC_NVMET);
8867 if (rc) {
8868 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8869 "6057 Failed setup of NVMET "
8870 "Receive Queue: rc = 0x%x\n",
8871 (uint32_t)rc);
8872 goto out_destroy;
8873 }
8874
8875 lpfc_printf_log(
8876 phba, KERN_INFO, LOG_INIT,
8877 "6099 NVMET RQ setup: hdr-rq-id=%d, "
8878 "dat-rq-id=%d parent cq-id=%d\n",
8879 phba->sli4_hba.nvmet_mrq_hdr[0]->queue_id,
8880 phba->sli4_hba.nvmet_mrq_data[0]->queue_id,
8881 phba->sli4_hba.nvmet_cqset[0]->queue_id);
8882
8883 }
8884 }
8885
8886 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
8887 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8888 "0540 Receive Queue not allocated\n");
8889 rc = -ENOMEM;
8890 goto out_destroy;
8891 }
8892
8893 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
8894 phba->sli4_hba.els_cq, LPFC_USOL);
8895 if (rc) {
8896 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8897 "0541 Failed setup of Receive Queue: "
8898 "rc = 0x%x\n", (uint32_t)rc);
8899 goto out_destroy;
8900 }
8901
8902 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8903 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
8904 "parent cq-id=%d\n",
8905 phba->sli4_hba.hdr_rq->queue_id,
8906 phba->sli4_hba.dat_rq->queue_id,
8907 phba->sli4_hba.els_cq->queue_id);
8908
8909 if (phba->cfg_fof) {
8910 rc = lpfc_fof_queue_setup(phba);
8911 if (rc) {
8912 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8913 "0549 Failed setup of FOF Queues: "
8914 "rc = 0x%x\n", rc);
8915 goto out_destroy;
8916 }
8917 }
8918
8919 for (qidx = 0; qidx < io_channel; qidx += LPFC_MAX_EQ_DELAY_EQID_CNT)
8920 lpfc_modify_hba_eq_delay(phba, qidx, LPFC_MAX_EQ_DELAY_EQID_CNT,
8921 phba->cfg_fcp_imax);
8922
8923 return 0;
8924
8925out_destroy:
8926 lpfc_sli4_queue_unset(phba);
8927out_error:
8928 return rc;
8929}
8930
8931
8932
8933
8934
8935
8936
8937
8938
8939
8940
8941
8942
8943void
8944lpfc_sli4_queue_unset(struct lpfc_hba *phba)
8945{
8946 int qidx;
8947
8948
8949 if (phba->cfg_fof)
8950 lpfc_fof_queue_destroy(phba);
8951
8952
8953 if (phba->sli4_hba.mbx_wq)
8954 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
8955
8956
8957 if (phba->sli4_hba.nvmels_wq)
8958 lpfc_wq_destroy(phba, phba->sli4_hba.nvmels_wq);
8959
8960
8961 if (phba->sli4_hba.els_wq)
8962 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
8963
8964
8965 if (phba->sli4_hba.hdr_rq)
8966 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq,
8967 phba->sli4_hba.dat_rq);
8968
8969
8970 if (phba->sli4_hba.fcp_wq)
8971 for (qidx = 0; qidx < phba->cfg_fcp_io_channel; qidx++)
8972 lpfc_wq_destroy(phba, phba->sli4_hba.fcp_wq[qidx]);
8973
8974
8975 if (phba->sli4_hba.nvme_wq) {
8976 for (qidx = 0; qidx < phba->cfg_nvme_io_channel; qidx++)
8977 lpfc_wq_destroy(phba, phba->sli4_hba.nvme_wq[qidx]);
8978 }
8979
8980
8981 if (phba->sli4_hba.mbx_cq)
8982 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
8983
8984
8985 if (phba->sli4_hba.els_cq)
8986 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
8987
8988
8989 if (phba->sli4_hba.nvmels_cq)
8990 lpfc_cq_destroy(phba, phba->sli4_hba.nvmels_cq);
8991
8992
8993 if (phba->sli4_hba.nvme_cq)
8994 for (qidx = 0; qidx < phba->cfg_nvme_io_channel; qidx++)
8995 lpfc_cq_destroy(phba, phba->sli4_hba.nvme_cq[qidx]);
8996
8997
8998 if (phba->sli4_hba.nvmet_mrq_hdr) {
8999 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
9000 lpfc_rq_destroy(phba,
9001 phba->sli4_hba.nvmet_mrq_hdr[qidx],
9002 phba->sli4_hba.nvmet_mrq_data[qidx]);
9003 }
9004
9005
9006 if (phba->sli4_hba.nvmet_cqset) {
9007 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
9008 lpfc_cq_destroy(phba,
9009 phba->sli4_hba.nvmet_cqset[qidx]);
9010 }
9011
9012
9013 if (phba->sli4_hba.fcp_cq)
9014 for (qidx = 0; qidx < phba->cfg_fcp_io_channel; qidx++)
9015 lpfc_cq_destroy(phba, phba->sli4_hba.fcp_cq[qidx]);
9016
9017
9018 if (phba->sli4_hba.hba_eq)
9019 for (qidx = 0; qidx < phba->io_channel_irqs; qidx++)
9020 lpfc_eq_destroy(phba, phba->sli4_hba.hba_eq[qidx]);
9021}
9022
9023
9024
9025
9026
9027
9028
9029
9030
9031
9032
9033
9034
9035
9036
9037
9038
9039static int
9040lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
9041{
9042 struct lpfc_cq_event *cq_event;
9043 int i;
9044
9045 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
9046 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
9047 if (!cq_event)
9048 goto out_pool_create_fail;
9049 list_add_tail(&cq_event->list,
9050 &phba->sli4_hba.sp_cqe_event_pool);
9051 }
9052 return 0;
9053
9054out_pool_create_fail:
9055 lpfc_sli4_cq_event_pool_destroy(phba);
9056 return -ENOMEM;
9057}
9058
9059
9060
9061
9062
9063
9064
9065
9066
9067
9068
9069static void
9070lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
9071{
9072 struct lpfc_cq_event *cq_event, *next_cq_event;
9073
9074 list_for_each_entry_safe(cq_event, next_cq_event,
9075 &phba->sli4_hba.sp_cqe_event_pool, list) {
9076 list_del(&cq_event->list);
9077 kfree(cq_event);
9078 }
9079}
9080
9081
9082
9083
9084
9085
9086
9087
9088
9089
9090
9091struct lpfc_cq_event *
9092__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
9093{
9094 struct lpfc_cq_event *cq_event = NULL;
9095
9096 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
9097 struct lpfc_cq_event, list);
9098 return cq_event;
9099}
9100
9101
9102
9103
9104
9105
9106
9107
9108
9109
9110
9111struct lpfc_cq_event *
9112lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
9113{
9114 struct lpfc_cq_event *cq_event;
9115 unsigned long iflags;
9116
9117 spin_lock_irqsave(&phba->hbalock, iflags);
9118 cq_event = __lpfc_sli4_cq_event_alloc(phba);
9119 spin_unlock_irqrestore(&phba->hbalock, iflags);
9120 return cq_event;
9121}
9122
9123
9124
9125
9126
9127
9128
9129
9130
9131void
9132__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
9133 struct lpfc_cq_event *cq_event)
9134{
9135 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
9136}
9137
9138
9139
9140
9141
9142
9143
9144
9145
9146void
9147lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
9148 struct lpfc_cq_event *cq_event)
9149{
9150 unsigned long iflags;
9151 spin_lock_irqsave(&phba->hbalock, iflags);
9152 __lpfc_sli4_cq_event_release(phba, cq_event);
9153 spin_unlock_irqrestore(&phba->hbalock, iflags);
9154}
9155
9156
9157
9158
9159
9160
9161
9162
9163static void
9164lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
9165{
9166 LIST_HEAD(cqelist);
9167 struct lpfc_cq_event *cqe;
9168 unsigned long iflags;
9169
9170
9171 spin_lock_irqsave(&phba->hbalock, iflags);
9172
9173 list_splice_init(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue,
9174 &cqelist);
9175
9176 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
9177 &cqelist);
9178 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9179
9180 list_splice_init(&phba->sli4_hba.sp_nvme_xri_aborted_work_queue,
9181 &cqelist);
9182 }
9183
9184 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
9185 &cqelist);
9186 spin_unlock_irqrestore(&phba->hbalock, iflags);
9187
9188 while (!list_empty(&cqelist)) {
9189 list_remove_head(&cqelist, cqe, struct lpfc_cq_event, list);
9190 lpfc_sli4_cq_event_release(phba, cqe);
9191 }
9192}
9193
9194
9195
9196
9197
9198
9199
9200
9201
9202
9203
9204
9205
9206int
9207lpfc_pci_function_reset(struct lpfc_hba *phba)
9208{
9209 LPFC_MBOXQ_t *mboxq;
9210 uint32_t rc = 0, if_type;
9211 uint32_t shdr_status, shdr_add_status;
9212 uint32_t rdy_chk;
9213 uint32_t port_reset = 0;
9214 union lpfc_sli4_cfg_shdr *shdr;
9215 struct lpfc_register reg_data;
9216 uint16_t devid;
9217
9218 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
9219 switch (if_type) {
9220 case LPFC_SLI_INTF_IF_TYPE_0:
9221 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
9222 GFP_KERNEL);
9223 if (!mboxq) {
9224 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9225 "0494 Unable to allocate memory for "
9226 "issuing SLI_FUNCTION_RESET mailbox "
9227 "command\n");
9228 return -ENOMEM;
9229 }
9230
9231
9232 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9233 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
9234 LPFC_SLI4_MBX_EMBED);
9235 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9236 shdr = (union lpfc_sli4_cfg_shdr *)
9237 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9238 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9239 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
9240 &shdr->response);
9241 if (rc != MBX_TIMEOUT)
9242 mempool_free(mboxq, phba->mbox_mem_pool);
9243 if (shdr_status || shdr_add_status || rc) {
9244 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9245 "0495 SLI_FUNCTION_RESET mailbox "
9246 "failed with status x%x add_status x%x,"
9247 " mbx status x%x\n",
9248 shdr_status, shdr_add_status, rc);
9249 rc = -ENXIO;
9250 }
9251 break;
9252 case LPFC_SLI_INTF_IF_TYPE_2:
9253wait:
9254
9255
9256
9257
9258
9259 for (rdy_chk = 0; rdy_chk < 1500; rdy_chk++) {
9260 if (lpfc_readl(phba->sli4_hba.u.if_type2.
9261 STATUSregaddr, ®_data.word0)) {
9262 rc = -ENODEV;
9263 goto out;
9264 }
9265 if (bf_get(lpfc_sliport_status_rdy, ®_data))
9266 break;
9267 msleep(20);
9268 }
9269
9270 if (!bf_get(lpfc_sliport_status_rdy, ®_data)) {
9271 phba->work_status[0] = readl(
9272 phba->sli4_hba.u.if_type2.ERR1regaddr);
9273 phba->work_status[1] = readl(
9274 phba->sli4_hba.u.if_type2.ERR2regaddr);
9275 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9276 "2890 Port not ready, port status reg "
9277 "0x%x error 1=0x%x, error 2=0x%x\n",
9278 reg_data.word0,
9279 phba->work_status[0],
9280 phba->work_status[1]);
9281 rc = -ENODEV;
9282 goto out;
9283 }
9284
9285 if (!port_reset) {
9286
9287
9288
9289 reg_data.word0 = 0;
9290 bf_set(lpfc_sliport_ctrl_end, ®_data,
9291 LPFC_SLIPORT_LITTLE_ENDIAN);
9292 bf_set(lpfc_sliport_ctrl_ip, ®_data,
9293 LPFC_SLIPORT_INIT_PORT);
9294 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
9295 CTRLregaddr);
9296
9297 pci_read_config_word(phba->pcidev,
9298 PCI_DEVICE_ID, &devid);
9299
9300 port_reset = 1;
9301 msleep(20);
9302 goto wait;
9303 } else if (bf_get(lpfc_sliport_status_rn, ®_data)) {
9304 rc = -ENODEV;
9305 goto out;
9306 }
9307 break;
9308
9309 case LPFC_SLI_INTF_IF_TYPE_1:
9310 default:
9311 break;
9312 }
9313
9314out:
9315
9316 if (rc) {
9317 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9318 "3317 HBA not functional: IP Reset Failed "
9319 "try: echo fw_reset > board_mode\n");
9320 rc = -ENODEV;
9321 }
9322
9323 return rc;
9324}
9325
9326
9327
9328
9329
9330
9331
9332
9333
9334
9335
9336
9337static int
9338lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
9339{
9340 struct pci_dev *pdev;
9341 unsigned long bar0map_len, bar1map_len, bar2map_len;
9342 int error = -ENODEV;
9343 uint32_t if_type;
9344
9345
9346 if (!phba->pcidev)
9347 return error;
9348 else
9349 pdev = phba->pcidev;
9350
9351
9352 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0
9353 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(64)) != 0) {
9354 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0
9355 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(32)) != 0) {
9356 return error;
9357 }
9358 }
9359
9360
9361
9362
9363
9364 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
9365 &phba->sli4_hba.sli_intf.word0)) {
9366 return error;
9367 }
9368
9369
9370 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
9371 LPFC_SLI_INTF_VALID) {
9372 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9373 "2894 SLI_INTF reg contents invalid "
9374 "sli_intf reg 0x%x\n",
9375 phba->sli4_hba.sli_intf.word0);
9376 return error;
9377 }
9378
9379 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
9380
9381
9382
9383
9384
9385
9386 if (pci_resource_start(pdev, PCI_64BIT_BAR0)) {
9387 phba->pci_bar0_map = pci_resource_start(pdev, PCI_64BIT_BAR0);
9388 bar0map_len = pci_resource_len(pdev, PCI_64BIT_BAR0);
9389
9390
9391
9392
9393
9394 phba->sli4_hba.conf_regs_memmap_p =
9395 ioremap(phba->pci_bar0_map, bar0map_len);
9396 if (!phba->sli4_hba.conf_regs_memmap_p) {
9397 dev_printk(KERN_ERR, &pdev->dev,
9398 "ioremap failed for SLI4 PCI config "
9399 "registers.\n");
9400 goto out;
9401 }
9402 phba->pci_bar0_memmap_p = phba->sli4_hba.conf_regs_memmap_p;
9403
9404 lpfc_sli4_bar0_register_memmap(phba, if_type);
9405 } else {
9406 phba->pci_bar0_map = pci_resource_start(pdev, 1);
9407 bar0map_len = pci_resource_len(pdev, 1);
9408 if (if_type == LPFC_SLI_INTF_IF_TYPE_2) {
9409 dev_printk(KERN_ERR, &pdev->dev,
9410 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
9411 goto out;
9412 }
9413 phba->sli4_hba.conf_regs_memmap_p =
9414 ioremap(phba->pci_bar0_map, bar0map_len);
9415 if (!phba->sli4_hba.conf_regs_memmap_p) {
9416 dev_printk(KERN_ERR, &pdev->dev,
9417 "ioremap failed for SLI4 PCI config "
9418 "registers.\n");
9419 goto out;
9420 }
9421 lpfc_sli4_bar0_register_memmap(phba, if_type);
9422 }
9423
9424 if ((if_type == LPFC_SLI_INTF_IF_TYPE_0) &&
9425 (pci_resource_start(pdev, PCI_64BIT_BAR2))) {
9426
9427
9428
9429
9430 phba->pci_bar1_map = pci_resource_start(pdev, PCI_64BIT_BAR2);
9431 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
9432 phba->sli4_hba.ctrl_regs_memmap_p =
9433 ioremap(phba->pci_bar1_map, bar1map_len);
9434 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
9435 dev_printk(KERN_ERR, &pdev->dev,
9436 "ioremap failed for SLI4 HBA control registers.\n");
9437 goto out_iounmap_conf;
9438 }
9439 phba->pci_bar2_memmap_p = phba->sli4_hba.ctrl_regs_memmap_p;
9440 lpfc_sli4_bar1_register_memmap(phba);
9441 }
9442
9443 if ((if_type == LPFC_SLI_INTF_IF_TYPE_0) &&
9444 (pci_resource_start(pdev, PCI_64BIT_BAR4))) {
9445
9446
9447
9448
9449 phba->pci_bar2_map = pci_resource_start(pdev, PCI_64BIT_BAR4);
9450 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
9451 phba->sli4_hba.drbl_regs_memmap_p =
9452 ioremap(phba->pci_bar2_map, bar2map_len);
9453 if (!phba->sli4_hba.drbl_regs_memmap_p) {
9454 dev_printk(KERN_ERR, &pdev->dev,
9455 "ioremap failed for SLI4 HBA doorbell registers.\n");
9456 goto out_iounmap_ctrl;
9457 }
9458 phba->pci_bar4_memmap_p = phba->sli4_hba.drbl_regs_memmap_p;
9459 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
9460 if (error)
9461 goto out_iounmap_all;
9462 }
9463
9464 return 0;
9465
9466out_iounmap_all:
9467 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
9468out_iounmap_ctrl:
9469 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
9470out_iounmap_conf:
9471 iounmap(phba->sli4_hba.conf_regs_memmap_p);
9472out:
9473 return error;
9474}
9475
9476
9477
9478
9479
9480
9481
9482
9483static void
9484lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
9485{
9486 uint32_t if_type;
9487 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
9488
9489 switch (if_type) {
9490 case LPFC_SLI_INTF_IF_TYPE_0:
9491 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
9492 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
9493 iounmap(phba->sli4_hba.conf_regs_memmap_p);
9494 break;
9495 case LPFC_SLI_INTF_IF_TYPE_2:
9496 iounmap(phba->sli4_hba.conf_regs_memmap_p);
9497 break;
9498 case LPFC_SLI_INTF_IF_TYPE_1:
9499 default:
9500 dev_printk(KERN_ERR, &phba->pcidev->dev,
9501 "FATAL - unsupported SLI4 interface type - %d\n",
9502 if_type);
9503 break;
9504 }
9505}
9506
9507
9508
9509
9510
9511
9512
9513
9514
9515
9516
9517
9518static int
9519lpfc_sli_enable_msix(struct lpfc_hba *phba)
9520{
9521 int rc;
9522 LPFC_MBOXQ_t *pmb;
9523
9524
9525 rc = pci_alloc_irq_vectors(phba->pcidev,
9526 LPFC_MSIX_VECTORS, LPFC_MSIX_VECTORS, PCI_IRQ_MSIX);
9527 if (rc < 0) {
9528 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9529 "0420 PCI enable MSI-X failed (%d)\n", rc);
9530 goto vec_fail_out;
9531 }
9532
9533
9534
9535
9536
9537
9538 rc = request_irq(pci_irq_vector(phba->pcidev, 0),
9539 &lpfc_sli_sp_intr_handler, 0,
9540 LPFC_SP_DRIVER_HANDLER_NAME, phba);
9541 if (rc) {
9542 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
9543 "0421 MSI-X slow-path request_irq failed "
9544 "(%d)\n", rc);
9545 goto msi_fail_out;
9546 }
9547
9548
9549 rc = request_irq(pci_irq_vector(phba->pcidev, 1),
9550 &lpfc_sli_fp_intr_handler, 0,
9551 LPFC_FP_DRIVER_HANDLER_NAME, phba);
9552
9553 if (rc) {
9554 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
9555 "0429 MSI-X fast-path request_irq failed "
9556 "(%d)\n", rc);
9557 goto irq_fail_out;
9558 }
9559
9560
9561
9562
9563 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9564
9565 if (!pmb) {
9566 rc = -ENOMEM;
9567 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9568 "0474 Unable to allocate memory for issuing "
9569 "MBOX_CONFIG_MSI command\n");
9570 goto mem_fail_out;
9571 }
9572 rc = lpfc_config_msi(phba, pmb);
9573 if (rc)
9574 goto mbx_fail_out;
9575 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
9576 if (rc != MBX_SUCCESS) {
9577 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
9578 "0351 Config MSI mailbox command failed, "
9579 "mbxCmd x%x, mbxStatus x%x\n",
9580 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
9581 goto mbx_fail_out;
9582 }
9583
9584
9585 mempool_free(pmb, phba->mbox_mem_pool);
9586 return rc;
9587
9588mbx_fail_out:
9589
9590 mempool_free(pmb, phba->mbox_mem_pool);
9591
9592mem_fail_out:
9593
9594 free_irq(pci_irq_vector(phba->pcidev, 1), phba);
9595
9596irq_fail_out:
9597
9598 free_irq(pci_irq_vector(phba->pcidev, 0), phba);
9599
9600msi_fail_out:
9601
9602 pci_free_irq_vectors(phba->pcidev);
9603
9604vec_fail_out:
9605 return rc;
9606}
9607
9608
9609
9610
9611
9612
9613
9614
9615
9616
9617
9618
9619
9620
9621
9622static int
9623lpfc_sli_enable_msi(struct lpfc_hba *phba)
9624{
9625 int rc;
9626
9627 rc = pci_enable_msi(phba->pcidev);
9628 if (!rc)
9629 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9630 "0462 PCI enable MSI mode success.\n");
9631 else {
9632 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9633 "0471 PCI enable MSI mode failed (%d)\n", rc);
9634 return rc;
9635 }
9636
9637 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
9638 0, LPFC_DRIVER_NAME, phba);
9639 if (rc) {
9640 pci_disable_msi(phba->pcidev);
9641 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
9642 "0478 MSI request_irq failed (%d)\n", rc);
9643 }
9644 return rc;
9645}
9646
9647
9648
9649
9650
9651
9652
9653
9654
9655
9656
9657
9658
9659
9660
9661
9662
9663static uint32_t
9664lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
9665{
9666 uint32_t intr_mode = LPFC_INTR_ERROR;
9667 int retval;
9668
9669 if (cfg_mode == 2) {
9670
9671 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
9672 if (!retval) {
9673
9674 retval = lpfc_sli_enable_msix(phba);
9675 if (!retval) {
9676
9677 phba->intr_type = MSIX;
9678 intr_mode = 2;
9679 }
9680 }
9681 }
9682
9683
9684 if (cfg_mode >= 1 && phba->intr_type == NONE) {
9685 retval = lpfc_sli_enable_msi(phba);
9686 if (!retval) {
9687
9688 phba->intr_type = MSI;
9689 intr_mode = 1;
9690 }
9691 }
9692
9693
9694 if (phba->intr_type == NONE) {
9695 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
9696 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
9697 if (!retval) {
9698
9699 phba->intr_type = INTx;
9700 intr_mode = 0;
9701 }
9702 }
9703 return intr_mode;
9704}
9705
9706
9707
9708
9709
9710
9711
9712
9713
9714
9715static void
9716lpfc_sli_disable_intr(struct lpfc_hba *phba)
9717{
9718 int nr_irqs, i;
9719
9720 if (phba->intr_type == MSIX)
9721 nr_irqs = LPFC_MSIX_VECTORS;
9722 else
9723 nr_irqs = 1;
9724
9725 for (i = 0; i < nr_irqs; i++)
9726 free_irq(pci_irq_vector(phba->pcidev, i), phba);
9727 pci_free_irq_vectors(phba->pcidev);
9728
9729
9730 phba->intr_type = NONE;
9731 phba->sli.slistat.sli_intr = 0;
9732}
9733
9734
9735
9736
9737
9738
9739
9740
9741
9742
9743
9744
9745
9746
9747static void
9748lpfc_cpu_affinity_check(struct lpfc_hba *phba, int vectors)
9749{
9750 struct lpfc_vector_map_info *cpup;
9751 int index = 0;
9752 int vec = 0;
9753 int cpu;
9754#ifdef CONFIG_X86
9755 struct cpuinfo_x86 *cpuinfo;
9756#endif
9757
9758
9759 memset(phba->sli4_hba.cpu_map, 0xff,
9760 (sizeof(struct lpfc_vector_map_info) *
9761 phba->sli4_hba.num_present_cpu));
9762
9763
9764 cpup = phba->sli4_hba.cpu_map;
9765 for (cpu = 0; cpu < phba->sli4_hba.num_present_cpu; cpu++) {
9766#ifdef CONFIG_X86
9767 cpuinfo = &cpu_data(cpu);
9768 cpup->phys_id = cpuinfo->phys_proc_id;
9769 cpup->core_id = cpuinfo->cpu_core_id;
9770#else
9771
9772 cpup->phys_id = 0;
9773 cpup->core_id = 0;
9774#endif
9775 cpup->channel_id = index;
9776 cpup->irq = pci_irq_vector(phba->pcidev, vec);
9777 vec++;
9778 if (vec >= vectors)
9779 vec = 0;
9780 index++;
9781 if (index >= phba->cfg_fcp_io_channel)
9782 index = 0;
9783 cpup++;
9784 }
9785}
9786
9787
9788
9789
9790
9791
9792
9793
9794
9795
9796
9797
9798
9799static int
9800lpfc_sli4_enable_msix(struct lpfc_hba *phba)
9801{
9802 int vectors, rc, index;
9803 char *name;
9804
9805
9806 vectors = phba->io_channel_irqs;
9807 if (phba->cfg_fof)
9808 vectors++;
9809
9810 rc = pci_alloc_irq_vectors(phba->pcidev,
9811 (phba->nvmet_support) ? 1 : 2,
9812 vectors, PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
9813 if (rc < 0) {
9814 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9815 "0484 PCI enable MSI-X failed (%d)\n", rc);
9816 goto vec_fail_out;
9817 }
9818 vectors = rc;
9819
9820
9821 for (index = 0; index < vectors; index++) {
9822 name = phba->sli4_hba.hba_eq_hdl[index].handler_name;
9823 memset(name, 0, LPFC_SLI4_HANDLER_NAME_SZ);
9824 snprintf(name, LPFC_SLI4_HANDLER_NAME_SZ,
9825 LPFC_DRIVER_HANDLER_NAME"%d", index);
9826
9827 phba->sli4_hba.hba_eq_hdl[index].idx = index;
9828 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
9829 atomic_set(&phba->sli4_hba.hba_eq_hdl[index].hba_eq_in_use, 1);
9830 if (phba->cfg_fof && (index == (vectors - 1)))
9831 rc = request_irq(pci_irq_vector(phba->pcidev, index),
9832 &lpfc_sli4_fof_intr_handler, 0,
9833 name,
9834 &phba->sli4_hba.hba_eq_hdl[index]);
9835 else
9836 rc = request_irq(pci_irq_vector(phba->pcidev, index),
9837 &lpfc_sli4_hba_intr_handler, 0,
9838 name,
9839 &phba->sli4_hba.hba_eq_hdl[index]);
9840 if (rc) {
9841 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
9842 "0486 MSI-X fast-path (%d) "
9843 "request_irq failed (%d)\n", index, rc);
9844 goto cfg_fail_out;
9845 }
9846 }
9847
9848 if (phba->cfg_fof)
9849 vectors--;
9850
9851 if (vectors != phba->io_channel_irqs) {
9852 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9853 "3238 Reducing IO channels to match number of "
9854 "MSI-X vectors, requested %d got %d\n",
9855 phba->io_channel_irqs, vectors);
9856 if (phba->cfg_fcp_io_channel > vectors)
9857 phba->cfg_fcp_io_channel = vectors;
9858 if (phba->cfg_nvme_io_channel > vectors)
9859 phba->cfg_nvme_io_channel = vectors;
9860 if (phba->cfg_fcp_io_channel > phba->cfg_nvme_io_channel)
9861 phba->io_channel_irqs = phba->cfg_fcp_io_channel;
9862 else
9863 phba->io_channel_irqs = phba->cfg_nvme_io_channel;
9864 }
9865 lpfc_cpu_affinity_check(phba, vectors);
9866
9867 return rc;
9868
9869cfg_fail_out:
9870
9871 for (--index; index >= 0; index--)
9872 free_irq(pci_irq_vector(phba->pcidev, index),
9873 &phba->sli4_hba.hba_eq_hdl[index]);
9874
9875
9876 pci_free_irq_vectors(phba->pcidev);
9877
9878vec_fail_out:
9879 return rc;
9880}
9881
9882
9883
9884
9885
9886
9887
9888
9889
9890
9891
9892
9893
9894
9895
9896static int
9897lpfc_sli4_enable_msi(struct lpfc_hba *phba)
9898{
9899 int rc, index;
9900
9901 rc = pci_enable_msi(phba->pcidev);
9902 if (!rc)
9903 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9904 "0487 PCI enable MSI mode success.\n");
9905 else {
9906 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9907 "0488 PCI enable MSI mode failed (%d)\n", rc);
9908 return rc;
9909 }
9910
9911 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
9912 0, LPFC_DRIVER_NAME, phba);
9913 if (rc) {
9914 pci_disable_msi(phba->pcidev);
9915 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
9916 "0490 MSI request_irq failed (%d)\n", rc);
9917 return rc;
9918 }
9919
9920 for (index = 0; index < phba->io_channel_irqs; index++) {
9921 phba->sli4_hba.hba_eq_hdl[index].idx = index;
9922 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
9923 }
9924
9925 if (phba->cfg_fof) {
9926 phba->sli4_hba.hba_eq_hdl[index].idx = index;
9927 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
9928 }
9929 return 0;
9930}
9931
9932
9933
9934
9935
9936
9937
9938
9939
9940
9941
9942
9943
9944
9945
9946
9947
9948static uint32_t
9949lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
9950{
9951 uint32_t intr_mode = LPFC_INTR_ERROR;
9952 int retval, idx;
9953
9954 if (cfg_mode == 2) {
9955
9956 retval = 0;
9957 if (!retval) {
9958
9959 retval = lpfc_sli4_enable_msix(phba);
9960 if (!retval) {
9961
9962 phba->intr_type = MSIX;
9963 intr_mode = 2;
9964 }
9965 }
9966 }
9967
9968
9969 if (cfg_mode >= 1 && phba->intr_type == NONE) {
9970 retval = lpfc_sli4_enable_msi(phba);
9971 if (!retval) {
9972
9973 phba->intr_type = MSI;
9974 intr_mode = 1;
9975 }
9976 }
9977
9978
9979 if (phba->intr_type == NONE) {
9980 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
9981 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
9982 if (!retval) {
9983 struct lpfc_hba_eq_hdl *eqhdl;
9984
9985
9986 phba->intr_type = INTx;
9987 intr_mode = 0;
9988
9989 for (idx = 0; idx < phba->io_channel_irqs; idx++) {
9990 eqhdl = &phba->sli4_hba.hba_eq_hdl[idx];
9991 eqhdl->idx = idx;
9992 eqhdl->phba = phba;
9993 atomic_set(&eqhdl->hba_eq_in_use, 1);
9994 }
9995 if (phba->cfg_fof) {
9996 eqhdl = &phba->sli4_hba.hba_eq_hdl[idx];
9997 eqhdl->idx = idx;
9998 eqhdl->phba = phba;
9999 atomic_set(&eqhdl->hba_eq_in_use, 1);
10000 }
10001 }
10002 }
10003 return intr_mode;
10004}
10005
10006
10007
10008
10009
10010
10011
10012
10013
10014
10015static void
10016lpfc_sli4_disable_intr(struct lpfc_hba *phba)
10017{
10018
10019 if (phba->intr_type == MSIX) {
10020 int index;
10021
10022
10023 for (index = 0; index < phba->io_channel_irqs; index++)
10024 free_irq(pci_irq_vector(phba->pcidev, index),
10025 &phba->sli4_hba.hba_eq_hdl[index]);
10026
10027 if (phba->cfg_fof)
10028 free_irq(pci_irq_vector(phba->pcidev, index),
10029 &phba->sli4_hba.hba_eq_hdl[index]);
10030 } else {
10031 free_irq(phba->pcidev->irq, phba);
10032 }
10033
10034 pci_free_irq_vectors(phba->pcidev);
10035
10036
10037 phba->intr_type = NONE;
10038 phba->sli.slistat.sli_intr = 0;
10039}
10040
10041
10042
10043
10044
10045
10046
10047
10048static void
10049lpfc_unset_hba(struct lpfc_hba *phba)
10050{
10051 struct lpfc_vport *vport = phba->pport;
10052 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
10053
10054 spin_lock_irq(shost->host_lock);
10055 vport->load_flag |= FC_UNLOADING;
10056 spin_unlock_irq(shost->host_lock);
10057
10058 kfree(phba->vpi_bmask);
10059 kfree(phba->vpi_ids);
10060
10061 lpfc_stop_hba_timers(phba);
10062
10063 phba->pport->work_port_events = 0;
10064
10065 lpfc_sli_hba_down(phba);
10066
10067 lpfc_sli_brdrestart(phba);
10068
10069 lpfc_sli_disable_intr(phba);
10070
10071 return;
10072}
10073
10074
10075
10076
10077
10078
10079
10080
10081
10082
10083
10084
10085
10086
10087static void
10088lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
10089{
10090 int wait_time = 0;
10091 int nvme_xri_cmpl = 1;
10092 int nvmet_xri_cmpl = 1;
10093 int fcp_xri_cmpl = 1;
10094 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
10095
10096 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP)
10097 fcp_xri_cmpl =
10098 list_empty(&phba->sli4_hba.lpfc_abts_scsi_buf_list);
10099 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
10100 nvme_xri_cmpl =
10101 list_empty(&phba->sli4_hba.lpfc_abts_nvme_buf_list);
10102 nvmet_xri_cmpl =
10103 list_empty(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
10104 }
10105
10106 while (!fcp_xri_cmpl || !els_xri_cmpl || !nvme_xri_cmpl ||
10107 !nvmet_xri_cmpl) {
10108 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
10109 if (!nvme_xri_cmpl)
10110 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10111 "6100 NVME XRI exchange busy "
10112 "wait time: %d seconds.\n",
10113 wait_time/1000);
10114 if (!fcp_xri_cmpl)
10115 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10116 "2877 FCP XRI exchange busy "
10117 "wait time: %d seconds.\n",
10118 wait_time/1000);
10119 if (!els_xri_cmpl)
10120 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10121 "2878 ELS XRI exchange busy "
10122 "wait time: %d seconds.\n",
10123 wait_time/1000);
10124 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
10125 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
10126 } else {
10127 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
10128 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
10129 }
10130 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
10131 nvme_xri_cmpl = list_empty(
10132 &phba->sli4_hba.lpfc_abts_nvme_buf_list);
10133 nvmet_xri_cmpl = list_empty(
10134 &phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
10135 }
10136
10137 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP)
10138 fcp_xri_cmpl = list_empty(
10139 &phba->sli4_hba.lpfc_abts_scsi_buf_list);
10140
10141 els_xri_cmpl =
10142 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
10143
10144 }
10145}
10146
10147
10148
10149
10150
10151
10152
10153
10154
10155
10156
10157static void
10158lpfc_sli4_hba_unset(struct lpfc_hba *phba)
10159{
10160 int wait_cnt = 0;
10161 LPFC_MBOXQ_t *mboxq;
10162 struct pci_dev *pdev = phba->pcidev;
10163
10164 lpfc_stop_hba_timers(phba);
10165 phba->sli4_hba.intr_enable = 0;
10166
10167
10168
10169
10170
10171
10172
10173 spin_lock_irq(&phba->hbalock);
10174 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
10175 spin_unlock_irq(&phba->hbalock);
10176
10177 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
10178 msleep(10);
10179 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
10180 break;
10181 }
10182
10183 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
10184 spin_lock_irq(&phba->hbalock);
10185 mboxq = phba->sli.mbox_active;
10186 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
10187 __lpfc_mbox_cmpl_put(phba, mboxq);
10188 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
10189 phba->sli.mbox_active = NULL;
10190 spin_unlock_irq(&phba->hbalock);
10191 }
10192
10193
10194 lpfc_sli_hba_iocb_abort(phba);
10195
10196
10197 lpfc_sli4_xri_exchange_busy_wait(phba);
10198
10199
10200 lpfc_sli4_disable_intr(phba);
10201
10202
10203 if (phba->cfg_sriov_nr_virtfn)
10204 pci_disable_sriov(pdev);
10205
10206
10207 kthread_stop(phba->worker_thread);
10208
10209
10210
10211
10212 lpfc_sli4_queue_unset(phba);
10213 lpfc_sli4_queue_destroy(phba);
10214
10215
10216 lpfc_pci_function_reset(phba);
10217
10218
10219 phba->pport->work_port_events = 0;
10220}
10221
10222
10223
10224
10225
10226
10227
10228
10229
10230
10231
10232
10233
10234int
10235lpfc_pc_sli4_params_get(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
10236{
10237 int rc;
10238 struct lpfc_mqe *mqe;
10239 struct lpfc_pc_sli4_params *sli4_params;
10240 uint32_t mbox_tmo;
10241
10242 rc = 0;
10243 mqe = &mboxq->u.mqe;
10244
10245
10246 lpfc_pc_sli4_params(mboxq);
10247 if (!phba->sli4_hba.intr_enable)
10248 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
10249 else {
10250 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
10251 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
10252 }
10253
10254 if (unlikely(rc))
10255 return 1;
10256
10257 sli4_params = &phba->sli4_hba.pc_sli4_params;
10258 sli4_params->if_type = bf_get(if_type, &mqe->un.sli4_params);
10259 sli4_params->sli_rev = bf_get(sli_rev, &mqe->un.sli4_params);
10260 sli4_params->sli_family = bf_get(sli_family, &mqe->un.sli4_params);
10261 sli4_params->featurelevel_1 = bf_get(featurelevel_1,
10262 &mqe->un.sli4_params);
10263 sli4_params->featurelevel_2 = bf_get(featurelevel_2,
10264 &mqe->un.sli4_params);
10265 sli4_params->proto_types = mqe->un.sli4_params.word3;
10266 sli4_params->sge_supp_len = mqe->un.sli4_params.sge_supp_len;
10267 sli4_params->if_page_sz = bf_get(if_page_sz, &mqe->un.sli4_params);
10268 sli4_params->rq_db_window = bf_get(rq_db_window, &mqe->un.sli4_params);
10269 sli4_params->loopbk_scope = bf_get(loopbk_scope, &mqe->un.sli4_params);
10270 sli4_params->eq_pages_max = bf_get(eq_pages, &mqe->un.sli4_params);
10271 sli4_params->eqe_size = bf_get(eqe_size, &mqe->un.sli4_params);
10272 sli4_params->cq_pages_max = bf_get(cq_pages, &mqe->un.sli4_params);
10273 sli4_params->cqe_size = bf_get(cqe_size, &mqe->un.sli4_params);
10274 sli4_params->mq_pages_max = bf_get(mq_pages, &mqe->un.sli4_params);
10275 sli4_params->mqe_size = bf_get(mqe_size, &mqe->un.sli4_params);
10276 sli4_params->mq_elem_cnt = bf_get(mq_elem_cnt, &mqe->un.sli4_params);
10277 sli4_params->wq_pages_max = bf_get(wq_pages, &mqe->un.sli4_params);
10278 sli4_params->wqe_size = bf_get(wqe_size, &mqe->un.sli4_params);
10279 sli4_params->rq_pages_max = bf_get(rq_pages, &mqe->un.sli4_params);
10280 sli4_params->rqe_size = bf_get(rqe_size, &mqe->un.sli4_params);
10281 sli4_params->hdr_pages_max = bf_get(hdr_pages, &mqe->un.sli4_params);
10282 sli4_params->hdr_size = bf_get(hdr_size, &mqe->un.sli4_params);
10283 sli4_params->hdr_pp_align = bf_get(hdr_pp_align, &mqe->un.sli4_params);
10284 sli4_params->sgl_pages_max = bf_get(sgl_pages, &mqe->un.sli4_params);
10285 sli4_params->sgl_pp_align = bf_get(sgl_pp_align, &mqe->un.sli4_params);
10286
10287
10288 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
10289 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
10290
10291 return rc;
10292}
10293
10294
10295
10296
10297
10298
10299
10300
10301
10302
10303
10304
10305
10306int
10307lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
10308{
10309 int rc;
10310 struct lpfc_mqe *mqe = &mboxq->u.mqe;
10311 struct lpfc_pc_sli4_params *sli4_params;
10312 uint32_t mbox_tmo;
10313 int length;
10314 struct lpfc_sli4_parameters *mbx_sli4_parameters;
10315
10316
10317
10318
10319
10320
10321 phba->sli4_hba.rpi_hdrs_in_use = 1;
10322
10323
10324 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
10325 sizeof(struct lpfc_sli4_cfg_mhdr));
10326 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
10327 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
10328 length, LPFC_SLI4_MBX_EMBED);
10329 if (!phba->sli4_hba.intr_enable)
10330 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
10331 else {
10332 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
10333 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
10334 }
10335 if (unlikely(rc))
10336 return rc;
10337 sli4_params = &phba->sli4_hba.pc_sli4_params;
10338 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
10339 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
10340 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
10341 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
10342 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
10343 mbx_sli4_parameters);
10344 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
10345 mbx_sli4_parameters);
10346 if (bf_get(cfg_phwq, mbx_sli4_parameters))
10347 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
10348 else
10349 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
10350 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
10351 sli4_params->loopbk_scope = bf_get(loopbk_scope, mbx_sli4_parameters);
10352 sli4_params->oas_supported = bf_get(cfg_oas, mbx_sli4_parameters);
10353 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
10354 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
10355 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
10356 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
10357 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters);
10358 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
10359 mbx_sli4_parameters);
10360 sli4_params->wqpcnt = bf_get(cfg_wqpcnt, mbx_sli4_parameters);
10361 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
10362 mbx_sli4_parameters);
10363 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
10364 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
10365 phba->nvme_support = (bf_get(cfg_nvme, mbx_sli4_parameters) &&
10366 bf_get(cfg_xib, mbx_sli4_parameters));
10367
10368 if ((phba->cfg_enable_fc4_type == LPFC_ENABLE_FCP) ||
10369 !phba->nvme_support) {
10370 phba->nvme_support = 0;
10371 phba->nvmet_support = 0;
10372 phba->cfg_nvmet_mrq = 0;
10373 phba->cfg_nvme_io_channel = 0;
10374 phba->io_channel_irqs = phba->cfg_fcp_io_channel;
10375 lpfc_printf_log(phba, KERN_ERR, LOG_INIT | LOG_NVME,
10376 "6101 Disabling NVME support: "
10377 "Not supported by firmware: %d %d\n",
10378 bf_get(cfg_nvme, mbx_sli4_parameters),
10379 bf_get(cfg_xib, mbx_sli4_parameters));
10380
10381
10382 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
10383 return -ENODEV;
10384 phba->cfg_enable_fc4_type = LPFC_ENABLE_FCP;
10385 }
10386
10387 if (bf_get(cfg_xib, mbx_sli4_parameters) && phba->cfg_suppress_rsp)
10388 phba->sli.sli_flag |= LPFC_SLI_SUPPRESS_RSP;
10389
10390 if (bf_get(cfg_eqdr, mbx_sli4_parameters))
10391 phba->sli.sli_flag |= LPFC_SLI_USE_EQDR;
10392
10393
10394 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
10395 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
10396
10397
10398
10399
10400
10401
10402 if (bf_get(cfg_ext_embed_cb, mbx_sli4_parameters))
10403 phba->fcp_embed_io = 1;
10404 else
10405 phba->fcp_embed_io = 0;
10406
10407
10408
10409
10410 if (bf_get(cfg_mds_diags, mbx_sli4_parameters))
10411 phba->mds_diags_support = 1;
10412 else
10413 phba->mds_diags_support = 0;
10414 return 0;
10415}
10416
10417
10418
10419
10420
10421
10422
10423
10424
10425
10426
10427
10428
10429
10430
10431
10432
10433
10434static int
10435lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
10436{
10437 struct lpfc_hba *phba;
10438 struct lpfc_vport *vport = NULL;
10439 struct Scsi_Host *shost = NULL;
10440 int error;
10441 uint32_t cfg_mode, intr_mode;
10442
10443
10444 phba = lpfc_hba_alloc(pdev);
10445 if (!phba)
10446 return -ENOMEM;
10447
10448
10449 error = lpfc_enable_pci_dev(phba);
10450 if (error)
10451 goto out_free_phba;
10452
10453
10454 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
10455 if (error)
10456 goto out_disable_pci_dev;
10457
10458
10459 error = lpfc_sli_pci_mem_setup(phba);
10460 if (error) {
10461 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10462 "1402 Failed to set up pci memory space.\n");
10463 goto out_disable_pci_dev;
10464 }
10465
10466
10467 error = lpfc_sli_driver_resource_setup(phba);
10468 if (error) {
10469 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10470 "1404 Failed to set up driver resource.\n");
10471 goto out_unset_pci_mem_s3;
10472 }
10473
10474
10475
10476 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
10477 if (error) {
10478 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10479 "1405 Failed to initialize iocb list.\n");
10480 goto out_unset_driver_resource_s3;
10481 }
10482
10483
10484 error = lpfc_setup_driver_resource_phase2(phba);
10485 if (error) {
10486 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10487 "1406 Failed to set up driver resource.\n");
10488 goto out_free_iocb_list;
10489 }
10490
10491
10492 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
10493
10494
10495 error = lpfc_create_shost(phba);
10496 if (error) {
10497 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10498 "1407 Failed to create scsi host.\n");
10499 goto out_unset_driver_resource;
10500 }
10501
10502
10503 vport = phba->pport;
10504 error = lpfc_alloc_sysfs_attr(vport);
10505 if (error) {
10506 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10507 "1476 Failed to allocate sysfs attr\n");
10508 goto out_destroy_shost;
10509 }
10510
10511 shost = lpfc_shost_from_vport(vport);
10512
10513 cfg_mode = phba->cfg_use_msi;
10514 while (true) {
10515
10516 lpfc_stop_port(phba);
10517
10518 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
10519 if (intr_mode == LPFC_INTR_ERROR) {
10520 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10521 "0431 Failed to enable interrupt.\n");
10522 error = -ENODEV;
10523 goto out_free_sysfs_attr;
10524 }
10525
10526 if (lpfc_sli_hba_setup(phba)) {
10527 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10528 "1477 Failed to set up hba\n");
10529 error = -ENODEV;
10530 goto out_remove_device;
10531 }
10532
10533
10534 msleep(50);
10535
10536 if (intr_mode == 0 ||
10537 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
10538
10539 phba->intr_mode = intr_mode;
10540 lpfc_log_intr_mode(phba, intr_mode);
10541 break;
10542 } else {
10543 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10544 "0447 Configure interrupt mode (%d) "
10545 "failed active interrupt test.\n",
10546 intr_mode);
10547
10548 lpfc_sli_disable_intr(phba);
10549
10550 cfg_mode = --intr_mode;
10551 }
10552 }
10553
10554
10555 lpfc_post_init_setup(phba);
10556
10557
10558 lpfc_create_static_vport(phba);
10559
10560 return 0;
10561
10562out_remove_device:
10563 lpfc_unset_hba(phba);
10564out_free_sysfs_attr:
10565 lpfc_free_sysfs_attr(vport);
10566out_destroy_shost:
10567 lpfc_destroy_shost(phba);
10568out_unset_driver_resource:
10569 lpfc_unset_driver_resource_phase2(phba);
10570out_free_iocb_list:
10571 lpfc_free_iocb_list(phba);
10572out_unset_driver_resource_s3:
10573 lpfc_sli_driver_resource_unset(phba);
10574out_unset_pci_mem_s3:
10575 lpfc_sli_pci_mem_unset(phba);
10576out_disable_pci_dev:
10577 lpfc_disable_pci_dev(phba);
10578 if (shost)
10579 scsi_host_put(shost);
10580out_free_phba:
10581 lpfc_hba_free(phba);
10582 return error;
10583}
10584
10585
10586
10587
10588
10589
10590
10591
10592
10593
10594static void
10595lpfc_pci_remove_one_s3(struct pci_dev *pdev)
10596{
10597 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10598 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
10599 struct lpfc_vport **vports;
10600 struct lpfc_hba *phba = vport->phba;
10601 int i;
10602
10603 spin_lock_irq(&phba->hbalock);
10604 vport->load_flag |= FC_UNLOADING;
10605 spin_unlock_irq(&phba->hbalock);
10606
10607 lpfc_free_sysfs_attr(vport);
10608
10609
10610 vports = lpfc_create_vport_work_array(phba);
10611 if (vports != NULL)
10612 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
10613 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
10614 continue;
10615 fc_vport_terminate(vports[i]->fc_vport);
10616 }
10617 lpfc_destroy_vport_work_array(phba, vports);
10618
10619
10620 fc_remove_host(shost);
10621 scsi_remove_host(shost);
10622
10623 lpfc_cleanup(vport);
10624
10625
10626
10627
10628
10629
10630
10631
10632 lpfc_sli_hba_down(phba);
10633
10634 kthread_stop(phba->worker_thread);
10635
10636 lpfc_sli_brdrestart(phba);
10637
10638 kfree(phba->vpi_bmask);
10639 kfree(phba->vpi_ids);
10640
10641 lpfc_stop_hba_timers(phba);
10642 spin_lock_irq(&phba->hbalock);
10643 list_del_init(&vport->listentry);
10644 spin_unlock_irq(&phba->hbalock);
10645
10646 lpfc_debugfs_terminate(vport);
10647
10648
10649 if (phba->cfg_sriov_nr_virtfn)
10650 pci_disable_sriov(pdev);
10651
10652
10653 lpfc_sli_disable_intr(phba);
10654
10655 scsi_host_put(shost);
10656
10657
10658
10659
10660
10661 lpfc_scsi_free(phba);
10662 lpfc_mem_free_all(phba);
10663
10664 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
10665 phba->hbqslimp.virt, phba->hbqslimp.phys);
10666
10667
10668 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
10669 phba->slim2p.virt, phba->slim2p.phys);
10670
10671
10672 iounmap(phba->ctrl_regs_memmap_p);
10673 iounmap(phba->slim_memmap_p);
10674
10675 lpfc_hba_free(phba);
10676
10677 pci_release_mem_regions(pdev);
10678 pci_disable_device(pdev);
10679}
10680
10681
10682
10683
10684
10685
10686
10687
10688
10689
10690
10691
10692
10693
10694
10695
10696
10697
10698
10699
10700
10701
10702static int
10703lpfc_pci_suspend_one_s3(struct pci_dev *pdev, pm_message_t msg)
10704{
10705 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10706 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10707
10708 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10709 "0473 PCI device Power Management suspend.\n");
10710
10711
10712 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
10713 lpfc_offline(phba);
10714 kthread_stop(phba->worker_thread);
10715
10716
10717 lpfc_sli_disable_intr(phba);
10718
10719
10720 pci_save_state(pdev);
10721 pci_set_power_state(pdev, PCI_D3hot);
10722
10723 return 0;
10724}
10725
10726
10727
10728
10729
10730
10731
10732
10733
10734
10735
10736
10737
10738
10739
10740
10741
10742
10743
10744
10745static int
10746lpfc_pci_resume_one_s3(struct pci_dev *pdev)
10747{
10748 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10749 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10750 uint32_t intr_mode;
10751 int error;
10752
10753 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10754 "0452 PCI device Power Management resume.\n");
10755
10756
10757 pci_set_power_state(pdev, PCI_D0);
10758 pci_restore_state(pdev);
10759
10760
10761
10762
10763
10764 pci_save_state(pdev);
10765
10766 if (pdev->is_busmaster)
10767 pci_set_master(pdev);
10768
10769
10770 phba->worker_thread = kthread_run(lpfc_do_work, phba,
10771 "lpfc_worker_%d", phba->brd_no);
10772 if (IS_ERR(phba->worker_thread)) {
10773 error = PTR_ERR(phba->worker_thread);
10774 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10775 "0434 PM resume failed to start worker "
10776 "thread: error=x%x.\n", error);
10777 return error;
10778 }
10779
10780
10781 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
10782 if (intr_mode == LPFC_INTR_ERROR) {
10783 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10784 "0430 PM resume Failed to enable interrupt\n");
10785 return -EIO;
10786 } else
10787 phba->intr_mode = intr_mode;
10788
10789
10790 lpfc_sli_brdrestart(phba);
10791 lpfc_online(phba);
10792
10793
10794 lpfc_log_intr_mode(phba, phba->intr_mode);
10795
10796 return 0;
10797}
10798
10799
10800
10801
10802
10803
10804
10805
10806static void
10807lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
10808{
10809 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10810 "2723 PCI channel I/O abort preparing for recovery\n");
10811
10812
10813
10814
10815
10816 lpfc_sli_abort_fcp_rings(phba);
10817}
10818
10819
10820
10821
10822
10823
10824
10825
10826
10827static void
10828lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
10829{
10830 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10831 "2710 PCI channel disable preparing for reset\n");
10832
10833
10834 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
10835
10836
10837 lpfc_scsi_dev_block(phba);
10838
10839
10840 lpfc_sli_flush_fcp_rings(phba);
10841
10842
10843 lpfc_stop_hba_timers(phba);
10844
10845
10846 lpfc_sli_disable_intr(phba);
10847 pci_disable_device(phba->pcidev);
10848}
10849
10850
10851
10852
10853
10854
10855
10856
10857
10858static void
10859lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
10860{
10861 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10862 "2711 PCI channel permanent disable for failure\n");
10863
10864 lpfc_scsi_dev_block(phba);
10865
10866
10867 lpfc_stop_hba_timers(phba);
10868
10869
10870 lpfc_sli_flush_fcp_rings(phba);
10871}
10872
10873
10874
10875
10876
10877
10878
10879
10880
10881
10882
10883
10884
10885
10886
10887
10888
10889
10890
10891static pci_ers_result_t
10892lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
10893{
10894 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10895 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10896
10897 switch (state) {
10898 case pci_channel_io_normal:
10899
10900 lpfc_sli_prep_dev_for_recover(phba);
10901 return PCI_ERS_RESULT_CAN_RECOVER;
10902 case pci_channel_io_frozen:
10903
10904 lpfc_sli_prep_dev_for_reset(phba);
10905 return PCI_ERS_RESULT_NEED_RESET;
10906 case pci_channel_io_perm_failure:
10907
10908 lpfc_sli_prep_dev_for_perm_failure(phba);
10909 return PCI_ERS_RESULT_DISCONNECT;
10910 default:
10911
10912 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10913 "0472 Unknown PCI error state: x%x\n", state);
10914 lpfc_sli_prep_dev_for_reset(phba);
10915 return PCI_ERS_RESULT_NEED_RESET;
10916 }
10917}
10918
10919
10920
10921
10922
10923
10924
10925
10926
10927
10928
10929
10930
10931
10932
10933
10934
10935
10936
10937static pci_ers_result_t
10938lpfc_io_slot_reset_s3(struct pci_dev *pdev)
10939{
10940 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10941 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10942 struct lpfc_sli *psli = &phba->sli;
10943 uint32_t intr_mode;
10944
10945 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
10946 if (pci_enable_device_mem(pdev)) {
10947 printk(KERN_ERR "lpfc: Cannot re-enable "
10948 "PCI device after reset.\n");
10949 return PCI_ERS_RESULT_DISCONNECT;
10950 }
10951
10952 pci_restore_state(pdev);
10953
10954
10955
10956
10957
10958 pci_save_state(pdev);
10959
10960 if (pdev->is_busmaster)
10961 pci_set_master(pdev);
10962
10963 spin_lock_irq(&phba->hbalock);
10964 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
10965 spin_unlock_irq(&phba->hbalock);
10966
10967
10968 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
10969 if (intr_mode == LPFC_INTR_ERROR) {
10970 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10971 "0427 Cannot re-enable interrupt after "
10972 "slot reset.\n");
10973 return PCI_ERS_RESULT_DISCONNECT;
10974 } else
10975 phba->intr_mode = intr_mode;
10976
10977
10978 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
10979 lpfc_offline(phba);
10980 lpfc_sli_brdrestart(phba);
10981
10982
10983 lpfc_log_intr_mode(phba, phba->intr_mode);
10984
10985 return PCI_ERS_RESULT_RECOVERED;
10986}
10987
10988
10989
10990
10991
10992
10993
10994
10995
10996
10997
10998static void
10999lpfc_io_resume_s3(struct pci_dev *pdev)
11000{
11001 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11002 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11003
11004
11005 lpfc_online(phba);
11006
11007
11008 if (phba->hba_flag & HBA_AER_ENABLED)
11009 pci_cleanup_aer_uncorrect_error_status(pdev);
11010}
11011
11012
11013
11014
11015
11016
11017
11018int
11019lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
11020{
11021 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
11022
11023 if (phba->sli_rev == LPFC_SLI_REV4) {
11024 if (max_xri <= 100)
11025 return 10;
11026 else if (max_xri <= 256)
11027 return 25;
11028 else if (max_xri <= 512)
11029 return 50;
11030 else if (max_xri <= 1024)
11031 return 100;
11032 else if (max_xri <= 1536)
11033 return 150;
11034 else if (max_xri <= 2048)
11035 return 200;
11036 else
11037 return 250;
11038 } else
11039 return 0;
11040}
11041
11042
11043
11044
11045
11046
11047
11048int
11049lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba)
11050{
11051 int max_xri = lpfc_sli4_get_els_iocb_cnt(phba);
11052
11053 if (phba->nvmet_support)
11054 max_xri += LPFC_NVMET_BUF_POST;
11055 return max_xri;
11056}
11057
11058
11059
11060
11061
11062
11063
11064
11065static void
11066lpfc_write_firmware(const struct firmware *fw, void *context)
11067{
11068 struct lpfc_hba *phba = (struct lpfc_hba *)context;
11069 char fwrev[FW_REV_STR_SIZE];
11070 struct lpfc_grp_hdr *image;
11071 struct list_head dma_buffer_list;
11072 int i, rc = 0;
11073 struct lpfc_dmabuf *dmabuf, *next;
11074 uint32_t offset = 0, temp_offset = 0;
11075 uint32_t magic_number, ftype, fid, fsize;
11076
11077
11078 if (!fw) {
11079 rc = -ENXIO;
11080 goto out;
11081 }
11082 image = (struct lpfc_grp_hdr *)fw->data;
11083
11084 magic_number = be32_to_cpu(image->magic_number);
11085 ftype = bf_get_be32(lpfc_grp_hdr_file_type, image);
11086 fid = bf_get_be32(lpfc_grp_hdr_id, image),
11087 fsize = be32_to_cpu(image->size);
11088
11089 INIT_LIST_HEAD(&dma_buffer_list);
11090 if ((magic_number != LPFC_GROUP_OJECT_MAGIC_G5 &&
11091 magic_number != LPFC_GROUP_OJECT_MAGIC_G6) ||
11092 ftype != LPFC_FILE_TYPE_GROUP || fsize != fw->size) {
11093 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11094 "3022 Invalid FW image found. "
11095 "Magic:%x Type:%x ID:%x Size %d %zd\n",
11096 magic_number, ftype, fid, fsize, fw->size);
11097 rc = -EINVAL;
11098 goto release_out;
11099 }
11100 lpfc_decode_firmware_rev(phba, fwrev, 1);
11101 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
11102 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11103 "3023 Updating Firmware, Current Version:%s "
11104 "New Version:%s\n",
11105 fwrev, image->revision);
11106 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
11107 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
11108 GFP_KERNEL);
11109 if (!dmabuf) {
11110 rc = -ENOMEM;
11111 goto release_out;
11112 }
11113 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
11114 SLI4_PAGE_SIZE,
11115 &dmabuf->phys,
11116 GFP_KERNEL);
11117 if (!dmabuf->virt) {
11118 kfree(dmabuf);
11119 rc = -ENOMEM;
11120 goto release_out;
11121 }
11122 list_add_tail(&dmabuf->list, &dma_buffer_list);
11123 }
11124 while (offset < fw->size) {
11125 temp_offset = offset;
11126 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
11127 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
11128 memcpy(dmabuf->virt,
11129 fw->data + temp_offset,
11130 fw->size - temp_offset);
11131 temp_offset = fw->size;
11132 break;
11133 }
11134 memcpy(dmabuf->virt, fw->data + temp_offset,
11135 SLI4_PAGE_SIZE);
11136 temp_offset += SLI4_PAGE_SIZE;
11137 }
11138 rc = lpfc_wr_object(phba, &dma_buffer_list,
11139 (fw->size - offset), &offset);
11140 if (rc)
11141 goto release_out;
11142 }
11143 rc = offset;
11144 }
11145
11146release_out:
11147 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
11148 list_del(&dmabuf->list);
11149 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
11150 dmabuf->virt, dmabuf->phys);
11151 kfree(dmabuf);
11152 }
11153 release_firmware(fw);
11154out:
11155 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11156 "3024 Firmware update done: %d.\n", rc);
11157 return;
11158}
11159
11160
11161
11162
11163
11164
11165
11166
11167int
11168lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
11169{
11170 uint8_t file_name[ELX_MODEL_NAME_SIZE];
11171 int ret;
11172 const struct firmware *fw;
11173
11174
11175 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
11176 LPFC_SLI_INTF_IF_TYPE_2)
11177 return -EPERM;
11178
11179 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
11180
11181 if (fw_upgrade == INT_FW_UPGRADE) {
11182 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
11183 file_name, &phba->pcidev->dev,
11184 GFP_KERNEL, (void *)phba,
11185 lpfc_write_firmware);
11186 } else if (fw_upgrade == RUN_FW_UPGRADE) {
11187 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
11188 if (!ret)
11189 lpfc_write_firmware(fw, (void *)phba);
11190 } else {
11191 ret = -EINVAL;
11192 }
11193
11194 return ret;
11195}
11196
11197
11198
11199
11200
11201
11202
11203
11204
11205
11206
11207
11208
11209
11210
11211
11212
11213
11214
11215static int
11216lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
11217{
11218 struct lpfc_hba *phba;
11219 struct lpfc_vport *vport = NULL;
11220 struct Scsi_Host *shost = NULL;
11221 int error;
11222 uint32_t cfg_mode, intr_mode;
11223
11224
11225 phba = lpfc_hba_alloc(pdev);
11226 if (!phba)
11227 return -ENOMEM;
11228
11229
11230 error = lpfc_enable_pci_dev(phba);
11231 if (error)
11232 goto out_free_phba;
11233
11234
11235 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
11236 if (error)
11237 goto out_disable_pci_dev;
11238
11239
11240 error = lpfc_sli4_pci_mem_setup(phba);
11241 if (error) {
11242 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11243 "1410 Failed to set up pci memory space.\n");
11244 goto out_disable_pci_dev;
11245 }
11246
11247
11248 error = lpfc_sli4_driver_resource_setup(phba);
11249 if (error) {
11250 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11251 "1412 Failed to set up driver resource.\n");
11252 goto out_unset_pci_mem_s4;
11253 }
11254
11255 INIT_LIST_HEAD(&phba->active_rrq_list);
11256 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
11257
11258
11259 error = lpfc_setup_driver_resource_phase2(phba);
11260 if (error) {
11261 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11262 "1414 Failed to set up driver resource.\n");
11263 goto out_unset_driver_resource_s4;
11264 }
11265
11266
11267 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
11268
11269
11270 error = lpfc_create_shost(phba);
11271 if (error) {
11272 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11273 "1415 Failed to create scsi host.\n");
11274 goto out_unset_driver_resource;
11275 }
11276
11277
11278 vport = phba->pport;
11279 error = lpfc_alloc_sysfs_attr(vport);
11280 if (error) {
11281 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11282 "1416 Failed to allocate sysfs attr\n");
11283 goto out_destroy_shost;
11284 }
11285
11286 shost = lpfc_shost_from_vport(vport);
11287
11288 cfg_mode = phba->cfg_use_msi;
11289
11290
11291 lpfc_stop_port(phba);
11292
11293
11294 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
11295 if (intr_mode == LPFC_INTR_ERROR) {
11296 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11297 "0426 Failed to enable interrupt.\n");
11298 error = -ENODEV;
11299 goto out_free_sysfs_attr;
11300 }
11301
11302 if (phba->intr_type != MSIX) {
11303 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP)
11304 phba->cfg_fcp_io_channel = 1;
11305 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
11306 phba->cfg_nvme_io_channel = 1;
11307 if (phba->nvmet_support)
11308 phba->cfg_nvmet_mrq = 1;
11309 }
11310 phba->io_channel_irqs = 1;
11311 }
11312
11313
11314 if (lpfc_sli4_hba_setup(phba)) {
11315 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11316 "1421 Failed to set up hba\n");
11317 error = -ENODEV;
11318 goto out_disable_intr;
11319 }
11320
11321
11322 phba->intr_mode = intr_mode;
11323 lpfc_log_intr_mode(phba, intr_mode);
11324
11325
11326 lpfc_post_init_setup(phba);
11327
11328
11329
11330
11331 if ((phba->nvmet_support == 0) &&
11332 (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)) {
11333
11334
11335
11336
11337
11338 error = lpfc_nvme_create_localport(vport);
11339 if (error) {
11340 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11341 "6004 NVME registration failed, "
11342 "error x%x\n",
11343 error);
11344 }
11345 }
11346
11347
11348 if (phba->cfg_request_firmware_upgrade)
11349 lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
11350
11351
11352 lpfc_create_static_vport(phba);
11353 return 0;
11354
11355out_disable_intr:
11356 lpfc_sli4_disable_intr(phba);
11357out_free_sysfs_attr:
11358 lpfc_free_sysfs_attr(vport);
11359out_destroy_shost:
11360 lpfc_destroy_shost(phba);
11361out_unset_driver_resource:
11362 lpfc_unset_driver_resource_phase2(phba);
11363out_unset_driver_resource_s4:
11364 lpfc_sli4_driver_resource_unset(phba);
11365out_unset_pci_mem_s4:
11366 lpfc_sli4_pci_mem_unset(phba);
11367out_disable_pci_dev:
11368 lpfc_disable_pci_dev(phba);
11369 if (shost)
11370 scsi_host_put(shost);
11371out_free_phba:
11372 lpfc_hba_free(phba);
11373 return error;
11374}
11375
11376
11377
11378
11379
11380
11381
11382
11383
11384
11385static void
11386lpfc_pci_remove_one_s4(struct pci_dev *pdev)
11387{
11388 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11389 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
11390 struct lpfc_vport **vports;
11391 struct lpfc_hba *phba = vport->phba;
11392 int i;
11393
11394
11395 spin_lock_irq(&phba->hbalock);
11396 vport->load_flag |= FC_UNLOADING;
11397 spin_unlock_irq(&phba->hbalock);
11398
11399
11400 lpfc_free_sysfs_attr(vport);
11401
11402
11403 vports = lpfc_create_vport_work_array(phba);
11404 if (vports != NULL)
11405 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
11406 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
11407 continue;
11408 fc_vport_terminate(vports[i]->fc_vport);
11409 }
11410 lpfc_destroy_vport_work_array(phba, vports);
11411
11412
11413 fc_remove_host(shost);
11414 scsi_remove_host(shost);
11415
11416
11417
11418
11419
11420 lpfc_debugfs_terminate(vport);
11421 lpfc_sli4_hba_unset(phba);
11422
11423
11424
11425
11426 lpfc_cleanup(vport);
11427 lpfc_nvmet_destroy_targetport(phba);
11428 lpfc_nvme_destroy_localport(vport);
11429
11430
11431 lpfc_stop_hba_timers(phba);
11432 spin_lock_irq(&phba->hbalock);
11433 list_del_init(&vport->listentry);
11434 spin_unlock_irq(&phba->hbalock);
11435
11436
11437
11438
11439 lpfc_scsi_free(phba);
11440 lpfc_nvme_free(phba);
11441 lpfc_free_iocb_list(phba);
11442
11443 lpfc_sli4_driver_resource_unset(phba);
11444
11445
11446 lpfc_sli4_pci_mem_unset(phba);
11447
11448
11449 scsi_host_put(shost);
11450 lpfc_disable_pci_dev(phba);
11451
11452
11453 lpfc_hba_free(phba);
11454
11455 return;
11456}
11457
11458
11459
11460
11461
11462
11463
11464
11465
11466
11467
11468
11469
11470
11471
11472
11473
11474
11475
11476
11477
11478
11479static int
11480lpfc_pci_suspend_one_s4(struct pci_dev *pdev, pm_message_t msg)
11481{
11482 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11483 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11484
11485 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11486 "2843 PCI device Power Management suspend.\n");
11487
11488
11489 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
11490 lpfc_offline(phba);
11491 kthread_stop(phba->worker_thread);
11492
11493
11494 lpfc_sli4_disable_intr(phba);
11495 lpfc_sli4_queue_destroy(phba);
11496
11497
11498 pci_save_state(pdev);
11499 pci_set_power_state(pdev, PCI_D3hot);
11500
11501 return 0;
11502}
11503
11504
11505
11506
11507
11508
11509
11510
11511
11512
11513
11514
11515
11516
11517
11518
11519
11520
11521
11522
11523static int
11524lpfc_pci_resume_one_s4(struct pci_dev *pdev)
11525{
11526 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11527 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11528 uint32_t intr_mode;
11529 int error;
11530
11531 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11532 "0292 PCI device Power Management resume.\n");
11533
11534
11535 pci_set_power_state(pdev, PCI_D0);
11536 pci_restore_state(pdev);
11537
11538
11539
11540
11541
11542 pci_save_state(pdev);
11543
11544 if (pdev->is_busmaster)
11545 pci_set_master(pdev);
11546
11547
11548 phba->worker_thread = kthread_run(lpfc_do_work, phba,
11549 "lpfc_worker_%d", phba->brd_no);
11550 if (IS_ERR(phba->worker_thread)) {
11551 error = PTR_ERR(phba->worker_thread);
11552 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11553 "0293 PM resume failed to start worker "
11554 "thread: error=x%x.\n", error);
11555 return error;
11556 }
11557
11558
11559 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
11560 if (intr_mode == LPFC_INTR_ERROR) {
11561 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11562 "0294 PM resume Failed to enable interrupt\n");
11563 return -EIO;
11564 } else
11565 phba->intr_mode = intr_mode;
11566
11567
11568 lpfc_sli_brdrestart(phba);
11569 lpfc_online(phba);
11570
11571
11572 lpfc_log_intr_mode(phba, phba->intr_mode);
11573
11574 return 0;
11575}
11576
11577
11578
11579
11580
11581
11582
11583
11584static void
11585lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
11586{
11587 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11588 "2828 PCI channel I/O abort preparing for recovery\n");
11589
11590
11591
11592
11593 lpfc_sli_abort_fcp_rings(phba);
11594}
11595
11596
11597
11598
11599
11600
11601
11602
11603
11604static void
11605lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
11606{
11607 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11608 "2826 PCI channel disable preparing for reset\n");
11609
11610
11611 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
11612
11613
11614 lpfc_scsi_dev_block(phba);
11615
11616
11617 lpfc_sli_flush_fcp_rings(phba);
11618
11619
11620 lpfc_stop_hba_timers(phba);
11621
11622
11623 lpfc_sli4_disable_intr(phba);
11624 lpfc_sli4_queue_destroy(phba);
11625 pci_disable_device(phba->pcidev);
11626}
11627
11628
11629
11630
11631
11632
11633
11634
11635
11636static void
11637lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
11638{
11639 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11640 "2827 PCI channel permanent disable for failure\n");
11641
11642
11643 lpfc_scsi_dev_block(phba);
11644
11645
11646 lpfc_stop_hba_timers(phba);
11647
11648
11649 lpfc_sli_flush_fcp_rings(phba);
11650}
11651
11652
11653
11654
11655
11656
11657
11658
11659
11660
11661
11662
11663
11664
11665
11666
11667
11668static pci_ers_result_t
11669lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
11670{
11671 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11672 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11673
11674 switch (state) {
11675 case pci_channel_io_normal:
11676
11677 lpfc_sli4_prep_dev_for_recover(phba);
11678 return PCI_ERS_RESULT_CAN_RECOVER;
11679 case pci_channel_io_frozen:
11680
11681 lpfc_sli4_prep_dev_for_reset(phba);
11682 return PCI_ERS_RESULT_NEED_RESET;
11683 case pci_channel_io_perm_failure:
11684
11685 lpfc_sli4_prep_dev_for_perm_failure(phba);
11686 return PCI_ERS_RESULT_DISCONNECT;
11687 default:
11688
11689 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11690 "2825 Unknown PCI error state: x%x\n", state);
11691 lpfc_sli4_prep_dev_for_reset(phba);
11692 return PCI_ERS_RESULT_NEED_RESET;
11693 }
11694}
11695
11696
11697
11698
11699
11700
11701
11702
11703
11704
11705
11706
11707
11708
11709
11710
11711
11712
11713
11714static pci_ers_result_t
11715lpfc_io_slot_reset_s4(struct pci_dev *pdev)
11716{
11717 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11718 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11719 struct lpfc_sli *psli = &phba->sli;
11720 uint32_t intr_mode;
11721
11722 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
11723 if (pci_enable_device_mem(pdev)) {
11724 printk(KERN_ERR "lpfc: Cannot re-enable "
11725 "PCI device after reset.\n");
11726 return PCI_ERS_RESULT_DISCONNECT;
11727 }
11728
11729 pci_restore_state(pdev);
11730
11731
11732
11733
11734
11735 pci_save_state(pdev);
11736
11737 if (pdev->is_busmaster)
11738 pci_set_master(pdev);
11739
11740 spin_lock_irq(&phba->hbalock);
11741 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
11742 spin_unlock_irq(&phba->hbalock);
11743
11744
11745 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
11746 if (intr_mode == LPFC_INTR_ERROR) {
11747 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11748 "2824 Cannot re-enable interrupt after "
11749 "slot reset.\n");
11750 return PCI_ERS_RESULT_DISCONNECT;
11751 } else
11752 phba->intr_mode = intr_mode;
11753
11754
11755 lpfc_log_intr_mode(phba, phba->intr_mode);
11756
11757 return PCI_ERS_RESULT_RECOVERED;
11758}
11759
11760
11761
11762
11763
11764
11765
11766
11767
11768
11769
11770static void
11771lpfc_io_resume_s4(struct pci_dev *pdev)
11772{
11773 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11774 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11775
11776
11777
11778
11779
11780
11781
11782 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
11783
11784 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
11785 lpfc_offline(phba);
11786 lpfc_sli_brdrestart(phba);
11787
11788 lpfc_online(phba);
11789 }
11790
11791
11792 if (phba->hba_flag & HBA_AER_ENABLED)
11793 pci_cleanup_aer_uncorrect_error_status(pdev);
11794}
11795
11796
11797
11798
11799
11800
11801
11802
11803
11804
11805
11806
11807
11808
11809
11810
11811
11812
11813
11814static int
11815lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
11816{
11817 int rc;
11818 struct lpfc_sli_intf intf;
11819
11820 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
11821 return -ENODEV;
11822
11823 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
11824 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
11825 rc = lpfc_pci_probe_one_s4(pdev, pid);
11826 else
11827 rc = lpfc_pci_probe_one_s3(pdev, pid);
11828
11829 return rc;
11830}
11831
11832
11833
11834
11835
11836
11837
11838
11839
11840
11841
11842static void
11843lpfc_pci_remove_one(struct pci_dev *pdev)
11844{
11845 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11846 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11847
11848 switch (phba->pci_dev_grp) {
11849 case LPFC_PCI_DEV_LP:
11850 lpfc_pci_remove_one_s3(pdev);
11851 break;
11852 case LPFC_PCI_DEV_OC:
11853 lpfc_pci_remove_one_s4(pdev);
11854 break;
11855 default:
11856 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11857 "1424 Invalid PCI device group: 0x%x\n",
11858 phba->pci_dev_grp);
11859 break;
11860 }
11861 return;
11862}
11863
11864
11865
11866
11867
11868
11869
11870
11871
11872
11873
11874
11875
11876
11877
11878static int
11879lpfc_pci_suspend_one(struct pci_dev *pdev, pm_message_t msg)
11880{
11881 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11882 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11883 int rc = -ENODEV;
11884
11885 switch (phba->pci_dev_grp) {
11886 case LPFC_PCI_DEV_LP:
11887 rc = lpfc_pci_suspend_one_s3(pdev, msg);
11888 break;
11889 case LPFC_PCI_DEV_OC:
11890 rc = lpfc_pci_suspend_one_s4(pdev, msg);
11891 break;
11892 default:
11893 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11894 "1425 Invalid PCI device group: 0x%x\n",
11895 phba->pci_dev_grp);
11896 break;
11897 }
11898 return rc;
11899}
11900
11901
11902
11903
11904
11905
11906
11907
11908
11909
11910
11911
11912
11913
11914static int
11915lpfc_pci_resume_one(struct pci_dev *pdev)
11916{
11917 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11918 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11919 int rc = -ENODEV;
11920
11921 switch (phba->pci_dev_grp) {
11922 case LPFC_PCI_DEV_LP:
11923 rc = lpfc_pci_resume_one_s3(pdev);
11924 break;
11925 case LPFC_PCI_DEV_OC:
11926 rc = lpfc_pci_resume_one_s4(pdev);
11927 break;
11928 default:
11929 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11930 "1426 Invalid PCI device group: 0x%x\n",
11931 phba->pci_dev_grp);
11932 break;
11933 }
11934 return rc;
11935}
11936
11937
11938
11939
11940
11941
11942
11943
11944
11945
11946
11947
11948
11949
11950
11951
11952static pci_ers_result_t
11953lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
11954{
11955 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11956 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11957 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
11958
11959 switch (phba->pci_dev_grp) {
11960 case LPFC_PCI_DEV_LP:
11961 rc = lpfc_io_error_detected_s3(pdev, state);
11962 break;
11963 case LPFC_PCI_DEV_OC:
11964 rc = lpfc_io_error_detected_s4(pdev, state);
11965 break;
11966 default:
11967 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11968 "1427 Invalid PCI device group: 0x%x\n",
11969 phba->pci_dev_grp);
11970 break;
11971 }
11972 return rc;
11973}
11974
11975
11976
11977
11978
11979
11980
11981
11982
11983
11984
11985
11986
11987
11988
11989static pci_ers_result_t
11990lpfc_io_slot_reset(struct pci_dev *pdev)
11991{
11992 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11993 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11994 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
11995
11996 switch (phba->pci_dev_grp) {
11997 case LPFC_PCI_DEV_LP:
11998 rc = lpfc_io_slot_reset_s3(pdev);
11999 break;
12000 case LPFC_PCI_DEV_OC:
12001 rc = lpfc_io_slot_reset_s4(pdev);
12002 break;
12003 default:
12004 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12005 "1428 Invalid PCI device group: 0x%x\n",
12006 phba->pci_dev_grp);
12007 break;
12008 }
12009 return rc;
12010}
12011
12012
12013
12014
12015
12016
12017
12018
12019
12020
12021
12022static void
12023lpfc_io_resume(struct pci_dev *pdev)
12024{
12025 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12026 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12027
12028 switch (phba->pci_dev_grp) {
12029 case LPFC_PCI_DEV_LP:
12030 lpfc_io_resume_s3(pdev);
12031 break;
12032 case LPFC_PCI_DEV_OC:
12033 lpfc_io_resume_s4(pdev);
12034 break;
12035 default:
12036 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12037 "1429 Invalid PCI device group: 0x%x\n",
12038 phba->pci_dev_grp);
12039 break;
12040 }
12041 return;
12042}
12043
12044
12045
12046
12047
12048
12049
12050
12051
12052
12053
12054void
12055lpfc_sli4_oas_verify(struct lpfc_hba *phba)
12056{
12057
12058 if (!phba->cfg_EnableXLane)
12059 return;
12060
12061 if (phba->sli4_hba.pc_sli4_params.oas_supported) {
12062 phba->cfg_fof = 1;
12063 } else {
12064 phba->cfg_fof = 0;
12065 if (phba->device_data_mem_pool)
12066 mempool_destroy(phba->device_data_mem_pool);
12067 phba->device_data_mem_pool = NULL;
12068 }
12069
12070 return;
12071}
12072
12073
12074
12075
12076
12077
12078
12079
12080
12081
12082
12083
12084int
12085lpfc_fof_queue_setup(struct lpfc_hba *phba)
12086{
12087 struct lpfc_sli_ring *pring;
12088 int rc;
12089
12090 rc = lpfc_eq_create(phba, phba->sli4_hba.fof_eq, LPFC_MAX_IMAX);
12091 if (rc)
12092 return -ENOMEM;
12093
12094 if (phba->cfg_fof) {
12095
12096 rc = lpfc_cq_create(phba, phba->sli4_hba.oas_cq,
12097 phba->sli4_hba.fof_eq, LPFC_WCQ, LPFC_FCP);
12098 if (rc)
12099 goto out_oas_cq;
12100
12101 rc = lpfc_wq_create(phba, phba->sli4_hba.oas_wq,
12102 phba->sli4_hba.oas_cq, LPFC_FCP);
12103 if (rc)
12104 goto out_oas_wq;
12105
12106
12107 pring = phba->sli4_hba.oas_wq->pring;
12108 pring->sli.sli4.wqp =
12109 (void *)phba->sli4_hba.oas_wq;
12110 phba->sli4_hba.oas_cq->pring = pring;
12111 }
12112
12113 return 0;
12114
12115out_oas_wq:
12116 lpfc_cq_destroy(phba, phba->sli4_hba.oas_cq);
12117out_oas_cq:
12118 lpfc_eq_destroy(phba, phba->sli4_hba.fof_eq);
12119 return rc;
12120
12121}
12122
12123
12124
12125
12126
12127
12128
12129
12130
12131
12132
12133
12134
12135
12136
12137int
12138lpfc_fof_queue_create(struct lpfc_hba *phba)
12139{
12140 struct lpfc_queue *qdesc;
12141 uint32_t wqesize;
12142
12143
12144 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.eq_esize,
12145 phba->sli4_hba.eq_ecount);
12146 if (!qdesc)
12147 goto out_error;
12148
12149 phba->sli4_hba.fof_eq = qdesc;
12150
12151 if (phba->cfg_fof) {
12152
12153
12154 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
12155 phba->sli4_hba.cq_ecount);
12156 if (!qdesc)
12157 goto out_error;
12158
12159 phba->sli4_hba.oas_cq = qdesc;
12160
12161
12162 wqesize = (phba->fcp_embed_io) ?
12163 LPFC_WQE128_SIZE : phba->sli4_hba.wq_esize;
12164 qdesc = lpfc_sli4_queue_alloc(phba, wqesize,
12165 phba->sli4_hba.wq_ecount);
12166
12167 if (!qdesc)
12168 goto out_error;
12169
12170 phba->sli4_hba.oas_wq = qdesc;
12171 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
12172
12173 }
12174 return 0;
12175
12176out_error:
12177 lpfc_fof_queue_destroy(phba);
12178 return -ENOMEM;
12179}
12180
12181
12182
12183
12184
12185
12186
12187
12188
12189
12190
12191int
12192lpfc_fof_queue_destroy(struct lpfc_hba *phba)
12193{
12194
12195 if (phba->sli4_hba.fof_eq != NULL) {
12196 lpfc_sli4_queue_free(phba->sli4_hba.fof_eq);
12197 phba->sli4_hba.fof_eq = NULL;
12198 }
12199
12200
12201 if (phba->sli4_hba.oas_cq != NULL) {
12202 lpfc_sli4_queue_free(phba->sli4_hba.oas_cq);
12203 phba->sli4_hba.oas_cq = NULL;
12204 }
12205
12206
12207 if (phba->sli4_hba.oas_wq != NULL) {
12208 lpfc_sli4_queue_free(phba->sli4_hba.oas_wq);
12209 phba->sli4_hba.oas_wq = NULL;
12210 }
12211 return 0;
12212}
12213
12214MODULE_DEVICE_TABLE(pci, lpfc_id_table);
12215
12216static const struct pci_error_handlers lpfc_err_handler = {
12217 .error_detected = lpfc_io_error_detected,
12218 .slot_reset = lpfc_io_slot_reset,
12219 .resume = lpfc_io_resume,
12220};
12221
12222static struct pci_driver lpfc_driver = {
12223 .name = LPFC_DRIVER_NAME,
12224 .id_table = lpfc_id_table,
12225 .probe = lpfc_pci_probe_one,
12226 .remove = lpfc_pci_remove_one,
12227 .shutdown = lpfc_pci_remove_one,
12228 .suspend = lpfc_pci_suspend_one,
12229 .resume = lpfc_pci_resume_one,
12230 .err_handler = &lpfc_err_handler,
12231};
12232
12233static const struct file_operations lpfc_mgmt_fop = {
12234 .owner = THIS_MODULE,
12235};
12236
12237static struct miscdevice lpfc_mgmt_dev = {
12238 .minor = MISC_DYNAMIC_MINOR,
12239 .name = "lpfcmgmt",
12240 .fops = &lpfc_mgmt_fop,
12241};
12242
12243
12244
12245
12246
12247
12248
12249
12250
12251
12252
12253
12254
12255static int __init
12256lpfc_init(void)
12257{
12258 int error = 0;
12259
12260 printk(LPFC_MODULE_DESC "\n");
12261 printk(LPFC_COPYRIGHT "\n");
12262
12263 error = misc_register(&lpfc_mgmt_dev);
12264 if (error)
12265 printk(KERN_ERR "Could not register lpfcmgmt device, "
12266 "misc_register returned with status %d", error);
12267
12268 lpfc_transport_functions.vport_create = lpfc_vport_create;
12269 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
12270 lpfc_transport_template =
12271 fc_attach_transport(&lpfc_transport_functions);
12272 if (lpfc_transport_template == NULL)
12273 return -ENOMEM;
12274 lpfc_vport_transport_template =
12275 fc_attach_transport(&lpfc_vport_transport_functions);
12276 if (lpfc_vport_transport_template == NULL) {
12277 fc_release_transport(lpfc_transport_template);
12278 return -ENOMEM;
12279 }
12280
12281
12282 lpfc_used_cpu = NULL;
12283 lpfc_present_cpu = num_present_cpus();
12284
12285 error = pci_register_driver(&lpfc_driver);
12286 if (error) {
12287 fc_release_transport(lpfc_transport_template);
12288 fc_release_transport(lpfc_vport_transport_template);
12289 }
12290
12291 return error;
12292}
12293
12294
12295
12296
12297
12298
12299
12300
12301static void __exit
12302lpfc_exit(void)
12303{
12304 misc_deregister(&lpfc_mgmt_dev);
12305 pci_unregister_driver(&lpfc_driver);
12306 fc_release_transport(lpfc_transport_template);
12307 fc_release_transport(lpfc_vport_transport_template);
12308 if (_dump_buf_data) {
12309 printk(KERN_ERR "9062 BLKGRD: freeing %lu pages for "
12310 "_dump_buf_data at 0x%p\n",
12311 (1L << _dump_buf_data_order), _dump_buf_data);
12312 free_pages((unsigned long)_dump_buf_data, _dump_buf_data_order);
12313 }
12314
12315 if (_dump_buf_dif) {
12316 printk(KERN_ERR "9049 BLKGRD: freeing %lu pages for "
12317 "_dump_buf_dif at 0x%p\n",
12318 (1L << _dump_buf_dif_order), _dump_buf_dif);
12319 free_pages((unsigned long)_dump_buf_dif, _dump_buf_dif_order);
12320 }
12321 kfree(lpfc_used_cpu);
12322 idr_destroy(&lpfc_hba_index);
12323}
12324
12325module_init(lpfc_init);
12326module_exit(lpfc_exit);
12327MODULE_LICENSE("GPL");
12328MODULE_DESCRIPTION(LPFC_MODULE_DESC);
12329MODULE_AUTHOR("Broadcom");
12330MODULE_VERSION("0:" LPFC_DRIVER_VERSION);
12331