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7#include "qla_def.h"
8#include "qla_target.h"
9
10#include <linux/delay.h>
11#include <linux/slab.h>
12#include <linux/cpu.h>
13#include <linux/t10-pi.h>
14#include <scsi/scsi_tcq.h>
15#include <scsi/scsi_bsg_fc.h>
16#include <scsi/scsi_eh.h>
17#include <scsi/fc/fc_fs.h>
18#include <linux/nvme-fc-driver.h>
19
20static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
21static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
22static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
23static int qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
24 sts_entry_t *);
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26
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34
35irqreturn_t
36qla2100_intr_handler(int irq, void *dev_id)
37{
38 scsi_qla_host_t *vha;
39 struct qla_hw_data *ha;
40 struct device_reg_2xxx __iomem *reg;
41 int status;
42 unsigned long iter;
43 uint16_t hccr;
44 uint16_t mb[4];
45 struct rsp_que *rsp;
46 unsigned long flags;
47
48 rsp = (struct rsp_que *) dev_id;
49 if (!rsp) {
50 ql_log(ql_log_info, NULL, 0x505d,
51 "%s: NULL response queue pointer.\n", __func__);
52 return (IRQ_NONE);
53 }
54
55 ha = rsp->hw;
56 reg = &ha->iobase->isp;
57 status = 0;
58
59 spin_lock_irqsave(&ha->hardware_lock, flags);
60 vha = pci_get_drvdata(ha->pdev);
61 for (iter = 50; iter--; ) {
62 hccr = RD_REG_WORD(®->hccr);
63 if (qla2x00_check_reg16_for_disconnect(vha, hccr))
64 break;
65 if (hccr & HCCR_RISC_PAUSE) {
66 if (pci_channel_offline(ha->pdev))
67 break;
68
69
70
71
72
73
74 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
75 RD_REG_WORD(®->hccr);
76
77 ha->isp_ops->fw_dump(vha, 1);
78 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
79 break;
80 } else if ((RD_REG_WORD(®->istatus) & ISR_RISC_INT) == 0)
81 break;
82
83 if (RD_REG_WORD(®->semaphore) & BIT_0) {
84 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
85 RD_REG_WORD(®->hccr);
86
87
88 mb[0] = RD_MAILBOX_REG(ha, reg, 0);
89 if (mb[0] > 0x3fff && mb[0] < 0x8000) {
90 qla2x00_mbx_completion(vha, mb[0]);
91 status |= MBX_INTERRUPT;
92 } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
93 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
94 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
95 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
96 qla2x00_async_event(vha, rsp, mb);
97 } else {
98
99 ql_dbg(ql_dbg_async, vha, 0x5025,
100 "Unrecognized interrupt type (%d).\n",
101 mb[0]);
102 }
103
104 WRT_REG_WORD(®->semaphore, 0);
105 RD_REG_WORD(®->semaphore);
106 } else {
107 qla2x00_process_response_queue(rsp);
108
109 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
110 RD_REG_WORD(®->hccr);
111 }
112 }
113 qla2x00_handle_mbx_completion(ha, status);
114 spin_unlock_irqrestore(&ha->hardware_lock, flags);
115
116 return (IRQ_HANDLED);
117}
118
119bool
120qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *vha, uint32_t reg)
121{
122
123 if (reg == 0xffffffff && !pci_channel_offline(vha->hw->pdev)) {
124 if (!test_and_set_bit(PFLG_DISCONNECTED, &vha->pci_flags) &&
125 !test_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags) &&
126 !test_bit(PFLG_DRIVER_PROBING, &vha->pci_flags)) {
127
128
129
130
131
132 schedule_work(&vha->hw->board_disable);
133 }
134 return true;
135 } else
136 return false;
137}
138
139bool
140qla2x00_check_reg16_for_disconnect(scsi_qla_host_t *vha, uint16_t reg)
141{
142 return qla2x00_check_reg32_for_disconnect(vha, 0xffff0000 | reg);
143}
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153
154irqreturn_t
155qla2300_intr_handler(int irq, void *dev_id)
156{
157 scsi_qla_host_t *vha;
158 struct device_reg_2xxx __iomem *reg;
159 int status;
160 unsigned long iter;
161 uint32_t stat;
162 uint16_t hccr;
163 uint16_t mb[4];
164 struct rsp_que *rsp;
165 struct qla_hw_data *ha;
166 unsigned long flags;
167
168 rsp = (struct rsp_que *) dev_id;
169 if (!rsp) {
170 ql_log(ql_log_info, NULL, 0x5058,
171 "%s: NULL response queue pointer.\n", __func__);
172 return (IRQ_NONE);
173 }
174
175 ha = rsp->hw;
176 reg = &ha->iobase->isp;
177 status = 0;
178
179 spin_lock_irqsave(&ha->hardware_lock, flags);
180 vha = pci_get_drvdata(ha->pdev);
181 for (iter = 50; iter--; ) {
182 stat = RD_REG_DWORD(®->u.isp2300.host_status);
183 if (qla2x00_check_reg32_for_disconnect(vha, stat))
184 break;
185 if (stat & HSR_RISC_PAUSED) {
186 if (unlikely(pci_channel_offline(ha->pdev)))
187 break;
188
189 hccr = RD_REG_WORD(®->hccr);
190
191 if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
192 ql_log(ql_log_warn, vha, 0x5026,
193 "Parity error -- HCCR=%x, Dumping "
194 "firmware.\n", hccr);
195 else
196 ql_log(ql_log_warn, vha, 0x5027,
197 "RISC paused -- HCCR=%x, Dumping "
198 "firmware.\n", hccr);
199
200
201
202
203
204
205 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
206 RD_REG_WORD(®->hccr);
207
208 ha->isp_ops->fw_dump(vha, 1);
209 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
210 break;
211 } else if ((stat & HSR_RISC_INT) == 0)
212 break;
213
214 switch (stat & 0xff) {
215 case 0x1:
216 case 0x2:
217 case 0x10:
218 case 0x11:
219 qla2x00_mbx_completion(vha, MSW(stat));
220 status |= MBX_INTERRUPT;
221
222
223 WRT_REG_WORD(®->semaphore, 0);
224 break;
225 case 0x12:
226 mb[0] = MSW(stat);
227 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
228 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
229 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
230 qla2x00_async_event(vha, rsp, mb);
231 break;
232 case 0x13:
233 qla2x00_process_response_queue(rsp);
234 break;
235 case 0x15:
236 mb[0] = MBA_CMPLT_1_16BIT;
237 mb[1] = MSW(stat);
238 qla2x00_async_event(vha, rsp, mb);
239 break;
240 case 0x16:
241 mb[0] = MBA_SCSI_COMPLETION;
242 mb[1] = MSW(stat);
243 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
244 qla2x00_async_event(vha, rsp, mb);
245 break;
246 default:
247 ql_dbg(ql_dbg_async, vha, 0x5028,
248 "Unrecognized interrupt type (%d).\n", stat & 0xff);
249 break;
250 }
251 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
252 RD_REG_WORD_RELAXED(®->hccr);
253 }
254 qla2x00_handle_mbx_completion(ha, status);
255 spin_unlock_irqrestore(&ha->hardware_lock, flags);
256
257 return (IRQ_HANDLED);
258}
259
260
261
262
263
264
265static void
266qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
267{
268 uint16_t cnt;
269 uint32_t mboxes;
270 uint16_t __iomem *wptr;
271 struct qla_hw_data *ha = vha->hw;
272 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
273
274
275 mboxes = (1 << ha->mbx_count) - 1;
276 if (!ha->mcp)
277 ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
278 else
279 mboxes = ha->mcp->in_mb;
280
281
282 ha->flags.mbox_int = 1;
283 ha->mailbox_out[0] = mb0;
284 mboxes >>= 1;
285 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
286
287 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
288 if (IS_QLA2200(ha) && cnt == 8)
289 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
290 if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
291 ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
292 else if (mboxes & BIT_0)
293 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
294
295 wptr++;
296 mboxes >>= 1;
297 }
298}
299
300static void
301qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
302{
303 static char *event[] =
304 { "Complete", "Request Notification", "Time Extension" };
305 int rval;
306 struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
307 struct device_reg_82xx __iomem *reg82 = &vha->hw->iobase->isp82;
308 uint16_t __iomem *wptr;
309 uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
310
311
312 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
313 wptr = (uint16_t __iomem *)®24->mailbox1;
314 else if (IS_QLA8044(vha->hw))
315 wptr = (uint16_t __iomem *)®82->mailbox_out[1];
316 else
317 return;
318
319 for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
320 mb[cnt] = RD_REG_WORD(wptr);
321
322 ql_dbg(ql_dbg_async, vha, 0x5021,
323 "Inter-Driver Communication %s -- "
324 "%04x %04x %04x %04x %04x %04x %04x.\n",
325 event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
326 mb[4], mb[5], mb[6]);
327 switch (aen) {
328
329 case MBA_IDC_COMPLETE:
330 if (mb[1] >> 15) {
331 vha->hw->flags.idc_compl_status = 1;
332 if (vha->hw->notify_dcbx_comp && !vha->vp_idx)
333 complete(&vha->hw->dcbx_comp);
334 }
335 break;
336
337 case MBA_IDC_NOTIFY:
338
339 timeout = (descr >> 8) & 0xf;
340 ql_dbg(ql_dbg_async, vha, 0x5022,
341 "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
342 vha->host_no, event[aen & 0xff], timeout);
343
344 if (!timeout)
345 return;
346 rval = qla2x00_post_idc_ack_work(vha, mb);
347 if (rval != QLA_SUCCESS)
348 ql_log(ql_log_warn, vha, 0x5023,
349 "IDC failed to post ACK.\n");
350 break;
351 case MBA_IDC_TIME_EXT:
352 vha->hw->idc_extend_tmo = descr;
353 ql_dbg(ql_dbg_async, vha, 0x5087,
354 "%lu Inter-Driver Communication %s -- "
355 "Extend timeout by=%d.\n",
356 vha->host_no, event[aen & 0xff], vha->hw->idc_extend_tmo);
357 break;
358 }
359}
360
361#define LS_UNKNOWN 2
362const char *
363qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
364{
365 static const char *const link_speeds[] = {
366 "1", "2", "?", "4", "8", "16", "32", "10"
367 };
368#define QLA_LAST_SPEED 7
369
370 if (IS_QLA2100(ha) || IS_QLA2200(ha))
371 return link_speeds[0];
372 else if (speed == 0x13)
373 return link_speeds[QLA_LAST_SPEED];
374 else if (speed < QLA_LAST_SPEED)
375 return link_speeds[speed];
376 else
377 return link_speeds[LS_UNKNOWN];
378}
379
380static void
381qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
382{
383 struct qla_hw_data *ha = vha->hw;
384
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394
395
396 ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
397 "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
398 mb[0], mb[1], mb[2], mb[6]);
399 ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
400 "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
401 "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
402
403 if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
404 IDC_HEARTBEAT_FAILURE)) {
405 ha->flags.nic_core_hung = 1;
406 ql_log(ql_log_warn, vha, 0x5060,
407 "83XX: F/W Error Reported: Check if reset required.\n");
408
409 if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
410 uint32_t protocol_engine_id, fw_err_code, err_level;
411
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425 protocol_engine_id = (mb[2] & 0xff);
426 fw_err_code = (((mb[2] & 0xff00) >> 8) |
427 ((mb[6] & 0x1fff) << 8));
428 err_level = ((mb[6] & 0xe000) >> 13);
429 ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
430 "Register: protocol_engine_id=0x%x "
431 "fw_err_code=0x%x err_level=0x%x.\n",
432 protocol_engine_id, fw_err_code, err_level);
433 ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
434 "Register: 0x%x%x.\n", mb[7], mb[3]);
435 if (err_level == ERR_LEVEL_NON_FATAL) {
436 ql_log(ql_log_warn, vha, 0x5063,
437 "Not a fatal error, f/w has recovered itself.\n");
438 } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
439 ql_log(ql_log_fatal, vha, 0x5064,
440 "Recoverable Fatal error: Chip reset "
441 "required.\n");
442 qla83xx_schedule_work(vha,
443 QLA83XX_NIC_CORE_RESET);
444 } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
445 ql_log(ql_log_fatal, vha, 0x5065,
446 "Unrecoverable Fatal error: Set FAILED "
447 "state, reboot required.\n");
448 qla83xx_schedule_work(vha,
449 QLA83XX_NIC_CORE_UNRECOVERABLE);
450 }
451 }
452
453 if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
454 uint16_t peg_fw_state, nw_interface_link_up;
455 uint16_t nw_interface_signal_detect, sfp_status;
456 uint16_t htbt_counter, htbt_monitor_enable;
457 uint16_t sfp_additional_info, sfp_multirate;
458 uint16_t sfp_tx_fault, link_speed, dcbx_status;
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491 peg_fw_state = (mb[2] & 0x00ff);
492 nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
493 nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
494 sfp_status = ((mb[2] & 0x0c00) >> 10);
495 htbt_counter = ((mb[2] & 0x7000) >> 12);
496 htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
497 sfp_additional_info = (mb[6] & 0x0003);
498 sfp_multirate = ((mb[6] & 0x0004) >> 2);
499 sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
500 link_speed = ((mb[6] & 0x0070) >> 4);
501 dcbx_status = ((mb[6] & 0x7000) >> 12);
502
503 ql_log(ql_log_warn, vha, 0x5066,
504 "Peg-to-Fc Status Register:\n"
505 "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
506 "nw_interface_signal_detect=0x%x"
507 "\nsfp_statis=0x%x.\n ", peg_fw_state,
508 nw_interface_link_up, nw_interface_signal_detect,
509 sfp_status);
510 ql_log(ql_log_warn, vha, 0x5067,
511 "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
512 "sfp_additional_info=0x%x, sfp_multirate=0x%x.\n ",
513 htbt_counter, htbt_monitor_enable,
514 sfp_additional_info, sfp_multirate);
515 ql_log(ql_log_warn, vha, 0x5068,
516 "sfp_tx_fault=0x%x, link_state=0x%x, "
517 "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
518 dcbx_status);
519
520 qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
521 }
522
523 if (mb[1] & IDC_HEARTBEAT_FAILURE) {
524 ql_log(ql_log_warn, vha, 0x5069,
525 "Heartbeat Failure encountered, chip reset "
526 "required.\n");
527
528 qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
529 }
530 }
531
532 if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
533 ql_log(ql_log_info, vha, 0x506a,
534 "IDC Device-State changed = 0x%x.\n", mb[4]);
535 if (ha->flags.nic_core_reset_owner)
536 return;
537 qla83xx_schedule_work(vha, MBA_IDC_AEN);
538 }
539}
540
541int
542qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
543{
544 struct qla_hw_data *ha = vha->hw;
545 scsi_qla_host_t *vp;
546 uint32_t vp_did;
547 unsigned long flags;
548 int ret = 0;
549
550 if (!ha->num_vhosts)
551 return ret;
552
553 spin_lock_irqsave(&ha->vport_slock, flags);
554 list_for_each_entry(vp, &ha->vp_list, list) {
555 vp_did = vp->d_id.b24;
556 if (vp_did == rscn_entry) {
557 ret = 1;
558 break;
559 }
560 }
561 spin_unlock_irqrestore(&ha->vport_slock, flags);
562
563 return ret;
564}
565
566fc_port_t *
567qla2x00_find_fcport_by_loopid(scsi_qla_host_t *vha, uint16_t loop_id)
568{
569 fc_port_t *f, *tf;
570
571 f = tf = NULL;
572 list_for_each_entry_safe(f, tf, &vha->vp_fcports, list)
573 if (f->loop_id == loop_id)
574 return f;
575 return NULL;
576}
577
578fc_port_t *
579qla2x00_find_fcport_by_wwpn(scsi_qla_host_t *vha, u8 *wwpn, u8 incl_deleted)
580{
581 fc_port_t *f, *tf;
582
583 f = tf = NULL;
584 list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) {
585 if (memcmp(f->port_name, wwpn, WWN_SIZE) == 0) {
586 if (incl_deleted)
587 return f;
588 else if (f->deleted == 0)
589 return f;
590 }
591 }
592 return NULL;
593}
594
595fc_port_t *
596qla2x00_find_fcport_by_nportid(scsi_qla_host_t *vha, port_id_t *id,
597 u8 incl_deleted)
598{
599 fc_port_t *f, *tf;
600
601 f = tf = NULL;
602 list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) {
603 if (f->d_id.b24 == id->b24) {
604 if (incl_deleted)
605 return f;
606 else if (f->deleted == 0)
607 return f;
608 }
609 }
610 return NULL;
611}
612
613
614
615
616
617
618void
619qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
620{
621 uint16_t handle_cnt;
622 uint16_t cnt, mbx;
623 uint32_t handles[5];
624 struct qla_hw_data *ha = vha->hw;
625 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
626 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
627 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
628 uint32_t rscn_entry, host_pid;
629 unsigned long flags;
630 fc_port_t *fcport = NULL;
631
632
633 handle_cnt = 0;
634 if (IS_CNA_CAPABLE(ha))
635 goto skip_rio;
636 switch (mb[0]) {
637 case MBA_SCSI_COMPLETION:
638 handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
639 handle_cnt = 1;
640 break;
641 case MBA_CMPLT_1_16BIT:
642 handles[0] = mb[1];
643 handle_cnt = 1;
644 mb[0] = MBA_SCSI_COMPLETION;
645 break;
646 case MBA_CMPLT_2_16BIT:
647 handles[0] = mb[1];
648 handles[1] = mb[2];
649 handle_cnt = 2;
650 mb[0] = MBA_SCSI_COMPLETION;
651 break;
652 case MBA_CMPLT_3_16BIT:
653 handles[0] = mb[1];
654 handles[1] = mb[2];
655 handles[2] = mb[3];
656 handle_cnt = 3;
657 mb[0] = MBA_SCSI_COMPLETION;
658 break;
659 case MBA_CMPLT_4_16BIT:
660 handles[0] = mb[1];
661 handles[1] = mb[2];
662 handles[2] = mb[3];
663 handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
664 handle_cnt = 4;
665 mb[0] = MBA_SCSI_COMPLETION;
666 break;
667 case MBA_CMPLT_5_16BIT:
668 handles[0] = mb[1];
669 handles[1] = mb[2];
670 handles[2] = mb[3];
671 handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
672 handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
673 handle_cnt = 5;
674 mb[0] = MBA_SCSI_COMPLETION;
675 break;
676 case MBA_CMPLT_2_32BIT:
677 handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
678 handles[1] = le32_to_cpu(
679 ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
680 RD_MAILBOX_REG(ha, reg, 6));
681 handle_cnt = 2;
682 mb[0] = MBA_SCSI_COMPLETION;
683 break;
684 default:
685 break;
686 }
687skip_rio:
688 switch (mb[0]) {
689 case MBA_SCSI_COMPLETION:
690 if (!vha->flags.online)
691 break;
692
693 for (cnt = 0; cnt < handle_cnt; cnt++)
694 qla2x00_process_completed_request(vha, rsp->req,
695 handles[cnt]);
696 break;
697
698 case MBA_RESET:
699 ql_dbg(ql_dbg_async, vha, 0x5002,
700 "Asynchronous RESET.\n");
701
702 set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
703 break;
704
705 case MBA_SYSTEM_ERR:
706 mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ?
707 RD_REG_WORD(®24->mailbox7) : 0;
708 ql_log(ql_log_warn, vha, 0x5003,
709 "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
710 "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
711
712 ha->isp_ops->fw_dump(vha, 1);
713 ha->flags.fw_init_done = 0;
714 QLA_FW_STOPPED(ha);
715
716 if (IS_FWI2_CAPABLE(ha)) {
717 if (mb[1] == 0 && mb[2] == 0) {
718 ql_log(ql_log_fatal, vha, 0x5004,
719 "Unrecoverable Hardware Error: adapter "
720 "marked OFFLINE!\n");
721 vha->flags.online = 0;
722 vha->device_flags |= DFLG_DEV_FAILED;
723 } else {
724
725 if ((mbx & MBX_3) && (ha->port_no == 0))
726 set_bit(MPI_RESET_NEEDED,
727 &vha->dpc_flags);
728
729 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
730 }
731 } else if (mb[1] == 0) {
732 ql_log(ql_log_fatal, vha, 0x5005,
733 "Unrecoverable Hardware Error: adapter marked "
734 "OFFLINE!\n");
735 vha->flags.online = 0;
736 vha->device_flags |= DFLG_DEV_FAILED;
737 } else
738 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
739 break;
740
741 case MBA_REQ_TRANSFER_ERR:
742 ql_log(ql_log_warn, vha, 0x5006,
743 "ISP Request Transfer Error (%x).\n", mb[1]);
744
745 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
746 break;
747
748 case MBA_RSP_TRANSFER_ERR:
749 ql_log(ql_log_warn, vha, 0x5007,
750 "ISP Response Transfer Error (%x).\n", mb[1]);
751
752 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
753 break;
754
755 case MBA_WAKEUP_THRES:
756 ql_dbg(ql_dbg_async, vha, 0x5008,
757 "Asynchronous WAKEUP_THRES (%x).\n", mb[1]);
758 break;
759
760 case MBA_LOOP_INIT_ERR:
761 ql_log(ql_log_warn, vha, 0x5090,
762 "LOOP INIT ERROR (%x).\n", mb[1]);
763 ha->isp_ops->fw_dump(vha, 1);
764 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
765 break;
766
767 case MBA_LIP_OCCURRED:
768 ha->flags.lip_ae = 1;
769 ha->flags.n2n_ae = 0;
770
771 ql_dbg(ql_dbg_async, vha, 0x5009,
772 "LIP occurred (%x).\n", mb[1]);
773
774 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
775 atomic_set(&vha->loop_state, LOOP_DOWN);
776 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
777 qla2x00_mark_all_devices_lost(vha, 1);
778 }
779
780 if (vha->vp_idx) {
781 atomic_set(&vha->vp_state, VP_FAILED);
782 fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
783 }
784
785 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
786 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
787
788 vha->flags.management_server_logged_in = 0;
789 qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
790 break;
791
792 case MBA_LOOP_UP:
793 if (IS_QLA2100(ha) || IS_QLA2200(ha))
794 ha->link_data_rate = PORT_SPEED_1GB;
795 else
796 ha->link_data_rate = mb[1];
797
798 ql_log(ql_log_info, vha, 0x500a,
799 "LOOP UP detected (%s Gbps).\n",
800 qla2x00_get_link_speed_str(ha, ha->link_data_rate));
801
802 vha->flags.management_server_logged_in = 0;
803 qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
804
805 if (AUTO_DETECT_SFP_SUPPORT(vha)) {
806 set_bit(DETECT_SFP_CHANGE, &vha->dpc_flags);
807 qla2xxx_wake_dpc(vha);
808 }
809 break;
810
811 case MBA_LOOP_DOWN:
812 ha->flags.n2n_ae = 0;
813 ha->flags.lip_ae = 0;
814 ha->current_topology = 0;
815
816 mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
817 ? RD_REG_WORD(®24->mailbox4) : 0;
818 mbx = (IS_P3P_TYPE(ha)) ? RD_REG_WORD(®82->mailbox_out[4])
819 : mbx;
820 ql_log(ql_log_info, vha, 0x500b,
821 "LOOP DOWN detected (%x %x %x %x).\n",
822 mb[1], mb[2], mb[3], mbx);
823
824 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
825 atomic_set(&vha->loop_state, LOOP_DOWN);
826 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
827
828
829
830
831
832 if (!vha->vp_idx) {
833 if (ha->flags.fawwpn_enabled) {
834 void *wwpn = ha->init_cb->port_name;
835 memcpy(vha->port_name, wwpn, WWN_SIZE);
836 fc_host_port_name(vha->host) =
837 wwn_to_u64(vha->port_name);
838 ql_dbg(ql_dbg_init + ql_dbg_verbose,
839 vha, 0x00d8, "LOOP DOWN detected,"
840 "restore WWPN %016llx\n",
841 wwn_to_u64(vha->port_name));
842 }
843
844 clear_bit(VP_CONFIG_OK, &vha->vp_flags);
845 }
846
847 vha->device_flags |= DFLG_NO_CABLE;
848 qla2x00_mark_all_devices_lost(vha, 1);
849 }
850
851 if (vha->vp_idx) {
852 atomic_set(&vha->vp_state, VP_FAILED);
853 fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
854 }
855
856 vha->flags.management_server_logged_in = 0;
857 ha->link_data_rate = PORT_SPEED_UNKNOWN;
858 qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
859 break;
860
861 case MBA_LIP_RESET:
862 ql_dbg(ql_dbg_async, vha, 0x500c,
863 "LIP reset occurred (%x).\n", mb[1]);
864
865 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
866 atomic_set(&vha->loop_state, LOOP_DOWN);
867 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
868 qla2x00_mark_all_devices_lost(vha, 1);
869 }
870
871 if (vha->vp_idx) {
872 atomic_set(&vha->vp_state, VP_FAILED);
873 fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
874 }
875
876 set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
877
878 ha->operating_mode = LOOP;
879 vha->flags.management_server_logged_in = 0;
880 qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
881 break;
882
883
884 case MBA_POINT_TO_POINT:
885 ha->flags.lip_ae = 0;
886 ha->flags.n2n_ae = 1;
887
888 if (IS_QLA2100(ha))
889 break;
890
891 if (IS_CNA_CAPABLE(ha)) {
892 ql_dbg(ql_dbg_async, vha, 0x500d,
893 "DCBX Completed -- %04x %04x %04x.\n",
894 mb[1], mb[2], mb[3]);
895 if (ha->notify_dcbx_comp && !vha->vp_idx)
896 complete(&ha->dcbx_comp);
897
898 } else
899 ql_dbg(ql_dbg_async, vha, 0x500e,
900 "Asynchronous P2P MODE received.\n");
901
902
903
904
905
906 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
907 atomic_set(&vha->loop_state, LOOP_DOWN);
908 if (!atomic_read(&vha->loop_down_timer))
909 atomic_set(&vha->loop_down_timer,
910 LOOP_DOWN_TIME);
911 qla2x00_mark_all_devices_lost(vha, 1);
912 }
913
914 if (vha->vp_idx) {
915 atomic_set(&vha->vp_state, VP_FAILED);
916 fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
917 }
918
919 if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
920 set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
921
922 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
923 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
924
925 ha->flags.gpsc_supported = 1;
926 vha->flags.management_server_logged_in = 0;
927 break;
928
929 case MBA_CHG_IN_CONNECTION:
930 if (IS_QLA2100(ha))
931 break;
932
933 ql_dbg(ql_dbg_async, vha, 0x500f,
934 "Configuration change detected: value=%x.\n", mb[1]);
935
936 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
937 atomic_set(&vha->loop_state, LOOP_DOWN);
938 if (!atomic_read(&vha->loop_down_timer))
939 atomic_set(&vha->loop_down_timer,
940 LOOP_DOWN_TIME);
941 qla2x00_mark_all_devices_lost(vha, 1);
942 }
943
944 if (vha->vp_idx) {
945 atomic_set(&vha->vp_state, VP_FAILED);
946 fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
947 }
948
949 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
950 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
951 break;
952
953 case MBA_PORT_UPDATE:
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969 if (IS_QLA2XXX_MIDTYPE(ha) &&
970 ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
971 (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
972 break;
973
974 if (mb[2] == 0x7) {
975 ql_dbg(ql_dbg_async, vha, 0x5010,
976 "Port %s %04x %04x %04x.\n",
977 mb[1] == 0xffff ? "unavailable" : "logout",
978 mb[1], mb[2], mb[3]);
979
980 if (mb[1] == 0xffff)
981 goto global_port_update;
982
983 if (mb[1] == NPH_SNS_LID(ha)) {
984 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
985 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
986 break;
987 }
988
989
990 if (IS_FWI2_CAPABLE(ha))
991 handle_cnt = NPH_SNS;
992 else
993 handle_cnt = SIMPLE_NAME_SERVER;
994 if (mb[1] == handle_cnt) {
995 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
996 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
997 break;
998 }
999
1000
1001 fcport = qla2x00_find_fcport_by_loopid(vha, mb[1]);
1002 if (!fcport)
1003 break;
1004 if (atomic_read(&fcport->state) != FCS_ONLINE)
1005 break;
1006 ql_dbg(ql_dbg_async, vha, 0x508a,
1007 "Marking port lost loopid=%04x portid=%06x.\n",
1008 fcport->loop_id, fcport->d_id.b24);
1009 if (qla_ini_mode_enabled(vha)) {
1010 qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
1011 fcport->logout_on_delete = 0;
1012 qlt_schedule_sess_for_deletion_lock(fcport);
1013 }
1014 break;
1015
1016global_port_update:
1017 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
1018 atomic_set(&vha->loop_state, LOOP_DOWN);
1019 atomic_set(&vha->loop_down_timer,
1020 LOOP_DOWN_TIME);
1021 vha->device_flags |= DFLG_NO_CABLE;
1022 qla2x00_mark_all_devices_lost(vha, 1);
1023 }
1024
1025 if (vha->vp_idx) {
1026 atomic_set(&vha->vp_state, VP_FAILED);
1027 fc_vport_set_state(vha->fc_vport,
1028 FC_VPORT_FAILED);
1029 qla2x00_mark_all_devices_lost(vha, 1);
1030 }
1031
1032 vha->flags.management_server_logged_in = 0;
1033 ha->link_data_rate = PORT_SPEED_UNKNOWN;
1034 break;
1035 }
1036
1037
1038
1039
1040
1041
1042 atomic_set(&vha->loop_down_timer, 0);
1043 if (atomic_read(&vha->loop_state) != LOOP_DOWN &&
1044 !ha->flags.n2n_ae &&
1045 atomic_read(&vha->loop_state) != LOOP_DEAD) {
1046 ql_dbg(ql_dbg_async, vha, 0x5011,
1047 "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
1048 mb[1], mb[2], mb[3]);
1049
1050 qlt_async_event(mb[0], vha, mb);
1051 break;
1052 }
1053
1054 ql_dbg(ql_dbg_async, vha, 0x5012,
1055 "Port database changed %04x %04x %04x.\n",
1056 mb[1], mb[2], mb[3]);
1057
1058
1059
1060
1061 atomic_set(&vha->loop_state, LOOP_UP);
1062
1063 qla2x00_mark_all_devices_lost(vha, 1);
1064
1065 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1066 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1067 set_bit(VP_CONFIG_OK, &vha->vp_flags);
1068
1069 qlt_async_event(mb[0], vha, mb);
1070 break;
1071
1072 case MBA_RSCN_UPDATE:
1073
1074 if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
1075 break;
1076
1077 if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
1078 break;
1079
1080 ql_dbg(ql_dbg_async, vha, 0x5013,
1081 "RSCN database changed -- %04x %04x %04x.\n",
1082 mb[1], mb[2], mb[3]);
1083
1084 rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
1085 host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
1086 | vha->d_id.b.al_pa;
1087 if (rscn_entry == host_pid) {
1088 ql_dbg(ql_dbg_async, vha, 0x5014,
1089 "Ignoring RSCN update to local host "
1090 "port ID (%06x).\n", host_pid);
1091 break;
1092 }
1093
1094
1095 rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
1096
1097
1098 if (qla2x00_is_a_vp_did(vha, rscn_entry))
1099 break;
1100
1101 atomic_set(&vha->loop_down_timer, 0);
1102 vha->flags.management_server_logged_in = 0;
1103 {
1104 struct event_arg ea;
1105
1106 memset(&ea, 0, sizeof(ea));
1107 ea.event = FCME_RSCN;
1108 ea.id.b24 = rscn_entry;
1109 ea.id.b.rsvd_1 = rscn_entry >> 24;
1110 qla2x00_fcport_event_handler(vha, &ea);
1111 qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
1112 }
1113 break;
1114
1115 case MBA_ZIO_RESPONSE:
1116 ql_dbg(ql_dbg_async, vha, 0x5015,
1117 "[R|Z]IO update completion.\n");
1118
1119 if (IS_FWI2_CAPABLE(ha))
1120 qla24xx_process_response_queue(vha, rsp);
1121 else
1122 qla2x00_process_response_queue(rsp);
1123 break;
1124
1125 case MBA_DISCARD_RND_FRAME:
1126 ql_dbg(ql_dbg_async, vha, 0x5016,
1127 "Discard RND Frame -- %04x %04x %04x.\n",
1128 mb[1], mb[2], mb[3]);
1129 break;
1130
1131 case MBA_TRACE_NOTIFICATION:
1132 ql_dbg(ql_dbg_async, vha, 0x5017,
1133 "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
1134 break;
1135
1136 case MBA_ISP84XX_ALERT:
1137 ql_dbg(ql_dbg_async, vha, 0x5018,
1138 "ISP84XX Alert Notification -- %04x %04x %04x.\n",
1139 mb[1], mb[2], mb[3]);
1140
1141 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
1142 switch (mb[1]) {
1143 case A84_PANIC_RECOVERY:
1144 ql_log(ql_log_info, vha, 0x5019,
1145 "Alert 84XX: panic recovery %04x %04x.\n",
1146 mb[2], mb[3]);
1147 break;
1148 case A84_OP_LOGIN_COMPLETE:
1149 ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
1150 ql_log(ql_log_info, vha, 0x501a,
1151 "Alert 84XX: firmware version %x.\n",
1152 ha->cs84xx->op_fw_version);
1153 break;
1154 case A84_DIAG_LOGIN_COMPLETE:
1155 ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
1156 ql_log(ql_log_info, vha, 0x501b,
1157 "Alert 84XX: diagnostic firmware version %x.\n",
1158 ha->cs84xx->diag_fw_version);
1159 break;
1160 case A84_GOLD_LOGIN_COMPLETE:
1161 ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
1162 ha->cs84xx->fw_update = 1;
1163 ql_log(ql_log_info, vha, 0x501c,
1164 "Alert 84XX: gold firmware version %x.\n",
1165 ha->cs84xx->gold_fw_version);
1166 break;
1167 default:
1168 ql_log(ql_log_warn, vha, 0x501d,
1169 "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
1170 mb[1], mb[2], mb[3]);
1171 }
1172 spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
1173 break;
1174 case MBA_DCBX_START:
1175 ql_dbg(ql_dbg_async, vha, 0x501e,
1176 "DCBX Started -- %04x %04x %04x.\n",
1177 mb[1], mb[2], mb[3]);
1178 break;
1179 case MBA_DCBX_PARAM_UPDATE:
1180 ql_dbg(ql_dbg_async, vha, 0x501f,
1181 "DCBX Parameters Updated -- %04x %04x %04x.\n",
1182 mb[1], mb[2], mb[3]);
1183 break;
1184 case MBA_FCF_CONF_ERR:
1185 ql_dbg(ql_dbg_async, vha, 0x5020,
1186 "FCF Configuration Error -- %04x %04x %04x.\n",
1187 mb[1], mb[2], mb[3]);
1188 break;
1189 case MBA_IDC_NOTIFY:
1190 if (IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
1191 mb[4] = RD_REG_WORD(®24->mailbox4);
1192 if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
1193 (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
1194 (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
1195 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
1196
1197
1198
1199 if (atomic_read(&vha->loop_state) == LOOP_DOWN)
1200 atomic_set(&vha->loop_down_timer,
1201 LOOP_DOWN_TIME);
1202 qla2xxx_wake_dpc(vha);
1203 }
1204 }
1205 case MBA_IDC_COMPLETE:
1206 if (ha->notify_lb_portup_comp && !vha->vp_idx)
1207 complete(&ha->lb_portup_comp);
1208
1209 case MBA_IDC_TIME_EXT:
1210 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) ||
1211 IS_QLA8044(ha))
1212 qla81xx_idc_event(vha, mb[0], mb[1]);
1213 break;
1214
1215 case MBA_IDC_AEN:
1216 mb[4] = RD_REG_WORD(®24->mailbox4);
1217 mb[5] = RD_REG_WORD(®24->mailbox5);
1218 mb[6] = RD_REG_WORD(®24->mailbox6);
1219 mb[7] = RD_REG_WORD(®24->mailbox7);
1220 qla83xx_handle_8200_aen(vha, mb);
1221 break;
1222
1223 case MBA_DPORT_DIAGNOSTICS:
1224 ql_dbg(ql_dbg_async, vha, 0x5052,
1225 "D-Port Diagnostics: %04x result=%s\n",
1226 mb[0],
1227 mb[1] == 0 ? "start" :
1228 mb[1] == 1 ? "done (pass)" :
1229 mb[1] == 2 ? "done (error)" : "other");
1230 break;
1231
1232 case MBA_TEMPERATURE_ALERT:
1233 ql_dbg(ql_dbg_async, vha, 0x505e,
1234 "TEMPERATURE ALERT: %04x %04x %04x\n", mb[1], mb[2], mb[3]);
1235 if (mb[1] == 0x12)
1236 schedule_work(&ha->board_disable);
1237 break;
1238
1239 case MBA_TRANS_INSERT:
1240 ql_dbg(ql_dbg_async, vha, 0x5091,
1241 "Transceiver Insertion: %04x\n", mb[1]);
1242 break;
1243
1244 default:
1245 ql_dbg(ql_dbg_async, vha, 0x5057,
1246 "Unknown AEN:%04x %04x %04x %04x\n",
1247 mb[0], mb[1], mb[2], mb[3]);
1248 }
1249
1250 qlt_async_event(mb[0], vha, mb);
1251
1252 if (!vha->vp_idx && ha->num_vhosts)
1253 qla2x00_alert_all_vps(rsp, mb);
1254}
1255
1256
1257
1258
1259
1260
1261void
1262qla2x00_process_completed_request(struct scsi_qla_host *vha,
1263 struct req_que *req, uint32_t index)
1264{
1265 srb_t *sp;
1266 struct qla_hw_data *ha = vha->hw;
1267
1268
1269 if (index >= req->num_outstanding_cmds) {
1270 ql_log(ql_log_warn, vha, 0x3014,
1271 "Invalid SCSI command index (%x).\n", index);
1272
1273 if (IS_P3P_TYPE(ha))
1274 set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
1275 else
1276 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1277 return;
1278 }
1279
1280 sp = req->outstanding_cmds[index];
1281 if (sp) {
1282
1283 req->outstanding_cmds[index] = NULL;
1284
1285
1286 sp->done(sp, DID_OK << 16);
1287 } else {
1288 ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
1289
1290 if (IS_P3P_TYPE(ha))
1291 set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
1292 else
1293 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1294 }
1295}
1296
1297srb_t *
1298qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
1299 struct req_que *req, void *iocb)
1300{
1301 struct qla_hw_data *ha = vha->hw;
1302 sts_entry_t *pkt = iocb;
1303 srb_t *sp = NULL;
1304 uint16_t index;
1305
1306 index = LSW(pkt->handle);
1307 if (index >= req->num_outstanding_cmds) {
1308 ql_log(ql_log_warn, vha, 0x5031,
1309 "Invalid command index (%x) type %8ph.\n",
1310 index, iocb);
1311 if (IS_P3P_TYPE(ha))
1312 set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
1313 else
1314 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1315 goto done;
1316 }
1317 sp = req->outstanding_cmds[index];
1318 if (!sp) {
1319 ql_log(ql_log_warn, vha, 0x5032,
1320 "Invalid completion handle (%x) -- timed-out.\n", index);
1321 return sp;
1322 }
1323 if (sp->handle != index) {
1324 ql_log(ql_log_warn, vha, 0x5033,
1325 "SRB handle (%x) mismatch %x.\n", sp->handle, index);
1326 return NULL;
1327 }
1328
1329 req->outstanding_cmds[index] = NULL;
1330
1331done:
1332 return sp;
1333}
1334
1335static void
1336qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
1337 struct mbx_entry *mbx)
1338{
1339 const char func[] = "MBX-IOCB";
1340 const char *type;
1341 fc_port_t *fcport;
1342 srb_t *sp;
1343 struct srb_iocb *lio;
1344 uint16_t *data;
1345 uint16_t status;
1346
1347 sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
1348 if (!sp)
1349 return;
1350
1351 lio = &sp->u.iocb_cmd;
1352 type = sp->name;
1353 fcport = sp->fcport;
1354 data = lio->u.logio.data;
1355
1356 data[0] = MBS_COMMAND_ERROR;
1357 data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
1358 QLA_LOGIO_LOGIN_RETRIED : 0;
1359 if (mbx->entry_status) {
1360 ql_dbg(ql_dbg_async, vha, 0x5043,
1361 "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
1362 "entry-status=%x status=%x state-flag=%x "
1363 "status-flags=%x.\n", type, sp->handle,
1364 fcport->d_id.b.domain, fcport->d_id.b.area,
1365 fcport->d_id.b.al_pa, mbx->entry_status,
1366 le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
1367 le16_to_cpu(mbx->status_flags));
1368
1369 ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
1370 (uint8_t *)mbx, sizeof(*mbx));
1371
1372 goto logio_done;
1373 }
1374
1375 status = le16_to_cpu(mbx->status);
1376 if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
1377 le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
1378 status = 0;
1379 if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
1380 ql_dbg(ql_dbg_async, vha, 0x5045,
1381 "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
1382 type, sp->handle, fcport->d_id.b.domain,
1383 fcport->d_id.b.area, fcport->d_id.b.al_pa,
1384 le16_to_cpu(mbx->mb1));
1385
1386 data[0] = MBS_COMMAND_COMPLETE;
1387 if (sp->type == SRB_LOGIN_CMD) {
1388 fcport->port_type = FCT_TARGET;
1389 if (le16_to_cpu(mbx->mb1) & BIT_0)
1390 fcport->port_type = FCT_INITIATOR;
1391 else if (le16_to_cpu(mbx->mb1) & BIT_1)
1392 fcport->flags |= FCF_FCP2_DEVICE;
1393 }
1394 goto logio_done;
1395 }
1396
1397 data[0] = le16_to_cpu(mbx->mb0);
1398 switch (data[0]) {
1399 case MBS_PORT_ID_USED:
1400 data[1] = le16_to_cpu(mbx->mb1);
1401 break;
1402 case MBS_LOOP_ID_USED:
1403 break;
1404 default:
1405 data[0] = MBS_COMMAND_ERROR;
1406 break;
1407 }
1408
1409 ql_log(ql_log_warn, vha, 0x5046,
1410 "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
1411 "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
1412 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
1413 status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
1414 le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
1415 le16_to_cpu(mbx->mb7));
1416
1417logio_done:
1418 sp->done(sp, 0);
1419}
1420
1421static void
1422qla24xx_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
1423 struct mbx_24xx_entry *pkt)
1424{
1425 const char func[] = "MBX-IOCB2";
1426 srb_t *sp;
1427 struct srb_iocb *si;
1428 u16 sz, i;
1429 int res;
1430
1431 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
1432 if (!sp)
1433 return;
1434
1435 si = &sp->u.iocb_cmd;
1436 sz = min(ARRAY_SIZE(pkt->mb), ARRAY_SIZE(sp->u.iocb_cmd.u.mbx.in_mb));
1437
1438 for (i = 0; i < sz; i++)
1439 si->u.mbx.in_mb[i] = le16_to_cpu(pkt->mb[i]);
1440
1441 res = (si->u.mbx.in_mb[0] & MBS_MASK);
1442
1443 sp->done(sp, res);
1444}
1445
1446static void
1447qla24xxx_nack_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
1448 struct nack_to_isp *pkt)
1449{
1450 const char func[] = "nack";
1451 srb_t *sp;
1452 int res = 0;
1453
1454 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
1455 if (!sp)
1456 return;
1457
1458 if (pkt->u.isp2x.status != cpu_to_le16(NOTIFY_ACK_SUCCESS))
1459 res = QLA_FUNCTION_FAILED;
1460
1461 sp->done(sp, res);
1462}
1463
1464static void
1465qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
1466 sts_entry_t *pkt, int iocb_type)
1467{
1468 const char func[] = "CT_IOCB";
1469 const char *type;
1470 srb_t *sp;
1471 struct bsg_job *bsg_job;
1472 struct fc_bsg_reply *bsg_reply;
1473 uint16_t comp_status;
1474 int res = 0;
1475
1476 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
1477 if (!sp)
1478 return;
1479
1480 switch (sp->type) {
1481 case SRB_CT_CMD:
1482 bsg_job = sp->u.bsg_job;
1483 bsg_reply = bsg_job->reply;
1484
1485 type = "ct pass-through";
1486
1487 comp_status = le16_to_cpu(pkt->comp_status);
1488
1489
1490
1491
1492
1493 bsg_reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
1494 bsg_job->reply_len = sizeof(struct fc_bsg_reply);
1495
1496 if (comp_status != CS_COMPLETE) {
1497 if (comp_status == CS_DATA_UNDERRUN) {
1498 res = DID_OK << 16;
1499 bsg_reply->reply_payload_rcv_len =
1500 le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
1501
1502 ql_log(ql_log_warn, vha, 0x5048,
1503 "CT pass-through-%s error comp_status=0x%x total_byte=0x%x.\n",
1504 type, comp_status,
1505 bsg_reply->reply_payload_rcv_len);
1506 } else {
1507 ql_log(ql_log_warn, vha, 0x5049,
1508 "CT pass-through-%s error comp_status=0x%x.\n",
1509 type, comp_status);
1510 res = DID_ERROR << 16;
1511 bsg_reply->reply_payload_rcv_len = 0;
1512 }
1513 ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
1514 (uint8_t *)pkt, sizeof(*pkt));
1515 } else {
1516 res = DID_OK << 16;
1517 bsg_reply->reply_payload_rcv_len =
1518 bsg_job->reply_payload.payload_len;
1519 bsg_job->reply_len = 0;
1520 }
1521 break;
1522 case SRB_CT_PTHRU_CMD:
1523
1524
1525
1526
1527 res = qla2x00_chk_ms_status(vha, (ms_iocb_entry_t *)pkt,
1528 (struct ct_sns_rsp *)sp->u.iocb_cmd.u.ctarg.rsp,
1529 sp->name);
1530 break;
1531 }
1532
1533 sp->done(sp, res);
1534}
1535
1536static void
1537qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
1538 struct sts_entry_24xx *pkt, int iocb_type)
1539{
1540 const char func[] = "ELS_CT_IOCB";
1541 const char *type;
1542 srb_t *sp;
1543 struct bsg_job *bsg_job;
1544 struct fc_bsg_reply *bsg_reply;
1545 uint16_t comp_status;
1546 uint32_t fw_status[3];
1547 int res;
1548 struct srb_iocb *els;
1549
1550 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
1551 if (!sp)
1552 return;
1553
1554 type = NULL;
1555 switch (sp->type) {
1556 case SRB_ELS_CMD_RPT:
1557 case SRB_ELS_CMD_HST:
1558 type = "els";
1559 break;
1560 case SRB_CT_CMD:
1561 type = "ct pass-through";
1562 break;
1563 case SRB_ELS_DCMD:
1564 type = "Driver ELS logo";
1565 if (iocb_type != ELS_IOCB_TYPE) {
1566 ql_dbg(ql_dbg_user, vha, 0x5047,
1567 "Completing %s: (%p) type=%d.\n",
1568 type, sp, sp->type);
1569 sp->done(sp, 0);
1570 return;
1571 }
1572 break;
1573 case SRB_CT_PTHRU_CMD:
1574
1575
1576
1577 res = qla2x00_chk_ms_status(vha, (ms_iocb_entry_t *)pkt,
1578 (struct ct_sns_rsp *)sp->u.iocb_cmd.u.ctarg.rsp,
1579 sp->name);
1580 sp->done(sp, res);
1581 return;
1582 default:
1583 ql_dbg(ql_dbg_user, vha, 0x503e,
1584 "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
1585 return;
1586 }
1587
1588 comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
1589 fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
1590 fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
1591
1592 if (iocb_type == ELS_IOCB_TYPE) {
1593 els = &sp->u.iocb_cmd;
1594 els->u.els_plogi.fw_status[0] = fw_status[0];
1595 els->u.els_plogi.fw_status[1] = fw_status[1];
1596 els->u.els_plogi.fw_status[2] = fw_status[2];
1597 els->u.els_plogi.comp_status = fw_status[0];
1598 if (comp_status == CS_COMPLETE) {
1599 res = DID_OK << 16;
1600 } else {
1601 if (comp_status == CS_DATA_UNDERRUN) {
1602 res = DID_OK << 16;
1603 els->u.els_plogi.len =
1604 le16_to_cpu(((struct els_sts_entry_24xx *)
1605 pkt)->total_byte_count);
1606 } else {
1607 els->u.els_plogi.len = 0;
1608 res = DID_ERROR << 16;
1609 }
1610 }
1611 ql_log(ql_log_info, vha, 0x503f,
1612 "ELS IOCB Done -%s error hdl=%x comp_status=0x%x error subcode 1=0x%x error subcode 2=0x%x total_byte=0x%x\n",
1613 type, sp->handle, comp_status, fw_status[1], fw_status[2],
1614 le16_to_cpu(((struct els_sts_entry_24xx *)
1615 pkt)->total_byte_count));
1616 goto els_ct_done;
1617 }
1618
1619
1620
1621
1622 bsg_job = sp->u.bsg_job;
1623 bsg_reply = bsg_job->reply;
1624 bsg_reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
1625 bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
1626
1627 if (comp_status != CS_COMPLETE) {
1628 if (comp_status == CS_DATA_UNDERRUN) {
1629 res = DID_OK << 16;
1630 bsg_reply->reply_payload_rcv_len =
1631 le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
1632
1633 ql_dbg(ql_dbg_user, vha, 0x503f,
1634 "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
1635 "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
1636 type, sp->handle, comp_status, fw_status[1], fw_status[2],
1637 le16_to_cpu(((struct els_sts_entry_24xx *)
1638 pkt)->total_byte_count));
1639 } else {
1640 ql_dbg(ql_dbg_user, vha, 0x5040,
1641 "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
1642 "error subcode 1=0x%x error subcode 2=0x%x.\n",
1643 type, sp->handle, comp_status,
1644 le16_to_cpu(((struct els_sts_entry_24xx *)
1645 pkt)->error_subcode_1),
1646 le16_to_cpu(((struct els_sts_entry_24xx *)
1647 pkt)->error_subcode_2));
1648 res = DID_ERROR << 16;
1649 bsg_reply->reply_payload_rcv_len = 0;
1650 }
1651 memcpy(bsg_job->reply + sizeof(struct fc_bsg_reply),
1652 fw_status, sizeof(fw_status));
1653 ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
1654 (uint8_t *)pkt, sizeof(*pkt));
1655 }
1656 else {
1657 res = DID_OK << 16;
1658 bsg_reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
1659 bsg_job->reply_len = 0;
1660 }
1661els_ct_done:
1662
1663 sp->done(sp, res);
1664}
1665
1666static void
1667qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
1668 struct logio_entry_24xx *logio)
1669{
1670 const char func[] = "LOGIO-IOCB";
1671 const char *type;
1672 fc_port_t *fcport;
1673 srb_t *sp;
1674 struct srb_iocb *lio;
1675 uint16_t *data;
1676 uint32_t iop[2];
1677
1678 sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
1679 if (!sp)
1680 return;
1681
1682 lio = &sp->u.iocb_cmd;
1683 type = sp->name;
1684 fcport = sp->fcport;
1685 data = lio->u.logio.data;
1686
1687 data[0] = MBS_COMMAND_ERROR;
1688 data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
1689 QLA_LOGIO_LOGIN_RETRIED : 0;
1690 if (logio->entry_status) {
1691 ql_log(ql_log_warn, fcport->vha, 0x5034,
1692 "Async-%s error entry - %8phC hdl=%x"
1693 "portid=%02x%02x%02x entry-status=%x.\n",
1694 type, fcport->port_name, sp->handle, fcport->d_id.b.domain,
1695 fcport->d_id.b.area, fcport->d_id.b.al_pa,
1696 logio->entry_status);
1697 ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
1698 (uint8_t *)logio, sizeof(*logio));
1699
1700 goto logio_done;
1701 }
1702
1703 if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
1704 ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
1705 "Async-%s complete - %8phC hdl=%x portid=%02x%02x%02x "
1706 "iop0=%x.\n", type, fcport->port_name, sp->handle,
1707 fcport->d_id.b.domain,
1708 fcport->d_id.b.area, fcport->d_id.b.al_pa,
1709 le32_to_cpu(logio->io_parameter[0]));
1710
1711 vha->hw->exch_starvation = 0;
1712 data[0] = MBS_COMMAND_COMPLETE;
1713 if (sp->type != SRB_LOGIN_CMD)
1714 goto logio_done;
1715
1716 iop[0] = le32_to_cpu(logio->io_parameter[0]);
1717 if (iop[0] & BIT_4) {
1718 fcport->port_type = FCT_TARGET;
1719 if (iop[0] & BIT_8)
1720 fcport->flags |= FCF_FCP2_DEVICE;
1721 } else if (iop[0] & BIT_5)
1722 fcport->port_type = FCT_INITIATOR;
1723
1724 if (iop[0] & BIT_7)
1725 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1726
1727 if (logio->io_parameter[7] || logio->io_parameter[8])
1728 fcport->supported_classes |= FC_COS_CLASS2;
1729 if (logio->io_parameter[9] || logio->io_parameter[10])
1730 fcport->supported_classes |= FC_COS_CLASS3;
1731
1732 goto logio_done;
1733 }
1734
1735 iop[0] = le32_to_cpu(logio->io_parameter[0]);
1736 iop[1] = le32_to_cpu(logio->io_parameter[1]);
1737 lio->u.logio.iop[0] = iop[0];
1738 lio->u.logio.iop[1] = iop[1];
1739 switch (iop[0]) {
1740 case LSC_SCODE_PORTID_USED:
1741 data[0] = MBS_PORT_ID_USED;
1742 data[1] = LSW(iop[1]);
1743 break;
1744 case LSC_SCODE_NPORT_USED:
1745 data[0] = MBS_LOOP_ID_USED;
1746 break;
1747 case LSC_SCODE_CMD_FAILED:
1748 if (iop[1] == 0x0606) {
1749
1750
1751
1752
1753 data[0] = MBS_COMMAND_COMPLETE;
1754 goto logio_done;
1755 }
1756 data[0] = MBS_COMMAND_ERROR;
1757 break;
1758 case LSC_SCODE_NOXCB:
1759 vha->hw->exch_starvation++;
1760 if (vha->hw->exch_starvation > 5) {
1761 ql_log(ql_log_warn, vha, 0xd046,
1762 "Exchange starvation. Resetting RISC\n");
1763
1764 vha->hw->exch_starvation = 0;
1765
1766 if (IS_P3P_TYPE(vha->hw))
1767 set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
1768 else
1769 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1770 qla2xxx_wake_dpc(vha);
1771 }
1772
1773 default:
1774 data[0] = MBS_COMMAND_ERROR;
1775 break;
1776 }
1777
1778 ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
1779 "Async-%s failed - %8phC hdl=%x portid=%02x%02x%02x comp=%x "
1780 "iop0=%x iop1=%x.\n", type, fcport->port_name,
1781 sp->handle, fcport->d_id.b.domain,
1782 fcport->d_id.b.area, fcport->d_id.b.al_pa,
1783 le16_to_cpu(logio->comp_status),
1784 le32_to_cpu(logio->io_parameter[0]),
1785 le32_to_cpu(logio->io_parameter[1]));
1786
1787logio_done:
1788 sp->done(sp, 0);
1789}
1790
1791static void
1792qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
1793{
1794 const char func[] = "TMF-IOCB";
1795 const char *type;
1796 fc_port_t *fcport;
1797 srb_t *sp;
1798 struct srb_iocb *iocb;
1799 struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
1800
1801 sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
1802 if (!sp)
1803 return;
1804
1805 iocb = &sp->u.iocb_cmd;
1806 type = sp->name;
1807 fcport = sp->fcport;
1808 iocb->u.tmf.data = QLA_SUCCESS;
1809
1810 if (sts->entry_status) {
1811 ql_log(ql_log_warn, fcport->vha, 0x5038,
1812 "Async-%s error - hdl=%x entry-status(%x).\n",
1813 type, sp->handle, sts->entry_status);
1814 iocb->u.tmf.data = QLA_FUNCTION_FAILED;
1815 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
1816 ql_log(ql_log_warn, fcport->vha, 0x5039,
1817 "Async-%s error - hdl=%x completion status(%x).\n",
1818 type, sp->handle, sts->comp_status);
1819 iocb->u.tmf.data = QLA_FUNCTION_FAILED;
1820 } else if ((le16_to_cpu(sts->scsi_status) &
1821 SS_RESPONSE_INFO_LEN_VALID)) {
1822 if (le32_to_cpu(sts->rsp_data_len) < 4) {
1823 ql_log(ql_log_warn, fcport->vha, 0x503b,
1824 "Async-%s error - hdl=%x not enough response(%d).\n",
1825 type, sp->handle, sts->rsp_data_len);
1826 } else if (sts->data[3]) {
1827 ql_log(ql_log_warn, fcport->vha, 0x503c,
1828 "Async-%s error - hdl=%x response(%x).\n",
1829 type, sp->handle, sts->data[3]);
1830 iocb->u.tmf.data = QLA_FUNCTION_FAILED;
1831 }
1832 }
1833
1834 if (iocb->u.tmf.data != QLA_SUCCESS)
1835 ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
1836 (uint8_t *)sts, sizeof(*sts));
1837
1838 sp->done(sp, 0);
1839}
1840
1841static void
1842qla24xx_nvme_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
1843{
1844 const char func[] = "NVME-IOCB";
1845 fc_port_t *fcport;
1846 srb_t *sp;
1847 struct srb_iocb *iocb;
1848 struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
1849 uint16_t state_flags;
1850 struct nvmefc_fcp_req *fd;
1851 uint16_t ret = 0;
1852 struct srb_iocb *nvme;
1853
1854 sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
1855 if (!sp)
1856 return;
1857
1858 iocb = &sp->u.iocb_cmd;
1859 fcport = sp->fcport;
1860 iocb->u.nvme.comp_status = le16_to_cpu(sts->comp_status);
1861 state_flags = le16_to_cpu(sts->state_flags);
1862 fd = iocb->u.nvme.desc;
1863 nvme = &sp->u.iocb_cmd;
1864
1865 if (unlikely(nvme->u.nvme.aen_op))
1866 atomic_dec(&sp->vha->hw->nvme_active_aen_cnt);
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876 if (!(state_flags & (SF_FCP_RSP_DMA | SF_NVME_ERSP))) {
1877 iocb->u.nvme.rsp_pyld_len = 0;
1878 } else if ((state_flags & SF_FCP_RSP_DMA)) {
1879 iocb->u.nvme.rsp_pyld_len = le16_to_cpu(sts->nvme_rsp_pyld_len);
1880 } else if (state_flags & SF_NVME_ERSP) {
1881 uint32_t *inbuf, *outbuf;
1882 uint16_t iter;
1883
1884 inbuf = (uint32_t *)&sts->nvme_ersp_data;
1885 outbuf = (uint32_t *)fd->rspaddr;
1886 iocb->u.nvme.rsp_pyld_len = le16_to_cpu(sts->nvme_rsp_pyld_len);
1887 iter = iocb->u.nvme.rsp_pyld_len >> 2;
1888 for (; iter; iter--)
1889 *outbuf++ = swab32(*inbuf++);
1890 } else {
1891 ql_log(ql_log_warn, fcport->vha, 0x503a,
1892 "NVME-%s error. Unhandled state_flags of %x\n",
1893 sp->name, state_flags);
1894 }
1895
1896 fd->transferred_length = fd->payload_length -
1897 le32_to_cpu(sts->residual_len);
1898
1899
1900
1901
1902
1903 if (sts->entry_status) {
1904 ql_log(ql_log_warn, fcport->vha, 0x5038,
1905 "NVME-%s error - hdl=%x entry-status(%x).\n",
1906 sp->name, sp->handle, sts->entry_status);
1907 ret = QLA_FUNCTION_FAILED;
1908 } else {
1909 switch (le16_to_cpu(sts->comp_status)) {
1910 case CS_COMPLETE:
1911 ret = 0;
1912 break;
1913
1914 case CS_ABORTED:
1915 case CS_RESET:
1916 case CS_PORT_UNAVAILABLE:
1917 case CS_PORT_LOGGED_OUT:
1918 case CS_PORT_BUSY:
1919 ql_log(ql_log_warn, fcport->vha, 0x5060,
1920 "NVME-%s ERR Handling - hdl=%x completion status(%x) resid=%x ox_id=%x\n",
1921 sp->name, sp->handle, sts->comp_status,
1922 le32_to_cpu(sts->residual_len), sts->ox_id);
1923 fd->transferred_length = fd->payload_length;
1924 ret = QLA_ABORTED;
1925 break;
1926
1927 default:
1928 ql_log(ql_log_warn, fcport->vha, 0x5060,
1929 "NVME-%s error - hdl=%x completion status(%x) resid=%x ox_id=%x\n",
1930 sp->name, sp->handle, sts->comp_status,
1931 le32_to_cpu(sts->residual_len), sts->ox_id);
1932 ret = QLA_FUNCTION_FAILED;
1933 break;
1934 }
1935 }
1936 sp->done(sp, ret);
1937}
1938
1939
1940
1941
1942
1943void
1944qla2x00_process_response_queue(struct rsp_que *rsp)
1945{
1946 struct scsi_qla_host *vha;
1947 struct qla_hw_data *ha = rsp->hw;
1948 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1949 sts_entry_t *pkt;
1950 uint16_t handle_cnt;
1951 uint16_t cnt;
1952
1953 vha = pci_get_drvdata(ha->pdev);
1954
1955 if (!vha->flags.online)
1956 return;
1957
1958 while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
1959 pkt = (sts_entry_t *)rsp->ring_ptr;
1960
1961 rsp->ring_index++;
1962 if (rsp->ring_index == rsp->length) {
1963 rsp->ring_index = 0;
1964 rsp->ring_ptr = rsp->ring;
1965 } else {
1966 rsp->ring_ptr++;
1967 }
1968
1969 if (pkt->entry_status != 0) {
1970 qla2x00_error_entry(vha, rsp, pkt);
1971 ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
1972 wmb();
1973 continue;
1974 }
1975
1976 switch (pkt->entry_type) {
1977 case STATUS_TYPE:
1978 qla2x00_status_entry(vha, rsp, pkt);
1979 break;
1980 case STATUS_TYPE_21:
1981 handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
1982 for (cnt = 0; cnt < handle_cnt; cnt++) {
1983 qla2x00_process_completed_request(vha, rsp->req,
1984 ((sts21_entry_t *)pkt)->handle[cnt]);
1985 }
1986 break;
1987 case STATUS_TYPE_22:
1988 handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
1989 for (cnt = 0; cnt < handle_cnt; cnt++) {
1990 qla2x00_process_completed_request(vha, rsp->req,
1991 ((sts22_entry_t *)pkt)->handle[cnt]);
1992 }
1993 break;
1994 case STATUS_CONT_TYPE:
1995 qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
1996 break;
1997 case MBX_IOCB_TYPE:
1998 qla2x00_mbx_iocb_entry(vha, rsp->req,
1999 (struct mbx_entry *)pkt);
2000 break;
2001 case CT_IOCB_TYPE:
2002 qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
2003 break;
2004 default:
2005
2006 ql_log(ql_log_warn, vha, 0x504a,
2007 "Received unknown response pkt type %x "
2008 "entry status=%x.\n",
2009 pkt->entry_type, pkt->entry_status);
2010 break;
2011 }
2012 ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
2013 wmb();
2014 }
2015
2016
2017 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
2018}
2019
2020static inline void
2021qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
2022 uint32_t sense_len, struct rsp_que *rsp, int res)
2023{
2024 struct scsi_qla_host *vha = sp->vha;
2025 struct scsi_cmnd *cp = GET_CMD_SP(sp);
2026 uint32_t track_sense_len;
2027
2028 if (sense_len >= SCSI_SENSE_BUFFERSIZE)
2029 sense_len = SCSI_SENSE_BUFFERSIZE;
2030
2031 SET_CMD_SENSE_LEN(sp, sense_len);
2032 SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
2033 track_sense_len = sense_len;
2034
2035 if (sense_len > par_sense_len)
2036 sense_len = par_sense_len;
2037
2038 memcpy(cp->sense_buffer, sense_data, sense_len);
2039
2040 SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
2041 track_sense_len -= sense_len;
2042 SET_CMD_SENSE_LEN(sp, track_sense_len);
2043
2044 if (track_sense_len != 0) {
2045 rsp->status_srb = sp;
2046 cp->result = res;
2047 }
2048
2049 if (sense_len) {
2050 ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
2051 "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
2052 sp->vha->host_no, cp->device->id, cp->device->lun,
2053 cp);
2054 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
2055 cp->sense_buffer, sense_len);
2056 }
2057}
2058
2059struct scsi_dif_tuple {
2060 __be16 guard;
2061 __be16 app_tag;
2062 __be32 ref_tag;
2063};
2064
2065
2066
2067
2068
2069
2070
2071static inline int
2072qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
2073{
2074 struct scsi_qla_host *vha = sp->vha;
2075 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
2076 uint8_t *ap = &sts24->data[12];
2077 uint8_t *ep = &sts24->data[20];
2078 uint32_t e_ref_tag, a_ref_tag;
2079 uint16_t e_app_tag, a_app_tag;
2080 uint16_t e_guard, a_guard;
2081
2082
2083
2084
2085
2086 a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
2087 a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
2088 a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
2089 e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
2090 e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
2091 e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
2092
2093 ql_dbg(ql_dbg_io, vha, 0x3023,
2094 "iocb(s) %p Returned STATUS.\n", sts24);
2095
2096 ql_dbg(ql_dbg_io, vha, 0x3024,
2097 "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
2098 " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
2099 " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
2100 cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
2101 a_app_tag, e_app_tag, a_guard, e_guard);
2102
2103
2104
2105
2106
2107
2108 if ((a_app_tag == T10_PI_APP_ESCAPE) &&
2109 ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
2110 (a_ref_tag == T10_PI_REF_ESCAPE))) {
2111 uint32_t blocks_done, resid;
2112 sector_t lba_s = scsi_get_lba(cmd);
2113
2114
2115 blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
2116
2117 resid = scsi_bufflen(cmd) - (blocks_done *
2118 cmd->device->sector_size);
2119
2120 scsi_set_resid(cmd, resid);
2121 cmd->result = DID_OK << 16;
2122
2123
2124 if (scsi_prot_sg_count(cmd)) {
2125 uint32_t i, j = 0, k = 0, num_ent;
2126 struct scatterlist *sg;
2127 struct t10_pi_tuple *spt;
2128
2129
2130 scsi_for_each_prot_sg(cmd, sg,
2131 scsi_prot_sg_count(cmd), i) {
2132 num_ent = sg_dma_len(sg) / 8;
2133 if (k + num_ent < blocks_done) {
2134 k += num_ent;
2135 continue;
2136 }
2137 j = blocks_done - k - 1;
2138 k = blocks_done;
2139 break;
2140 }
2141
2142 if (k != blocks_done) {
2143 ql_log(ql_log_warn, vha, 0x302f,
2144 "unexpected tag values tag:lba=%x:%llx)\n",
2145 e_ref_tag, (unsigned long long)lba_s);
2146 return 1;
2147 }
2148
2149 spt = page_address(sg_page(sg)) + sg->offset;
2150 spt += j;
2151
2152 spt->app_tag = T10_PI_APP_ESCAPE;
2153 if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
2154 spt->ref_tag = T10_PI_REF_ESCAPE;
2155 }
2156
2157 return 0;
2158 }
2159
2160
2161 if (e_guard != a_guard) {
2162 scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
2163 0x10, 0x1);
2164 set_driver_byte(cmd, DRIVER_SENSE);
2165 set_host_byte(cmd, DID_ABORT);
2166 cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
2167 return 1;
2168 }
2169
2170
2171 if (e_ref_tag != a_ref_tag) {
2172 scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
2173 0x10, 0x3);
2174 set_driver_byte(cmd, DRIVER_SENSE);
2175 set_host_byte(cmd, DID_ABORT);
2176 cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
2177 return 1;
2178 }
2179
2180
2181 if (e_app_tag != a_app_tag) {
2182 scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
2183 0x10, 0x2);
2184 set_driver_byte(cmd, DRIVER_SENSE);
2185 set_host_byte(cmd, DID_ABORT);
2186 cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
2187 return 1;
2188 }
2189
2190 return 1;
2191}
2192
2193static void
2194qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
2195 struct req_que *req, uint32_t index)
2196{
2197 struct qla_hw_data *ha = vha->hw;
2198 srb_t *sp;
2199 uint16_t comp_status;
2200 uint16_t scsi_status;
2201 uint16_t thread_id;
2202 uint32_t rval = EXT_STATUS_OK;
2203 struct bsg_job *bsg_job = NULL;
2204 struct fc_bsg_request *bsg_request;
2205 struct fc_bsg_reply *bsg_reply;
2206 sts_entry_t *sts;
2207 struct sts_entry_24xx *sts24;
2208 sts = (sts_entry_t *) pkt;
2209 sts24 = (struct sts_entry_24xx *) pkt;
2210
2211
2212 if (index >= req->num_outstanding_cmds) {
2213 ql_log(ql_log_warn, vha, 0x70af,
2214 "Invalid SCSI completion handle 0x%x.\n", index);
2215 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2216 return;
2217 }
2218
2219 sp = req->outstanding_cmds[index];
2220 if (!sp) {
2221 ql_log(ql_log_warn, vha, 0x70b0,
2222 "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
2223 req->id, index);
2224
2225 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2226 return;
2227 }
2228
2229
2230 req->outstanding_cmds[index] = NULL;
2231 bsg_job = sp->u.bsg_job;
2232 bsg_request = bsg_job->request;
2233 bsg_reply = bsg_job->reply;
2234
2235 if (IS_FWI2_CAPABLE(ha)) {
2236 comp_status = le16_to_cpu(sts24->comp_status);
2237 scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
2238 } else {
2239 comp_status = le16_to_cpu(sts->comp_status);
2240 scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
2241 }
2242
2243 thread_id = bsg_request->rqst_data.h_vendor.vendor_cmd[1];
2244 switch (comp_status) {
2245 case CS_COMPLETE:
2246 if (scsi_status == 0) {
2247 bsg_reply->reply_payload_rcv_len =
2248 bsg_job->reply_payload.payload_len;
2249 vha->qla_stats.input_bytes +=
2250 bsg_reply->reply_payload_rcv_len;
2251 vha->qla_stats.input_requests++;
2252 rval = EXT_STATUS_OK;
2253 }
2254 goto done;
2255
2256 case CS_DATA_OVERRUN:
2257 ql_dbg(ql_dbg_user, vha, 0x70b1,
2258 "Command completed with data overrun thread_id=%d\n",
2259 thread_id);
2260 rval = EXT_STATUS_DATA_OVERRUN;
2261 break;
2262
2263 case CS_DATA_UNDERRUN:
2264 ql_dbg(ql_dbg_user, vha, 0x70b2,
2265 "Command completed with data underrun thread_id=%d\n",
2266 thread_id);
2267 rval = EXT_STATUS_DATA_UNDERRUN;
2268 break;
2269 case CS_BIDIR_RD_OVERRUN:
2270 ql_dbg(ql_dbg_user, vha, 0x70b3,
2271 "Command completed with read data overrun thread_id=%d\n",
2272 thread_id);
2273 rval = EXT_STATUS_DATA_OVERRUN;
2274 break;
2275
2276 case CS_BIDIR_RD_WR_OVERRUN:
2277 ql_dbg(ql_dbg_user, vha, 0x70b4,
2278 "Command completed with read and write data overrun "
2279 "thread_id=%d\n", thread_id);
2280 rval = EXT_STATUS_DATA_OVERRUN;
2281 break;
2282
2283 case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
2284 ql_dbg(ql_dbg_user, vha, 0x70b5,
2285 "Command completed with read data over and write data "
2286 "underrun thread_id=%d\n", thread_id);
2287 rval = EXT_STATUS_DATA_OVERRUN;
2288 break;
2289
2290 case CS_BIDIR_RD_UNDERRUN:
2291 ql_dbg(ql_dbg_user, vha, 0x70b6,
2292 "Command completed with read data underrun "
2293 "thread_id=%d\n", thread_id);
2294 rval = EXT_STATUS_DATA_UNDERRUN;
2295 break;
2296
2297 case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
2298 ql_dbg(ql_dbg_user, vha, 0x70b7,
2299 "Command completed with read data under and write data "
2300 "overrun thread_id=%d\n", thread_id);
2301 rval = EXT_STATUS_DATA_UNDERRUN;
2302 break;
2303
2304 case CS_BIDIR_RD_WR_UNDERRUN:
2305 ql_dbg(ql_dbg_user, vha, 0x70b8,
2306 "Command completed with read and write data underrun "
2307 "thread_id=%d\n", thread_id);
2308 rval = EXT_STATUS_DATA_UNDERRUN;
2309 break;
2310
2311 case CS_BIDIR_DMA:
2312 ql_dbg(ql_dbg_user, vha, 0x70b9,
2313 "Command completed with data DMA error thread_id=%d\n",
2314 thread_id);
2315 rval = EXT_STATUS_DMA_ERR;
2316 break;
2317
2318 case CS_TIMEOUT:
2319 ql_dbg(ql_dbg_user, vha, 0x70ba,
2320 "Command completed with timeout thread_id=%d\n",
2321 thread_id);
2322 rval = EXT_STATUS_TIMEOUT;
2323 break;
2324 default:
2325 ql_dbg(ql_dbg_user, vha, 0x70bb,
2326 "Command completed with completion status=0x%x "
2327 "thread_id=%d\n", comp_status, thread_id);
2328 rval = EXT_STATUS_ERR;
2329 break;
2330 }
2331 bsg_reply->reply_payload_rcv_len = 0;
2332
2333done:
2334
2335 bsg_reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
2336 bsg_job->reply_len = sizeof(struct fc_bsg_reply);
2337
2338
2339 sp->done(sp, DID_OK << 6);
2340
2341}
2342
2343
2344
2345
2346
2347
2348static void
2349qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
2350{
2351 srb_t *sp;
2352 fc_port_t *fcport;
2353 struct scsi_cmnd *cp;
2354 sts_entry_t *sts;
2355 struct sts_entry_24xx *sts24;
2356 uint16_t comp_status;
2357 uint16_t scsi_status;
2358 uint16_t ox_id;
2359 uint8_t lscsi_status;
2360 int32_t resid;
2361 uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
2362 fw_resid_len;
2363 uint8_t *rsp_info, *sense_data;
2364 struct qla_hw_data *ha = vha->hw;
2365 uint32_t handle;
2366 uint16_t que;
2367 struct req_que *req;
2368 int logit = 1;
2369 int res = 0;
2370 uint16_t state_flags = 0;
2371 uint16_t retry_delay = 0;
2372 uint8_t no_logout = 0;
2373
2374 sts = (sts_entry_t *) pkt;
2375 sts24 = (struct sts_entry_24xx *) pkt;
2376 if (IS_FWI2_CAPABLE(ha)) {
2377 comp_status = le16_to_cpu(sts24->comp_status);
2378 scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
2379 state_flags = le16_to_cpu(sts24->state_flags);
2380 } else {
2381 comp_status = le16_to_cpu(sts->comp_status);
2382 scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
2383 }
2384 handle = (uint32_t) LSW(sts->handle);
2385 que = MSW(sts->handle);
2386 req = ha->req_q_map[que];
2387
2388
2389 if (req == NULL ||
2390 que >= find_first_zero_bit(ha->req_qid_map, ha->max_req_queues)) {
2391 ql_dbg(ql_dbg_io, vha, 0x3059,
2392 "Invalid status handle (0x%x): Bad req pointer. req=%p, "
2393 "que=%u.\n", sts->handle, req, que);
2394 return;
2395 }
2396
2397
2398 if (handle < req->num_outstanding_cmds) {
2399 sp = req->outstanding_cmds[handle];
2400 if (!sp) {
2401 ql_dbg(ql_dbg_io, vha, 0x3075,
2402 "%s(%ld): Already returned command for status handle (0x%x).\n",
2403 __func__, vha->host_no, sts->handle);
2404 return;
2405 }
2406 } else {
2407 ql_dbg(ql_dbg_io, vha, 0x3017,
2408 "Invalid status handle, out of range (0x%x).\n",
2409 sts->handle);
2410
2411 if (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
2412 if (IS_P3P_TYPE(ha))
2413 set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
2414 else
2415 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2416 qla2xxx_wake_dpc(vha);
2417 }
2418 return;
2419 }
2420
2421 if (sp->cmd_type != TYPE_SRB) {
2422 req->outstanding_cmds[handle] = NULL;
2423 ql_dbg(ql_dbg_io, vha, 0x3015,
2424 "Unknown sp->cmd_type %x %p).\n",
2425 sp->cmd_type, sp);
2426 return;
2427 }
2428
2429
2430 if (sp->type == SRB_NVME_CMD) {
2431 qla24xx_nvme_iocb_entry(vha, req, pkt);
2432 return;
2433 }
2434
2435 if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
2436 qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
2437 return;
2438 }
2439
2440
2441 if (sp->type == SRB_TM_CMD) {
2442 qla24xx_tm_iocb_entry(vha, req, pkt);
2443 return;
2444 }
2445
2446
2447 if (comp_status == CS_COMPLETE && scsi_status == 0) {
2448 qla2x00_process_completed_request(vha, req, handle);
2449
2450 return;
2451 }
2452
2453 req->outstanding_cmds[handle] = NULL;
2454 cp = GET_CMD_SP(sp);
2455 if (cp == NULL) {
2456 ql_dbg(ql_dbg_io, vha, 0x3018,
2457 "Command already returned (0x%x/%p).\n",
2458 sts->handle, sp);
2459
2460 return;
2461 }
2462
2463 lscsi_status = scsi_status & STATUS_MASK;
2464
2465 fcport = sp->fcport;
2466
2467 ox_id = 0;
2468 sense_len = par_sense_len = rsp_info_len = resid_len =
2469 fw_resid_len = 0;
2470 if (IS_FWI2_CAPABLE(ha)) {
2471 if (scsi_status & SS_SENSE_LEN_VALID)
2472 sense_len = le32_to_cpu(sts24->sense_len);
2473 if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
2474 rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
2475 if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
2476 resid_len = le32_to_cpu(sts24->rsp_residual_count);
2477 if (comp_status == CS_DATA_UNDERRUN)
2478 fw_resid_len = le32_to_cpu(sts24->residual_len);
2479 rsp_info = sts24->data;
2480 sense_data = sts24->data;
2481 host_to_fcp_swap(sts24->data, sizeof(sts24->data));
2482 ox_id = le16_to_cpu(sts24->ox_id);
2483 par_sense_len = sizeof(sts24->data);
2484
2485 if (sts24->retry_delay > 0 && sts24->retry_delay < 0xfff1)
2486 retry_delay = sts24->retry_delay;
2487 } else {
2488 if (scsi_status & SS_SENSE_LEN_VALID)
2489 sense_len = le16_to_cpu(sts->req_sense_length);
2490 if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
2491 rsp_info_len = le16_to_cpu(sts->rsp_info_len);
2492 resid_len = le32_to_cpu(sts->residual_length);
2493 rsp_info = sts->rsp_info;
2494 sense_data = sts->req_sense_data;
2495 par_sense_len = sizeof(sts->req_sense_data);
2496 }
2497
2498
2499 if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
2500
2501 if (IS_FWI2_CAPABLE(ha)) {
2502 sense_data += rsp_info_len;
2503 par_sense_len -= rsp_info_len;
2504 }
2505 if (rsp_info_len > 3 && rsp_info[3]) {
2506 ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
2507 "FCP I/O protocol failure (0x%x/0x%x).\n",
2508 rsp_info_len, rsp_info[3]);
2509
2510 res = DID_BUS_BUSY << 16;
2511 goto out;
2512 }
2513 }
2514
2515
2516 if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
2517 scsi_status & SS_RESIDUAL_OVER)
2518 comp_status = CS_DATA_OVERRUN;
2519
2520
2521
2522
2523
2524 if (lscsi_status == SAM_STAT_TASK_SET_FULL ||
2525 lscsi_status == SAM_STAT_BUSY)
2526 qla2x00_set_retry_delay_timestamp(fcport, retry_delay);
2527
2528
2529
2530
2531 switch (comp_status) {
2532 case CS_COMPLETE:
2533 case CS_QUEUE_FULL:
2534 if (scsi_status == 0) {
2535 res = DID_OK << 16;
2536 break;
2537 }
2538 if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
2539 resid = resid_len;
2540 scsi_set_resid(cp, resid);
2541
2542 if (!lscsi_status &&
2543 ((unsigned)(scsi_bufflen(cp) - resid) <
2544 cp->underflow)) {
2545 ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
2546 "Mid-layer underflow detected (0x%x of 0x%x bytes).\n",
2547 resid, scsi_bufflen(cp));
2548
2549 res = DID_ERROR << 16;
2550 break;
2551 }
2552 }
2553 res = DID_OK << 16 | lscsi_status;
2554
2555 if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
2556 ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
2557 "QUEUE FULL detected.\n");
2558 break;
2559 }
2560 logit = 0;
2561 if (lscsi_status != SS_CHECK_CONDITION)
2562 break;
2563
2564 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2565 if (!(scsi_status & SS_SENSE_LEN_VALID))
2566 break;
2567
2568 qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
2569 rsp, res);
2570 break;
2571
2572 case CS_DATA_UNDERRUN:
2573
2574 resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
2575 scsi_set_resid(cp, resid);
2576 if (scsi_status & SS_RESIDUAL_UNDER) {
2577 if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
2578 ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
2579 "Dropped frame(s) detected (0x%x of 0x%x bytes).\n",
2580 resid, scsi_bufflen(cp));
2581
2582 res = DID_ERROR << 16 | lscsi_status;
2583 goto check_scsi_status;
2584 }
2585
2586 if (!lscsi_status &&
2587 ((unsigned)(scsi_bufflen(cp) - resid) <
2588 cp->underflow)) {
2589 ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
2590 "Mid-layer underflow detected (0x%x of 0x%x bytes).\n",
2591 resid, scsi_bufflen(cp));
2592
2593 res = DID_ERROR << 16;
2594 break;
2595 }
2596 } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
2597 lscsi_status != SAM_STAT_BUSY) {
2598
2599
2600
2601
2602
2603 ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
2604 "Dropped frame(s) detected (0x%x of 0x%x bytes).\n",
2605 resid, scsi_bufflen(cp));
2606
2607 res = DID_ERROR << 16 | lscsi_status;
2608 goto check_scsi_status;
2609 } else {
2610 ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
2611 "scsi_status: 0x%x, lscsi_status: 0x%x\n",
2612 scsi_status, lscsi_status);
2613 }
2614
2615 res = DID_OK << 16 | lscsi_status;
2616 logit = 0;
2617
2618check_scsi_status:
2619
2620
2621
2622
2623 if (lscsi_status != 0) {
2624 if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
2625 ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
2626 "QUEUE FULL detected.\n");
2627 logit = 1;
2628 break;
2629 }
2630 if (lscsi_status != SS_CHECK_CONDITION)
2631 break;
2632
2633 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2634 if (!(scsi_status & SS_SENSE_LEN_VALID))
2635 break;
2636
2637 qla2x00_handle_sense(sp, sense_data, par_sense_len,
2638 sense_len, rsp, res);
2639 }
2640 break;
2641
2642 case CS_PORT_LOGGED_OUT:
2643 no_logout = 1;
2644 case CS_PORT_CONFIG_CHG:
2645 case CS_PORT_BUSY:
2646 case CS_INCOMPLETE:
2647 case CS_PORT_UNAVAILABLE:
2648 case CS_TIMEOUT:
2649 case CS_RESET:
2650
2651
2652
2653
2654
2655
2656 res = DID_TRANSPORT_DISRUPTED << 16;
2657
2658 if (comp_status == CS_TIMEOUT) {
2659 if (IS_FWI2_CAPABLE(ha))
2660 break;
2661 else if ((le16_to_cpu(sts->status_flags) &
2662 SF_LOGOUT_SENT) == 0)
2663 break;
2664 }
2665
2666 if (atomic_read(&fcport->state) == FCS_ONLINE) {
2667 ql_dbg(ql_dbg_disc, fcport->vha, 0x3021,
2668 "Port to be marked lost on fcport=%02x%02x%02x, current "
2669 "port state= %s comp_status %x.\n", fcport->d_id.b.domain,
2670 fcport->d_id.b.area, fcport->d_id.b.al_pa,
2671 port_state_str[atomic_read(&fcport->state)],
2672 comp_status);
2673
2674 if (no_logout)
2675 fcport->logout_on_delete = 0;
2676
2677 qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
2678 qlt_schedule_sess_for_deletion_lock(fcport);
2679 }
2680
2681 break;
2682
2683 case CS_ABORTED:
2684 res = DID_RESET << 16;
2685 break;
2686
2687 case CS_DIF_ERROR:
2688 logit = qla2x00_handle_dif_error(sp, sts24);
2689 res = cp->result;
2690 break;
2691
2692 case CS_TRANSPORT:
2693 res = DID_ERROR << 16;
2694
2695 if (!IS_PI_SPLIT_DET_CAPABLE(ha))
2696 break;
2697
2698 if (state_flags & BIT_4)
2699 scmd_printk(KERN_WARNING, cp,
2700 "Unsupported device '%s' found.\n",
2701 cp->device->vendor);
2702 break;
2703
2704 default:
2705 res = DID_ERROR << 16;
2706 break;
2707 }
2708
2709out:
2710 if (logit)
2711 ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
2712 "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
2713 "portid=%02x%02x%02x oxid=0x%x cdb=%10phN len=0x%x "
2714 "rsp_info=0x%x resid=0x%x fw_resid=0x%x sp=%p cp=%p.\n",
2715 comp_status, scsi_status, res, vha->host_no,
2716 cp->device->id, cp->device->lun, fcport->d_id.b.domain,
2717 fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
2718 cp->cmnd, scsi_bufflen(cp), rsp_info_len,
2719 resid_len, fw_resid_len, sp, cp);
2720
2721 if (rsp->status_srb == NULL)
2722 sp->done(sp, res);
2723}
2724
2725
2726
2727
2728
2729
2730
2731
2732static void
2733qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
2734{
2735 uint8_t sense_sz = 0;
2736 struct qla_hw_data *ha = rsp->hw;
2737 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
2738 srb_t *sp = rsp->status_srb;
2739 struct scsi_cmnd *cp;
2740 uint32_t sense_len;
2741 uint8_t *sense_ptr;
2742
2743 if (!sp || !GET_CMD_SENSE_LEN(sp))
2744 return;
2745
2746 sense_len = GET_CMD_SENSE_LEN(sp);
2747 sense_ptr = GET_CMD_SENSE_PTR(sp);
2748
2749 cp = GET_CMD_SP(sp);
2750 if (cp == NULL) {
2751 ql_log(ql_log_warn, vha, 0x3025,
2752 "cmd is NULL: already returned to OS (sp=%p).\n", sp);
2753
2754 rsp->status_srb = NULL;
2755 return;
2756 }
2757
2758 if (sense_len > sizeof(pkt->data))
2759 sense_sz = sizeof(pkt->data);
2760 else
2761 sense_sz = sense_len;
2762
2763
2764 if (IS_FWI2_CAPABLE(ha))
2765 host_to_fcp_swap(pkt->data, sizeof(pkt->data));
2766 memcpy(sense_ptr, pkt->data, sense_sz);
2767 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
2768 sense_ptr, sense_sz);
2769
2770 sense_len -= sense_sz;
2771 sense_ptr += sense_sz;
2772
2773 SET_CMD_SENSE_PTR(sp, sense_ptr);
2774 SET_CMD_SENSE_LEN(sp, sense_len);
2775
2776
2777 if (sense_len == 0) {
2778 rsp->status_srb = NULL;
2779 sp->done(sp, cp->result);
2780 }
2781}
2782
2783
2784
2785
2786
2787
2788
2789static int
2790qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
2791{
2792 srb_t *sp;
2793 struct qla_hw_data *ha = vha->hw;
2794 const char func[] = "ERROR-IOCB";
2795 uint16_t que = MSW(pkt->handle);
2796 struct req_que *req = NULL;
2797 int res = DID_ERROR << 16;
2798
2799 ql_dbg(ql_dbg_async, vha, 0x502a,
2800 "iocb type %xh with error status %xh, handle %xh, rspq id %d\n",
2801 pkt->entry_type, pkt->entry_status, pkt->handle, rsp->id);
2802
2803 if (que >= ha->max_req_queues || !ha->req_q_map[que])
2804 goto fatal;
2805
2806 req = ha->req_q_map[que];
2807
2808 if (pkt->entry_status & RF_BUSY)
2809 res = DID_BUS_BUSY << 16;
2810
2811 if ((pkt->handle & ~QLA_TGT_HANDLE_MASK) == QLA_TGT_SKIP_HANDLE)
2812 return 0;
2813
2814 switch (pkt->entry_type) {
2815 case NOTIFY_ACK_TYPE:
2816 case STATUS_TYPE:
2817 case STATUS_CONT_TYPE:
2818 case LOGINOUT_PORT_IOCB_TYPE:
2819 case CT_IOCB_TYPE:
2820 case ELS_IOCB_TYPE:
2821 case ABORT_IOCB_TYPE:
2822 case MBX_IOCB_TYPE:
2823 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2824 if (sp) {
2825 sp->done(sp, res);
2826 return 0;
2827 }
2828 break;
2829
2830 case ABTS_RESP_24XX:
2831 case CTIO_TYPE7:
2832 case CTIO_CRC2:
2833 default:
2834 return 1;
2835 }
2836fatal:
2837 ql_log(ql_log_warn, vha, 0x5030,
2838 "Error entry - invalid handle/queue (%04x).\n", que);
2839 return 0;
2840}
2841
2842
2843
2844
2845
2846
2847static void
2848qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
2849{
2850 uint16_t cnt;
2851 uint32_t mboxes;
2852 uint16_t __iomem *wptr;
2853 struct qla_hw_data *ha = vha->hw;
2854 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2855
2856
2857 mboxes = (1 << ha->mbx_count) - 1;
2858 if (!ha->mcp)
2859 ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
2860 else
2861 mboxes = ha->mcp->in_mb;
2862
2863
2864 ha->flags.mbox_int = 1;
2865 ha->mailbox_out[0] = mb0;
2866 mboxes >>= 1;
2867 wptr = (uint16_t __iomem *)®->mailbox1;
2868
2869 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2870 if (mboxes & BIT_0)
2871 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
2872
2873 mboxes >>= 1;
2874 wptr++;
2875 }
2876}
2877
2878static void
2879qla24xx_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2880 struct abort_entry_24xx *pkt)
2881{
2882 const char func[] = "ABT_IOCB";
2883 srb_t *sp;
2884 struct srb_iocb *abt;
2885
2886 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2887 if (!sp)
2888 return;
2889
2890 abt = &sp->u.iocb_cmd;
2891 abt->u.abt.comp_status = le16_to_cpu(pkt->nport_handle);
2892 sp->done(sp, 0);
2893}
2894
2895void qla24xx_nvme_ls4_iocb(struct scsi_qla_host *vha,
2896 struct pt_ls4_request *pkt, struct req_que *req)
2897{
2898 srb_t *sp;
2899 const char func[] = "LS4_IOCB";
2900 uint16_t comp_status;
2901
2902 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2903 if (!sp)
2904 return;
2905
2906 comp_status = le16_to_cpu(pkt->status);
2907 sp->done(sp, comp_status);
2908}
2909
2910
2911
2912
2913
2914void qla24xx_process_response_queue(struct scsi_qla_host *vha,
2915 struct rsp_que *rsp)
2916{
2917 struct sts_entry_24xx *pkt;
2918 struct qla_hw_data *ha = vha->hw;
2919
2920 if (!ha->flags.fw_started)
2921 return;
2922
2923 if (rsp->qpair->cpuid != smp_processor_id())
2924 qla_cpu_update(rsp->qpair, smp_processor_id());
2925
2926 while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
2927 pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
2928
2929 rsp->ring_index++;
2930 if (rsp->ring_index == rsp->length) {
2931 rsp->ring_index = 0;
2932 rsp->ring_ptr = rsp->ring;
2933 } else {
2934 rsp->ring_ptr++;
2935 }
2936
2937 if (pkt->entry_status != 0) {
2938 if (qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt))
2939 goto process_err;
2940
2941 ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
2942 wmb();
2943 continue;
2944 }
2945process_err:
2946
2947 switch (pkt->entry_type) {
2948 case STATUS_TYPE:
2949 qla2x00_status_entry(vha, rsp, pkt);
2950 break;
2951 case STATUS_CONT_TYPE:
2952 qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
2953 break;
2954 case VP_RPT_ID_IOCB_TYPE:
2955 qla24xx_report_id_acquisition(vha,
2956 (struct vp_rpt_id_entry_24xx *)pkt);
2957 break;
2958 case LOGINOUT_PORT_IOCB_TYPE:
2959 qla24xx_logio_entry(vha, rsp->req,
2960 (struct logio_entry_24xx *)pkt);
2961 break;
2962 case CT_IOCB_TYPE:
2963 qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
2964 break;
2965 case ELS_IOCB_TYPE:
2966 qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
2967 break;
2968 case ABTS_RECV_24XX:
2969 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2970
2971 qlt_handle_abts_recv(vha, rsp,
2972 (response_t *)pkt);
2973 break;
2974 } else {
2975
2976 qlt_24xx_process_atio_queue(vha, 1);
2977 }
2978 case ABTS_RESP_24XX:
2979 case CTIO_TYPE7:
2980 case CTIO_CRC2:
2981 qlt_response_pkt_all_vps(vha, rsp, (response_t *)pkt);
2982 break;
2983 case PT_LS4_REQUEST:
2984 qla24xx_nvme_ls4_iocb(vha, (struct pt_ls4_request *)pkt,
2985 rsp->req);
2986 break;
2987 case NOTIFY_ACK_TYPE:
2988 if (pkt->handle == QLA_TGT_SKIP_HANDLE)
2989 qlt_response_pkt_all_vps(vha, rsp,
2990 (response_t *)pkt);
2991 else
2992 qla24xxx_nack_iocb_entry(vha, rsp->req,
2993 (struct nack_to_isp *)pkt);
2994 break;
2995 case MARKER_TYPE:
2996
2997
2998
2999 break;
3000 case ABORT_IOCB_TYPE:
3001 qla24xx_abort_iocb_entry(vha, rsp->req,
3002 (struct abort_entry_24xx *)pkt);
3003 break;
3004 case MBX_IOCB_TYPE:
3005 qla24xx_mbx_iocb_entry(vha, rsp->req,
3006 (struct mbx_24xx_entry *)pkt);
3007 break;
3008 default:
3009
3010 ql_dbg(ql_dbg_async, vha, 0x5042,
3011 "Received unknown response pkt type %x "
3012 "entry status=%x.\n",
3013 pkt->entry_type, pkt->entry_status);
3014 break;
3015 }
3016 ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
3017 wmb();
3018 }
3019
3020
3021 if (IS_P3P_TYPE(ha)) {
3022 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
3023 WRT_REG_DWORD(®->rsp_q_out[0], rsp->ring_index);
3024 } else {
3025 WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
3026 }
3027}
3028
3029static void
3030qla2xxx_check_risc_status(scsi_qla_host_t *vha)
3031{
3032 int rval;
3033 uint32_t cnt;
3034 struct qla_hw_data *ha = vha->hw;
3035 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
3036
3037 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
3038 !IS_QLA27XX(ha))
3039 return;
3040
3041 rval = QLA_SUCCESS;
3042 WRT_REG_DWORD(®->iobase_addr, 0x7C00);
3043 RD_REG_DWORD(®->iobase_addr);
3044 WRT_REG_DWORD(®->iobase_window, 0x0001);
3045 for (cnt = 10000; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 &&
3046 rval == QLA_SUCCESS; cnt--) {
3047 if (cnt) {
3048 WRT_REG_DWORD(®->iobase_window, 0x0001);
3049 udelay(10);
3050 } else
3051 rval = QLA_FUNCTION_TIMEOUT;
3052 }
3053 if (rval == QLA_SUCCESS)
3054 goto next_test;
3055
3056 rval = QLA_SUCCESS;
3057 WRT_REG_DWORD(®->iobase_window, 0x0003);
3058 for (cnt = 100; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 &&
3059 rval == QLA_SUCCESS; cnt--) {
3060 if (cnt) {
3061 WRT_REG_DWORD(®->iobase_window, 0x0003);
3062 udelay(10);
3063 } else
3064 rval = QLA_FUNCTION_TIMEOUT;
3065 }
3066 if (rval != QLA_SUCCESS)
3067 goto done;
3068
3069next_test:
3070 if (RD_REG_DWORD(®->iobase_c8) & BIT_3)
3071 ql_log(ql_log_info, vha, 0x504c,
3072 "Additional code -- 0x55AA.\n");
3073
3074done:
3075 WRT_REG_DWORD(®->iobase_window, 0x0000);
3076 RD_REG_DWORD(®->iobase_window);
3077}
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088irqreturn_t
3089qla24xx_intr_handler(int irq, void *dev_id)
3090{
3091 scsi_qla_host_t *vha;
3092 struct qla_hw_data *ha;
3093 struct device_reg_24xx __iomem *reg;
3094 int status;
3095 unsigned long iter;
3096 uint32_t stat;
3097 uint32_t hccr;
3098 uint16_t mb[8];
3099 struct rsp_que *rsp;
3100 unsigned long flags;
3101
3102 rsp = (struct rsp_que *) dev_id;
3103 if (!rsp) {
3104 ql_log(ql_log_info, NULL, 0x5059,
3105 "%s: NULL response queue pointer.\n", __func__);
3106 return IRQ_NONE;
3107 }
3108
3109 ha = rsp->hw;
3110 reg = &ha->iobase->isp24;
3111 status = 0;
3112
3113 if (unlikely(pci_channel_offline(ha->pdev)))
3114 return IRQ_HANDLED;
3115
3116 spin_lock_irqsave(&ha->hardware_lock, flags);
3117 vha = pci_get_drvdata(ha->pdev);
3118 for (iter = 50; iter--; ) {
3119 stat = RD_REG_DWORD(®->host_status);
3120 if (qla2x00_check_reg32_for_disconnect(vha, stat))
3121 break;
3122 if (stat & HSRX_RISC_PAUSED) {
3123 if (unlikely(pci_channel_offline(ha->pdev)))
3124 break;
3125
3126 hccr = RD_REG_DWORD(®->hccr);
3127
3128 ql_log(ql_log_warn, vha, 0x504b,
3129 "RISC paused -- HCCR=%x, Dumping firmware.\n",
3130 hccr);
3131
3132 qla2xxx_check_risc_status(vha);
3133
3134 ha->isp_ops->fw_dump(vha, 1);
3135 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3136 break;
3137 } else if ((stat & HSRX_RISC_INT) == 0)
3138 break;
3139
3140 switch (stat & 0xff) {
3141 case INTR_ROM_MB_SUCCESS:
3142 case INTR_ROM_MB_FAILED:
3143 case INTR_MB_SUCCESS:
3144 case INTR_MB_FAILED:
3145 qla24xx_mbx_completion(vha, MSW(stat));
3146 status |= MBX_INTERRUPT;
3147
3148 break;
3149 case INTR_ASYNC_EVENT:
3150 mb[0] = MSW(stat);
3151 mb[1] = RD_REG_WORD(®->mailbox1);
3152 mb[2] = RD_REG_WORD(®->mailbox2);
3153 mb[3] = RD_REG_WORD(®->mailbox3);
3154 qla2x00_async_event(vha, rsp, mb);
3155 break;
3156 case INTR_RSP_QUE_UPDATE:
3157 case INTR_RSP_QUE_UPDATE_83XX:
3158 qla24xx_process_response_queue(vha, rsp);
3159 break;
3160 case INTR_ATIO_QUE_UPDATE_27XX:
3161 case INTR_ATIO_QUE_UPDATE:{
3162 unsigned long flags2;
3163 spin_lock_irqsave(&ha->tgt.atio_lock, flags2);
3164 qlt_24xx_process_atio_queue(vha, 1);
3165 spin_unlock_irqrestore(&ha->tgt.atio_lock, flags2);
3166 break;
3167 }
3168 case INTR_ATIO_RSP_QUE_UPDATE: {
3169 unsigned long flags2;
3170 spin_lock_irqsave(&ha->tgt.atio_lock, flags2);
3171 qlt_24xx_process_atio_queue(vha, 1);
3172 spin_unlock_irqrestore(&ha->tgt.atio_lock, flags2);
3173
3174 qla24xx_process_response_queue(vha, rsp);
3175 break;
3176 }
3177 default:
3178 ql_dbg(ql_dbg_async, vha, 0x504f,
3179 "Unrecognized interrupt type (%d).\n", stat * 0xff);
3180 break;
3181 }
3182 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
3183 RD_REG_DWORD_RELAXED(®->hccr);
3184 if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
3185 ndelay(3500);
3186 }
3187 qla2x00_handle_mbx_completion(ha, status);
3188 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3189
3190 return IRQ_HANDLED;
3191}
3192
3193static irqreturn_t
3194qla24xx_msix_rsp_q(int irq, void *dev_id)
3195{
3196 struct qla_hw_data *ha;
3197 struct rsp_que *rsp;
3198 struct device_reg_24xx __iomem *reg;
3199 struct scsi_qla_host *vha;
3200 unsigned long flags;
3201
3202 rsp = (struct rsp_que *) dev_id;
3203 if (!rsp) {
3204 ql_log(ql_log_info, NULL, 0x505a,
3205 "%s: NULL response queue pointer.\n", __func__);
3206 return IRQ_NONE;
3207 }
3208 ha = rsp->hw;
3209 reg = &ha->iobase->isp24;
3210
3211 spin_lock_irqsave(&ha->hardware_lock, flags);
3212
3213 vha = pci_get_drvdata(ha->pdev);
3214 qla24xx_process_response_queue(vha, rsp);
3215 if (!ha->flags.disable_msix_handshake) {
3216 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
3217 RD_REG_DWORD_RELAXED(®->hccr);
3218 }
3219 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3220
3221 return IRQ_HANDLED;
3222}
3223
3224static irqreturn_t
3225qla24xx_msix_default(int irq, void *dev_id)
3226{
3227 scsi_qla_host_t *vha;
3228 struct qla_hw_data *ha;
3229 struct rsp_que *rsp;
3230 struct device_reg_24xx __iomem *reg;
3231 int status;
3232 uint32_t stat;
3233 uint32_t hccr;
3234 uint16_t mb[8];
3235 unsigned long flags;
3236
3237 rsp = (struct rsp_que *) dev_id;
3238 if (!rsp) {
3239 ql_log(ql_log_info, NULL, 0x505c,
3240 "%s: NULL response queue pointer.\n", __func__);
3241 return IRQ_NONE;
3242 }
3243 ha = rsp->hw;
3244 reg = &ha->iobase->isp24;
3245 status = 0;
3246
3247 spin_lock_irqsave(&ha->hardware_lock, flags);
3248 vha = pci_get_drvdata(ha->pdev);
3249 do {
3250 stat = RD_REG_DWORD(®->host_status);
3251 if (qla2x00_check_reg32_for_disconnect(vha, stat))
3252 break;
3253 if (stat & HSRX_RISC_PAUSED) {
3254 if (unlikely(pci_channel_offline(ha->pdev)))
3255 break;
3256
3257 hccr = RD_REG_DWORD(®->hccr);
3258
3259 ql_log(ql_log_info, vha, 0x5050,
3260 "RISC paused -- HCCR=%x, Dumping firmware.\n",
3261 hccr);
3262
3263 qla2xxx_check_risc_status(vha);
3264
3265 ha->isp_ops->fw_dump(vha, 1);
3266 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3267 break;
3268 } else if ((stat & HSRX_RISC_INT) == 0)
3269 break;
3270
3271 switch (stat & 0xff) {
3272 case INTR_ROM_MB_SUCCESS:
3273 case INTR_ROM_MB_FAILED:
3274 case INTR_MB_SUCCESS:
3275 case INTR_MB_FAILED:
3276 qla24xx_mbx_completion(vha, MSW(stat));
3277 status |= MBX_INTERRUPT;
3278
3279 break;
3280 case INTR_ASYNC_EVENT:
3281 mb[0] = MSW(stat);
3282 mb[1] = RD_REG_WORD(®->mailbox1);
3283 mb[2] = RD_REG_WORD(®->mailbox2);
3284 mb[3] = RD_REG_WORD(®->mailbox3);
3285 qla2x00_async_event(vha, rsp, mb);
3286 break;
3287 case INTR_RSP_QUE_UPDATE:
3288 case INTR_RSP_QUE_UPDATE_83XX:
3289 qla24xx_process_response_queue(vha, rsp);
3290 break;
3291 case INTR_ATIO_QUE_UPDATE_27XX:
3292 case INTR_ATIO_QUE_UPDATE:{
3293 unsigned long flags2;
3294 spin_lock_irqsave(&ha->tgt.atio_lock, flags2);
3295 qlt_24xx_process_atio_queue(vha, 1);
3296 spin_unlock_irqrestore(&ha->tgt.atio_lock, flags2);
3297 break;
3298 }
3299 case INTR_ATIO_RSP_QUE_UPDATE: {
3300 unsigned long flags2;
3301 spin_lock_irqsave(&ha->tgt.atio_lock, flags2);
3302 qlt_24xx_process_atio_queue(vha, 1);
3303 spin_unlock_irqrestore(&ha->tgt.atio_lock, flags2);
3304
3305 qla24xx_process_response_queue(vha, rsp);
3306 break;
3307 }
3308 default:
3309 ql_dbg(ql_dbg_async, vha, 0x5051,
3310 "Unrecognized interrupt type (%d).\n", stat & 0xff);
3311 break;
3312 }
3313 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
3314 } while (0);
3315 qla2x00_handle_mbx_completion(ha, status);
3316 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3317
3318 return IRQ_HANDLED;
3319}
3320
3321irqreturn_t
3322qla2xxx_msix_rsp_q(int irq, void *dev_id)
3323{
3324 struct qla_hw_data *ha;
3325 struct qla_qpair *qpair;
3326 struct device_reg_24xx __iomem *reg;
3327 unsigned long flags;
3328
3329 qpair = dev_id;
3330 if (!qpair) {
3331 ql_log(ql_log_info, NULL, 0x505b,
3332 "%s: NULL response queue pointer.\n", __func__);
3333 return IRQ_NONE;
3334 }
3335 ha = qpair->hw;
3336
3337
3338 if (unlikely(!ha->flags.disable_msix_handshake)) {
3339 reg = &ha->iobase->isp24;
3340 spin_lock_irqsave(&ha->hardware_lock, flags);
3341 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
3342 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3343 }
3344
3345 queue_work(ha->wq, &qpair->q_work);
3346
3347 return IRQ_HANDLED;
3348}
3349
3350
3351
3352struct qla_init_msix_entry {
3353 const char *name;
3354 irq_handler_t handler;
3355};
3356
3357static const struct qla_init_msix_entry msix_entries[] = {
3358 { "default", qla24xx_msix_default },
3359 { "rsp_q", qla24xx_msix_rsp_q },
3360 { "atio_q", qla83xx_msix_atio_q },
3361 { "qpair_multiq", qla2xxx_msix_rsp_q },
3362};
3363
3364static const struct qla_init_msix_entry qla82xx_msix_entries[] = {
3365 { "qla2xxx (default)", qla82xx_msix_default },
3366 { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
3367};
3368
3369static int
3370qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
3371{
3372 int i, ret;
3373 struct qla_msix_entry *qentry;
3374 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
3375 int min_vecs = QLA_BASE_VECTORS;
3376 struct irq_affinity desc = {
3377 .pre_vectors = QLA_BASE_VECTORS,
3378 };
3379
3380 if (QLA_TGT_MODE_ENABLED() && (ql2xenablemsix != 0) &&
3381 IS_ATIO_MSIX_CAPABLE(ha)) {
3382 desc.pre_vectors++;
3383 min_vecs++;
3384 }
3385
3386 if (USER_CTRL_IRQ(ha)) {
3387
3388 ret = pci_alloc_irq_vectors(ha->pdev, min_vecs,
3389 ha->msix_count, PCI_IRQ_MSIX);
3390 } else
3391 ret = pci_alloc_irq_vectors_affinity(ha->pdev, min_vecs,
3392 ha->msix_count, PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
3393 &desc);
3394
3395 if (ret < 0) {
3396 ql_log(ql_log_fatal, vha, 0x00c7,
3397 "MSI-X: Failed to enable support, "
3398 "giving up -- %d/%d.\n",
3399 ha->msix_count, ret);
3400 goto msix_out;
3401 } else if (ret < ha->msix_count) {
3402 ql_log(ql_log_warn, vha, 0x00c6,
3403 "MSI-X: Failed to enable support "
3404 "with %d vectors, using %d vectors.\n",
3405 ha->msix_count, ret);
3406 ha->msix_count = ret;
3407
3408 if (ha->mqiobase && (ql2xmqsupport || ql2xnvmeenable)) {
3409 ha->max_req_queues = ha->msix_count - 1;
3410
3411
3412 if (QLA_TGT_MODE_ENABLED())
3413 ha->max_req_queues--;
3414
3415 ha->max_rsp_queues = ha->max_req_queues;
3416
3417 ha->max_qpairs = ha->max_req_queues - 1;
3418 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
3419 "Adjusted Max no of queues pairs: %d.\n", ha->max_qpairs);
3420 }
3421 }
3422 ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
3423 ha->msix_count, GFP_KERNEL);
3424 if (!ha->msix_entries) {
3425 ql_log(ql_log_fatal, vha, 0x00c8,
3426 "Failed to allocate memory for ha->msix_entries.\n");
3427 ret = -ENOMEM;
3428 goto msix_out;
3429 }
3430 ha->flags.msix_enabled = 1;
3431
3432 for (i = 0; i < ha->msix_count; i++) {
3433 qentry = &ha->msix_entries[i];
3434 qentry->vector = pci_irq_vector(ha->pdev, i);
3435 qentry->entry = i;
3436 qentry->have_irq = 0;
3437 qentry->in_use = 0;
3438 qentry->handle = NULL;
3439 }
3440
3441
3442 for (i = 0; i < QLA_BASE_VECTORS; i++) {
3443 qentry = &ha->msix_entries[i];
3444 qentry->handle = rsp;
3445 rsp->msix = qentry;
3446 scnprintf(qentry->name, sizeof(qentry->name),
3447 "qla2xxx%lu_%s", vha->host_no, msix_entries[i].name);
3448 if (IS_P3P_TYPE(ha))
3449 ret = request_irq(qentry->vector,
3450 qla82xx_msix_entries[i].handler,
3451 0, qla82xx_msix_entries[i].name, rsp);
3452 else
3453 ret = request_irq(qentry->vector,
3454 msix_entries[i].handler,
3455 0, qentry->name, rsp);
3456 if (ret)
3457 goto msix_register_fail;
3458 qentry->have_irq = 1;
3459 qentry->in_use = 1;
3460 }
3461
3462
3463
3464
3465
3466 if (QLA_TGT_MODE_ENABLED() && (ql2xenablemsix != 0) &&
3467 IS_ATIO_MSIX_CAPABLE(ha)) {
3468 qentry = &ha->msix_entries[QLA_ATIO_VECTOR];
3469 rsp->msix = qentry;
3470 qentry->handle = rsp;
3471 scnprintf(qentry->name, sizeof(qentry->name),
3472 "qla2xxx%lu_%s", vha->host_no,
3473 msix_entries[QLA_ATIO_VECTOR].name);
3474 qentry->in_use = 1;
3475 ret = request_irq(qentry->vector,
3476 msix_entries[QLA_ATIO_VECTOR].handler,
3477 0, qentry->name, rsp);
3478 qentry->have_irq = 1;
3479 }
3480
3481msix_register_fail:
3482 if (ret) {
3483 ql_log(ql_log_fatal, vha, 0x00cb,
3484 "MSI-X: unable to register handler -- %x/%d.\n",
3485 qentry->vector, ret);
3486 qla2x00_free_irqs(vha);
3487 ha->mqenable = 0;
3488 goto msix_out;
3489 }
3490
3491
3492 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3493 if (ha->msixbase && ha->mqiobase &&
3494 (ha->max_rsp_queues > 1 || ha->max_req_queues > 1 ||
3495 ql2xmqsupport))
3496 ha->mqenable = 1;
3497 } else
3498 if (ha->mqiobase &&
3499 (ha->max_rsp_queues > 1 || ha->max_req_queues > 1 ||
3500 ql2xmqsupport))
3501 ha->mqenable = 1;
3502 ql_dbg(ql_dbg_multiq, vha, 0xc005,
3503 "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
3504 ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
3505 ql_dbg(ql_dbg_init, vha, 0x0055,
3506 "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
3507 ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
3508
3509msix_out:
3510 return ret;
3511}
3512
3513int
3514qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
3515{
3516 int ret = QLA_FUNCTION_FAILED;
3517 device_reg_t *reg = ha->iobase;
3518 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
3519
3520
3521 if (ql2xenablemsix == 0 || (!IS_QLA2432(ha) && !IS_QLA2532(ha) &&
3522 !IS_QLA8432(ha) && !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) &&
3523 !IS_QLAFX00(ha) && !IS_QLA27XX(ha)))
3524 goto skip_msi;
3525
3526 if (ql2xenablemsix == 2)
3527 goto skip_msix;
3528
3529 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
3530 (ha->pdev->subsystem_device == 0x7040 ||
3531 ha->pdev->subsystem_device == 0x7041 ||
3532 ha->pdev->subsystem_device == 0x1705)) {
3533 ql_log(ql_log_warn, vha, 0x0034,
3534 "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
3535 ha->pdev->subsystem_vendor,
3536 ha->pdev->subsystem_device);
3537 goto skip_msi;
3538 }
3539
3540 if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
3541 ql_log(ql_log_warn, vha, 0x0035,
3542 "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
3543 ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
3544 goto skip_msix;
3545 }
3546
3547 ret = qla24xx_enable_msix(ha, rsp);
3548 if (!ret) {
3549 ql_dbg(ql_dbg_init, vha, 0x0036,
3550 "MSI-X: Enabled (0x%X, 0x%X).\n",
3551 ha->chip_revision, ha->fw_attributes);
3552 goto clear_risc_ints;
3553 }
3554
3555skip_msix:
3556
3557 ql_log(ql_log_info, vha, 0x0037,
3558 "Falling back-to MSI mode -%d.\n", ret);
3559
3560 if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
3561 !IS_QLA8001(ha) && !IS_P3P_TYPE(ha) && !IS_QLAFX00(ha) &&
3562 !IS_QLA27XX(ha))
3563 goto skip_msi;
3564
3565 ret = pci_alloc_irq_vectors(ha->pdev, 1, 1, PCI_IRQ_MSI);
3566 if (!ret) {
3567 ql_dbg(ql_dbg_init, vha, 0x0038,
3568 "MSI: Enabled.\n");
3569 ha->flags.msi_enabled = 1;
3570 } else
3571 ql_log(ql_log_warn, vha, 0x0039,
3572 "Falling back-to INTa mode -- %d.\n", ret);
3573skip_msi:
3574
3575
3576 if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
3577 return QLA_FUNCTION_FAILED;
3578
3579 ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
3580 ha->flags.msi_enabled ? 0 : IRQF_SHARED,
3581 QLA2XXX_DRIVER_NAME, rsp);
3582 if (ret) {
3583 ql_log(ql_log_warn, vha, 0x003a,
3584 "Failed to reserve interrupt %d already in use.\n",
3585 ha->pdev->irq);
3586 goto fail;
3587 } else if (!ha->flags.msi_enabled) {
3588 ql_dbg(ql_dbg_init, vha, 0x0125,
3589 "INTa mode: Enabled.\n");
3590 ha->flags.mr_intr_valid = 1;
3591 }
3592
3593clear_risc_ints:
3594 if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
3595 goto fail;
3596
3597 spin_lock_irq(&ha->hardware_lock);
3598 WRT_REG_WORD(®->isp.semaphore, 0);
3599 spin_unlock_irq(&ha->hardware_lock);
3600
3601fail:
3602 return ret;
3603}
3604
3605void
3606qla2x00_free_irqs(scsi_qla_host_t *vha)
3607{
3608 struct qla_hw_data *ha = vha->hw;
3609 struct rsp_que *rsp;
3610 struct qla_msix_entry *qentry;
3611 int i;
3612
3613
3614
3615
3616
3617 if (!ha->rsp_q_map || !ha->rsp_q_map[0])
3618 goto free_irqs;
3619 rsp = ha->rsp_q_map[0];
3620
3621 if (ha->flags.msix_enabled) {
3622 for (i = 0; i < ha->msix_count; i++) {
3623 qentry = &ha->msix_entries[i];
3624 if (qentry->have_irq) {
3625 irq_set_affinity_notifier(qentry->vector, NULL);
3626 free_irq(pci_irq_vector(ha->pdev, i), qentry->handle);
3627 }
3628 }
3629 kfree(ha->msix_entries);
3630 ha->msix_entries = NULL;
3631 ha->flags.msix_enabled = 0;
3632 ql_dbg(ql_dbg_init, vha, 0x0042,
3633 "Disabled MSI-X.\n");
3634 } else {
3635 free_irq(pci_irq_vector(ha->pdev, 0), rsp);
3636 }
3637
3638free_irqs:
3639 pci_free_irq_vectors(ha->pdev);
3640}
3641
3642int qla25xx_request_irq(struct qla_hw_data *ha, struct qla_qpair *qpair,
3643 struct qla_msix_entry *msix, int vector_type)
3644{
3645 const struct qla_init_msix_entry *intr = &msix_entries[vector_type];
3646 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
3647 int ret;
3648
3649 scnprintf(msix->name, sizeof(msix->name),
3650 "qla2xxx%lu_qpair%d", vha->host_no, qpair->id);
3651 ret = request_irq(msix->vector, intr->handler, 0, msix->name, qpair);
3652 if (ret) {
3653 ql_log(ql_log_fatal, vha, 0x00e6,
3654 "MSI-X: Unable to register handler -- %x/%d.\n",
3655 msix->vector, ret);
3656 return ret;
3657 }
3658 msix->have_irq = 1;
3659 msix->handle = qpair;
3660 return ret;
3661}
3662