linux/drivers/scsi/qla2xxx/qla_sup.c
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   1/*
   2 * QLogic Fibre Channel HBA Driver
   3 * Copyright (c)  2003-2014 QLogic Corporation
   4 *
   5 * See LICENSE.qla2xxx for copyright and licensing details.
   6 */
   7#include "qla_def.h"
   8
   9#include <linux/delay.h>
  10#include <linux/slab.h>
  11#include <linux/vmalloc.h>
  12#include <linux/uaccess.h>
  13
  14/*
  15 * NVRAM support routines
  16 */
  17
  18/**
  19 * qla2x00_lock_nvram_access() -
  20 * @ha: HA context
  21 */
  22static void
  23qla2x00_lock_nvram_access(struct qla_hw_data *ha)
  24{
  25        uint16_t data;
  26        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  27
  28        if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  29                data = RD_REG_WORD(&reg->nvram);
  30                while (data & NVR_BUSY) {
  31                        udelay(100);
  32                        data = RD_REG_WORD(&reg->nvram);
  33                }
  34
  35                /* Lock resource */
  36                WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  37                RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  38                udelay(5);
  39                data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  40                while ((data & BIT_0) == 0) {
  41                        /* Lock failed */
  42                        udelay(100);
  43                        WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  44                        RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  45                        udelay(5);
  46                        data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  47                }
  48        }
  49}
  50
  51/**
  52 * qla2x00_unlock_nvram_access() -
  53 * @ha: HA context
  54 */
  55static void
  56qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
  57{
  58        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  59
  60        if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  61                WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  62                RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  63        }
  64}
  65
  66/**
  67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
  68 * @ha: HA context
  69 * @data: Serial interface selector
  70 */
  71static void
  72qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
  73{
  74        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  75
  76        WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  77        RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  78        NVRAM_DELAY();
  79        WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
  80            NVR_WRT_ENABLE);
  81        RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  82        NVRAM_DELAY();
  83        WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  84        RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  85        NVRAM_DELAY();
  86}
  87
  88/**
  89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
  90 *      NVRAM.
  91 * @ha: HA context
  92 * @nv_cmd: NVRAM command
  93 *
  94 * Bit definitions for NVRAM command:
  95 *
  96 *      Bit 26     = start bit
  97 *      Bit 25, 24 = opcode
  98 *      Bit 23-16  = address
  99 *      Bit 15-0   = write data
 100 *
 101 * Returns the word read from nvram @addr.
 102 */
 103static uint16_t
 104qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
 105{
 106        uint8_t         cnt;
 107        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 108        uint16_t        data = 0;
 109        uint16_t        reg_data;
 110
 111        /* Send command to NVRAM. */
 112        nv_cmd <<= 5;
 113        for (cnt = 0; cnt < 11; cnt++) {
 114                if (nv_cmd & BIT_31)
 115                        qla2x00_nv_write(ha, NVR_DATA_OUT);
 116                else
 117                        qla2x00_nv_write(ha, 0);
 118                nv_cmd <<= 1;
 119        }
 120
 121        /* Read data from NVRAM. */
 122        for (cnt = 0; cnt < 16; cnt++) {
 123                WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 124                RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 125                NVRAM_DELAY();
 126                data <<= 1;
 127                reg_data = RD_REG_WORD(&reg->nvram);
 128                if (reg_data & NVR_DATA_IN)
 129                        data |= BIT_0;
 130                WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 131                RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 132                NVRAM_DELAY();
 133        }
 134
 135        /* Deselect chip. */
 136        WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 137        RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 138        NVRAM_DELAY();
 139
 140        return data;
 141}
 142
 143
 144/**
 145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
 146 *      request routine to get the word from NVRAM.
 147 * @ha: HA context
 148 * @addr: Address in NVRAM to read
 149 *
 150 * Returns the word read from nvram @addr.
 151 */
 152static uint16_t
 153qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
 154{
 155        uint16_t        data;
 156        uint32_t        nv_cmd;
 157
 158        nv_cmd = addr << 16;
 159        nv_cmd |= NV_READ_OP;
 160        data = qla2x00_nvram_request(ha, nv_cmd);
 161
 162        return (data);
 163}
 164
 165/**
 166 * qla2x00_nv_deselect() - Deselect NVRAM operations.
 167 * @ha: HA context
 168 */
 169static void
 170qla2x00_nv_deselect(struct qla_hw_data *ha)
 171{
 172        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 173
 174        WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 175        RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 176        NVRAM_DELAY();
 177}
 178
 179/**
 180 * qla2x00_write_nvram_word() - Write NVRAM data.
 181 * @ha: HA context
 182 * @addr: Address in NVRAM to write
 183 * @data: word to program
 184 */
 185static void
 186qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
 187{
 188        int count;
 189        uint16_t word;
 190        uint32_t nv_cmd, wait_cnt;
 191        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 192        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 193
 194        qla2x00_nv_write(ha, NVR_DATA_OUT);
 195        qla2x00_nv_write(ha, 0);
 196        qla2x00_nv_write(ha, 0);
 197
 198        for (word = 0; word < 8; word++)
 199                qla2x00_nv_write(ha, NVR_DATA_OUT);
 200
 201        qla2x00_nv_deselect(ha);
 202
 203        /* Write data */
 204        nv_cmd = (addr << 16) | NV_WRITE_OP;
 205        nv_cmd |= data;
 206        nv_cmd <<= 5;
 207        for (count = 0; count < 27; count++) {
 208                if (nv_cmd & BIT_31)
 209                        qla2x00_nv_write(ha, NVR_DATA_OUT);
 210                else
 211                        qla2x00_nv_write(ha, 0);
 212
 213                nv_cmd <<= 1;
 214        }
 215
 216        qla2x00_nv_deselect(ha);
 217
 218        /* Wait for NVRAM to become ready */
 219        WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 220        RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 221        wait_cnt = NVR_WAIT_CNT;
 222        do {
 223                if (!--wait_cnt) {
 224                        ql_dbg(ql_dbg_user, vha, 0x708d,
 225                            "NVRAM didn't go ready...\n");
 226                        break;
 227                }
 228                NVRAM_DELAY();
 229                word = RD_REG_WORD(&reg->nvram);
 230        } while ((word & NVR_DATA_IN) == 0);
 231
 232        qla2x00_nv_deselect(ha);
 233
 234        /* Disable writes */
 235        qla2x00_nv_write(ha, NVR_DATA_OUT);
 236        for (count = 0; count < 10; count++)
 237                qla2x00_nv_write(ha, 0);
 238
 239        qla2x00_nv_deselect(ha);
 240}
 241
 242static int
 243qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
 244        uint16_t data, uint32_t tmo)
 245{
 246        int ret, count;
 247        uint16_t word;
 248        uint32_t nv_cmd;
 249        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 250
 251        ret = QLA_SUCCESS;
 252
 253        qla2x00_nv_write(ha, NVR_DATA_OUT);
 254        qla2x00_nv_write(ha, 0);
 255        qla2x00_nv_write(ha, 0);
 256
 257        for (word = 0; word < 8; word++)
 258                qla2x00_nv_write(ha, NVR_DATA_OUT);
 259
 260        qla2x00_nv_deselect(ha);
 261
 262        /* Write data */
 263        nv_cmd = (addr << 16) | NV_WRITE_OP;
 264        nv_cmd |= data;
 265        nv_cmd <<= 5;
 266        for (count = 0; count < 27; count++) {
 267                if (nv_cmd & BIT_31)
 268                        qla2x00_nv_write(ha, NVR_DATA_OUT);
 269                else
 270                        qla2x00_nv_write(ha, 0);
 271
 272                nv_cmd <<= 1;
 273        }
 274
 275        qla2x00_nv_deselect(ha);
 276
 277        /* Wait for NVRAM to become ready */
 278        WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 279        RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 280        do {
 281                NVRAM_DELAY();
 282                word = RD_REG_WORD(&reg->nvram);
 283                if (!--tmo) {
 284                        ret = QLA_FUNCTION_FAILED;
 285                        break;
 286                }
 287        } while ((word & NVR_DATA_IN) == 0);
 288
 289        qla2x00_nv_deselect(ha);
 290
 291        /* Disable writes */
 292        qla2x00_nv_write(ha, NVR_DATA_OUT);
 293        for (count = 0; count < 10; count++)
 294                qla2x00_nv_write(ha, 0);
 295
 296        qla2x00_nv_deselect(ha);
 297
 298        return ret;
 299}
 300
 301/**
 302 * qla2x00_clear_nvram_protection() -
 303 * @ha: HA context
 304 */
 305static int
 306qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
 307{
 308        int ret, stat;
 309        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 310        uint32_t word, wait_cnt;
 311        uint16_t wprot, wprot_old;
 312        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 313
 314        /* Clear NVRAM write protection. */
 315        ret = QLA_FUNCTION_FAILED;
 316
 317        wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318        stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 319                                            cpu_to_le16(0x1234), 100000);
 320        wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 321        if (stat != QLA_SUCCESS || wprot != 0x1234) {
 322                /* Write enable. */
 323                qla2x00_nv_write(ha, NVR_DATA_OUT);
 324                qla2x00_nv_write(ha, 0);
 325                qla2x00_nv_write(ha, 0);
 326                for (word = 0; word < 8; word++)
 327                        qla2x00_nv_write(ha, NVR_DATA_OUT);
 328
 329                qla2x00_nv_deselect(ha);
 330
 331                /* Enable protection register. */
 332                qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 333                qla2x00_nv_write(ha, NVR_PR_ENABLE);
 334                qla2x00_nv_write(ha, NVR_PR_ENABLE);
 335                for (word = 0; word < 8; word++)
 336                        qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 337
 338                qla2x00_nv_deselect(ha);
 339
 340                /* Clear protection register (ffff is cleared). */
 341                qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 342                qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 343                qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 344                for (word = 0; word < 8; word++)
 345                        qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 346
 347                qla2x00_nv_deselect(ha);
 348
 349                /* Wait for NVRAM to become ready. */
 350                WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 351                RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 352                wait_cnt = NVR_WAIT_CNT;
 353                do {
 354                        if (!--wait_cnt) {
 355                                ql_dbg(ql_dbg_user, vha, 0x708e,
 356                                    "NVRAM didn't go ready...\n");
 357                                break;
 358                        }
 359                        NVRAM_DELAY();
 360                        word = RD_REG_WORD(&reg->nvram);
 361                } while ((word & NVR_DATA_IN) == 0);
 362
 363                if (wait_cnt)
 364                        ret = QLA_SUCCESS;
 365        } else
 366                qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 367
 368        return ret;
 369}
 370
 371static void
 372qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
 373{
 374        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 375        uint32_t word, wait_cnt;
 376        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 377
 378        if (stat != QLA_SUCCESS)
 379                return;
 380
 381        /* Set NVRAM write protection. */
 382        /* Write enable. */
 383        qla2x00_nv_write(ha, NVR_DATA_OUT);
 384        qla2x00_nv_write(ha, 0);
 385        qla2x00_nv_write(ha, 0);
 386        for (word = 0; word < 8; word++)
 387                qla2x00_nv_write(ha, NVR_DATA_OUT);
 388
 389        qla2x00_nv_deselect(ha);
 390
 391        /* Enable protection register. */
 392        qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 393        qla2x00_nv_write(ha, NVR_PR_ENABLE);
 394        qla2x00_nv_write(ha, NVR_PR_ENABLE);
 395        for (word = 0; word < 8; word++)
 396                qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 397
 398        qla2x00_nv_deselect(ha);
 399
 400        /* Enable protection register. */
 401        qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 402        qla2x00_nv_write(ha, NVR_PR_ENABLE);
 403        qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 404        for (word = 0; word < 8; word++)
 405                qla2x00_nv_write(ha, NVR_PR_ENABLE);
 406
 407        qla2x00_nv_deselect(ha);
 408
 409        /* Wait for NVRAM to become ready. */
 410        WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 411        RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 412        wait_cnt = NVR_WAIT_CNT;
 413        do {
 414                if (!--wait_cnt) {
 415                        ql_dbg(ql_dbg_user, vha, 0x708f,
 416                            "NVRAM didn't go ready...\n");
 417                        break;
 418                }
 419                NVRAM_DELAY();
 420                word = RD_REG_WORD(&reg->nvram);
 421        } while ((word & NVR_DATA_IN) == 0);
 422}
 423
 424
 425/*****************************************************************************/
 426/* Flash Manipulation Routines                                               */
 427/*****************************************************************************/
 428
 429static inline uint32_t
 430flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
 431{
 432        return ha->flash_conf_off | faddr;
 433}
 434
 435static inline uint32_t
 436flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
 437{
 438        return ha->flash_data_off | faddr;
 439}
 440
 441static inline uint32_t
 442nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
 443{
 444        return ha->nvram_conf_off | naddr;
 445}
 446
 447static inline uint32_t
 448nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
 449{
 450        return ha->nvram_data_off | naddr;
 451}
 452
 453static uint32_t
 454qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
 455{
 456        int rval;
 457        uint32_t cnt, data;
 458        struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 459
 460        WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 461        /* Wait for READ cycle to complete. */
 462        rval = QLA_SUCCESS;
 463        for (cnt = 3000;
 464            (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 465            rval == QLA_SUCCESS; cnt--) {
 466                if (cnt)
 467                        udelay(10);
 468                else
 469                        rval = QLA_FUNCTION_TIMEOUT;
 470                cond_resched();
 471        }
 472
 473        /* TODO: What happens if we time out? */
 474        data = 0xDEADDEAD;
 475        if (rval == QLA_SUCCESS)
 476                data = RD_REG_DWORD(&reg->flash_data);
 477
 478        return data;
 479}
 480
 481uint32_t *
 482qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
 483    uint32_t dwords)
 484{
 485        uint32_t i;
 486        struct qla_hw_data *ha = vha->hw;
 487
 488        /* Dword reads to flash. */
 489        for (i = 0; i < dwords; i++, faddr++)
 490                dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 491                    flash_data_addr(ha, faddr)));
 492
 493        return dwptr;
 494}
 495
 496static int
 497qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
 498{
 499        int rval;
 500        uint32_t cnt;
 501        struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 502
 503        WRT_REG_DWORD(&reg->flash_data, data);
 504        RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 505        WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 506        /* Wait for Write cycle to complete. */
 507        rval = QLA_SUCCESS;
 508        for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 509            rval == QLA_SUCCESS; cnt--) {
 510                if (cnt)
 511                        udelay(10);
 512                else
 513                        rval = QLA_FUNCTION_TIMEOUT;
 514                cond_resched();
 515        }
 516        return rval;
 517}
 518
 519static void
 520qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
 521    uint8_t *flash_id)
 522{
 523        uint32_t ids;
 524
 525        ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
 526        *man_id = LSB(ids);
 527        *flash_id = MSB(ids);
 528
 529        /* Check if man_id and flash_id are valid. */
 530        if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 531                /* Read information using 0x9f opcode
 532                 * Device ID, Mfg ID would be read in the format:
 533                 *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 534                 * Example: ATMEL 0x00 01 45 1F
 535                 * Extract MFG and Dev ID from last two bytes.
 536                 */
 537                ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
 538                *man_id = LSB(ids);
 539                *flash_id = MSB(ids);
 540        }
 541}
 542
 543static int
 544qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
 545{
 546        const char *loc, *locations[] = { "DEF", "PCI" };
 547        uint32_t pcihdr, pcids;
 548        uint32_t *dcode;
 549        uint8_t *buf, *bcode, last_image;
 550        uint16_t cnt, chksum, *wptr;
 551        struct qla_flt_location *fltl;
 552        struct qla_hw_data *ha = vha->hw;
 553        struct req_que *req = ha->req_q_map[0];
 554
 555        /*
 556         * FLT-location structure resides after the last PCI region.
 557         */
 558
 559        /* Begin with sane defaults. */
 560        loc = locations[0];
 561        *start = 0;
 562        if (IS_QLA24XX_TYPE(ha))
 563                *start = FA_FLASH_LAYOUT_ADDR_24;
 564        else if (IS_QLA25XX(ha))
 565                *start = FA_FLASH_LAYOUT_ADDR;
 566        else if (IS_QLA81XX(ha))
 567                *start = FA_FLASH_LAYOUT_ADDR_81;
 568        else if (IS_P3P_TYPE(ha)) {
 569                *start = FA_FLASH_LAYOUT_ADDR_82;
 570                goto end;
 571        } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
 572                *start = FA_FLASH_LAYOUT_ADDR_83;
 573                goto end;
 574        }
 575        /* Begin with first PCI expansion ROM header. */
 576        buf = (uint8_t *)req->ring;
 577        dcode = (uint32_t *)req->ring;
 578        pcihdr = 0;
 579        last_image = 1;
 580        do {
 581                /* Verify PCI expansion ROM header. */
 582                qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
 583                bcode = buf + (pcihdr % 4);
 584                if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
 585                        goto end;
 586
 587                /* Locate PCI data structure. */
 588                pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
 589                qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
 590                bcode = buf + (pcihdr % 4);
 591
 592                /* Validate signature of PCI data structure. */
 593                if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
 594                    bcode[0x2] != 'I' || bcode[0x3] != 'R')
 595                        goto end;
 596
 597                last_image = bcode[0x15] & BIT_7;
 598
 599                /* Locate next PCI expansion ROM. */
 600                pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
 601        } while (!last_image);
 602
 603        /* Now verify FLT-location structure. */
 604        fltl = (struct qla_flt_location *)req->ring;
 605        qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
 606            sizeof(struct qla_flt_location) >> 2);
 607        if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
 608            fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
 609                goto end;
 610
 611        wptr = (uint16_t *)req->ring;
 612        cnt = sizeof(struct qla_flt_location) >> 1;
 613        for (chksum = 0; cnt--; wptr++)
 614                chksum += le16_to_cpu(*wptr);
 615        if (chksum) {
 616                ql_log(ql_log_fatal, vha, 0x0045,
 617                    "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
 618                ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
 619                    buf, sizeof(struct qla_flt_location));
 620                return QLA_FUNCTION_FAILED;
 621        }
 622
 623        /* Good data.  Use specified location. */
 624        loc = locations[1];
 625        *start = (le16_to_cpu(fltl->start_hi) << 16 |
 626            le16_to_cpu(fltl->start_lo)) >> 2;
 627end:
 628        ql_dbg(ql_dbg_init, vha, 0x0046,
 629            "FLTL[%s] = 0x%x.\n",
 630            loc, *start);
 631        return QLA_SUCCESS;
 632}
 633
 634static void
 635qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
 636{
 637        const char *loc, *locations[] = { "DEF", "FLT" };
 638        const uint32_t def_fw[] =
 639                { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
 640        const uint32_t def_boot[] =
 641                { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
 642        const uint32_t def_vpd_nvram[] =
 643                { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
 644        const uint32_t def_vpd0[] =
 645                { 0, 0, FA_VPD0_ADDR_81 };
 646        const uint32_t def_vpd1[] =
 647                { 0, 0, FA_VPD1_ADDR_81 };
 648        const uint32_t def_nvram0[] =
 649                { 0, 0, FA_NVRAM0_ADDR_81 };
 650        const uint32_t def_nvram1[] =
 651                { 0, 0, FA_NVRAM1_ADDR_81 };
 652        const uint32_t def_fdt[] =
 653                { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
 654                        FA_FLASH_DESCR_ADDR_81 };
 655        const uint32_t def_npiv_conf0[] =
 656                { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
 657                        FA_NPIV_CONF0_ADDR_81 };
 658        const uint32_t def_npiv_conf1[] =
 659                { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
 660                        FA_NPIV_CONF1_ADDR_81 };
 661        const uint32_t fcp_prio_cfg0[] =
 662                { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
 663                        0 };
 664        const uint32_t fcp_prio_cfg1[] =
 665                { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
 666                        0 };
 667        uint32_t def;
 668        uint16_t *wptr;
 669        uint16_t cnt, chksum;
 670        uint32_t start;
 671        struct qla_flt_header *flt;
 672        struct qla_flt_region *region;
 673        struct qla_hw_data *ha = vha->hw;
 674        struct req_que *req = ha->req_q_map[0];
 675
 676        def = 0;
 677        if (IS_QLA25XX(ha))
 678                def = 1;
 679        else if (IS_QLA81XX(ha))
 680                def = 2;
 681
 682        /* Assign FCP prio region since older adapters may not have FLT, or
 683           FCP prio region in it's FLT.
 684         */
 685        ha->flt_region_fcp_prio = (ha->port_no == 0) ?
 686            fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
 687
 688        ha->flt_region_flt = flt_addr;
 689        wptr = (uint16_t *)req->ring;
 690        flt = (struct qla_flt_header *)req->ring;
 691        region = (struct qla_flt_region *)&flt[1];
 692        ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 693            flt_addr << 2, OPTROM_BURST_SIZE);
 694        if (*wptr == cpu_to_le16(0xffff))
 695                goto no_flash_data;
 696        if (flt->version != cpu_to_le16(1)) {
 697                ql_log(ql_log_warn, vha, 0x0047,
 698                    "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
 699                    le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 700                    le16_to_cpu(flt->checksum));
 701                goto no_flash_data;
 702        }
 703
 704        cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
 705        for (chksum = 0; cnt--; wptr++)
 706                chksum += le16_to_cpu(*wptr);
 707        if (chksum) {
 708                ql_log(ql_log_fatal, vha, 0x0048,
 709                    "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
 710                    le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 711                    le16_to_cpu(flt->checksum));
 712                goto no_flash_data;
 713        }
 714
 715        loc = locations[1];
 716        cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
 717        for ( ; cnt; cnt--, region++) {
 718                /* Store addresses as DWORD offsets. */
 719                start = le32_to_cpu(region->start) >> 2;
 720                ql_dbg(ql_dbg_init, vha, 0x0049,
 721                    "FLT[%02x]: start=0x%x "
 722                    "end=0x%x size=0x%x.\n", le32_to_cpu(region->code) & 0xff,
 723                    start, le32_to_cpu(region->end) >> 2,
 724                    le32_to_cpu(region->size));
 725
 726                switch (le32_to_cpu(region->code) & 0xff) {
 727                case FLT_REG_FCOE_FW:
 728                        if (!IS_QLA8031(ha))
 729                                break;
 730                        ha->flt_region_fw = start;
 731                        break;
 732                case FLT_REG_FW:
 733                        if (IS_QLA8031(ha))
 734                                break;
 735                        ha->flt_region_fw = start;
 736                        break;
 737                case FLT_REG_BOOT_CODE:
 738                        ha->flt_region_boot = start;
 739                        break;
 740                case FLT_REG_VPD_0:
 741                        if (IS_QLA8031(ha))
 742                                break;
 743                        ha->flt_region_vpd_nvram = start;
 744                        if (IS_P3P_TYPE(ha))
 745                                break;
 746                        if (ha->port_no == 0)
 747                                ha->flt_region_vpd = start;
 748                        break;
 749                case FLT_REG_VPD_1:
 750                        if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
 751                                break;
 752                        if (ha->port_no == 1)
 753                                ha->flt_region_vpd = start;
 754                        break;
 755                case FLT_REG_VPD_2:
 756                        if (!IS_QLA27XX(ha))
 757                                break;
 758                        if (ha->port_no == 2)
 759                                ha->flt_region_vpd = start;
 760                        break;
 761                case FLT_REG_VPD_3:
 762                        if (!IS_QLA27XX(ha))
 763                                break;
 764                        if (ha->port_no == 3)
 765                                ha->flt_region_vpd = start;
 766                        break;
 767                case FLT_REG_NVRAM_0:
 768                        if (IS_QLA8031(ha))
 769                                break;
 770                        if (ha->port_no == 0)
 771                                ha->flt_region_nvram = start;
 772                        break;
 773                case FLT_REG_NVRAM_1:
 774                        if (IS_QLA8031(ha))
 775                                break;
 776                        if (ha->port_no == 1)
 777                                ha->flt_region_nvram = start;
 778                        break;
 779                case FLT_REG_NVRAM_2:
 780                        if (!IS_QLA27XX(ha))
 781                                break;
 782                        if (ha->port_no == 2)
 783                                ha->flt_region_nvram = start;
 784                        break;
 785                case FLT_REG_NVRAM_3:
 786                        if (!IS_QLA27XX(ha))
 787                                break;
 788                        if (ha->port_no == 3)
 789                                ha->flt_region_nvram = start;
 790                        break;
 791                case FLT_REG_FDT:
 792                        ha->flt_region_fdt = start;
 793                        break;
 794                case FLT_REG_NPIV_CONF_0:
 795                        if (ha->port_no == 0)
 796                                ha->flt_region_npiv_conf = start;
 797                        break;
 798                case FLT_REG_NPIV_CONF_1:
 799                        if (ha->port_no == 1)
 800                                ha->flt_region_npiv_conf = start;
 801                        break;
 802                case FLT_REG_GOLD_FW:
 803                        ha->flt_region_gold_fw = start;
 804                        break;
 805                case FLT_REG_FCP_PRIO_0:
 806                        if (ha->port_no == 0)
 807                                ha->flt_region_fcp_prio = start;
 808                        break;
 809                case FLT_REG_FCP_PRIO_1:
 810                        if (ha->port_no == 1)
 811                                ha->flt_region_fcp_prio = start;
 812                        break;
 813                case FLT_REG_BOOT_CODE_82XX:
 814                        ha->flt_region_boot = start;
 815                        break;
 816                case FLT_REG_BOOT_CODE_8044:
 817                        if (IS_QLA8044(ha))
 818                                ha->flt_region_boot = start;
 819                        break;
 820                case FLT_REG_FW_82XX:
 821                        ha->flt_region_fw = start;
 822                        break;
 823                case FLT_REG_CNA_FW:
 824                        if (IS_CNA_CAPABLE(ha))
 825                                ha->flt_region_fw = start;
 826                        break;
 827                case FLT_REG_GOLD_FW_82XX:
 828                        ha->flt_region_gold_fw = start;
 829                        break;
 830                case FLT_REG_BOOTLOAD_82XX:
 831                        ha->flt_region_bootload = start;
 832                        break;
 833                case FLT_REG_VPD_8XXX:
 834                        if (IS_CNA_CAPABLE(ha))
 835                                ha->flt_region_vpd = start;
 836                        break;
 837                case FLT_REG_FCOE_NVRAM_0:
 838                        if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
 839                                break;
 840                        if (ha->port_no == 0)
 841                                ha->flt_region_nvram = start;
 842                        break;
 843                case FLT_REG_FCOE_NVRAM_1:
 844                        if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
 845                                break;
 846                        if (ha->port_no == 1)
 847                                ha->flt_region_nvram = start;
 848                        break;
 849                case FLT_REG_IMG_PRI_27XX:
 850                        if (IS_QLA27XX(ha))
 851                                ha->flt_region_img_status_pri = start;
 852                        break;
 853                case FLT_REG_IMG_SEC_27XX:
 854                        if (IS_QLA27XX(ha))
 855                                ha->flt_region_img_status_sec = start;
 856                        break;
 857                case FLT_REG_FW_SEC_27XX:
 858                        if (IS_QLA27XX(ha))
 859                                ha->flt_region_fw_sec = start;
 860                        break;
 861                case FLT_REG_BOOTLOAD_SEC_27XX:
 862                        if (IS_QLA27XX(ha))
 863                                ha->flt_region_boot_sec = start;
 864                        break;
 865                case FLT_REG_VPD_SEC_27XX_0:
 866                        if (IS_QLA27XX(ha))
 867                                ha->flt_region_vpd_sec = start;
 868                        break;
 869                case FLT_REG_VPD_SEC_27XX_1:
 870                        if (IS_QLA27XX(ha))
 871                                ha->flt_region_vpd_sec = start;
 872                        break;
 873                case FLT_REG_VPD_SEC_27XX_2:
 874                        if (IS_QLA27XX(ha))
 875                                ha->flt_region_vpd_sec = start;
 876                        break;
 877                case FLT_REG_VPD_SEC_27XX_3:
 878                        if (IS_QLA27XX(ha))
 879                                ha->flt_region_vpd_sec = start;
 880                        break;
 881                }
 882        }
 883        goto done;
 884
 885no_flash_data:
 886        /* Use hardcoded defaults. */
 887        loc = locations[0];
 888        ha->flt_region_fw = def_fw[def];
 889        ha->flt_region_boot = def_boot[def];
 890        ha->flt_region_vpd_nvram = def_vpd_nvram[def];
 891        ha->flt_region_vpd = (ha->port_no == 0) ?
 892            def_vpd0[def] : def_vpd1[def];
 893        ha->flt_region_nvram = (ha->port_no == 0) ?
 894            def_nvram0[def] : def_nvram1[def];
 895        ha->flt_region_fdt = def_fdt[def];
 896        ha->flt_region_npiv_conf = (ha->port_no == 0) ?
 897            def_npiv_conf0[def] : def_npiv_conf1[def];
 898done:
 899        ql_dbg(ql_dbg_init, vha, 0x004a,
 900            "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
 901            "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
 902            loc, ha->flt_region_boot, ha->flt_region_fw,
 903            ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
 904            ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
 905            ha->flt_region_fcp_prio);
 906}
 907
 908static void
 909qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
 910{
 911#define FLASH_BLK_SIZE_4K       0x1000
 912#define FLASH_BLK_SIZE_32K      0x8000
 913#define FLASH_BLK_SIZE_64K      0x10000
 914        const char *loc, *locations[] = { "MID", "FDT" };
 915        uint16_t cnt, chksum;
 916        uint16_t *wptr;
 917        struct qla_fdt_layout *fdt;
 918        uint8_t man_id, flash_id;
 919        uint16_t mid = 0, fid = 0;
 920        struct qla_hw_data *ha = vha->hw;
 921        struct req_que *req = ha->req_q_map[0];
 922
 923        wptr = (uint16_t *)req->ring;
 924        fdt = (struct qla_fdt_layout *)req->ring;
 925        ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 926            ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
 927        if (*wptr == cpu_to_le16(0xffff))
 928                goto no_flash_data;
 929        if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 930            fdt->sig[3] != 'D')
 931                goto no_flash_data;
 932
 933        for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++)
 934                chksum += le16_to_cpu(*wptr);
 935        if (chksum) {
 936                ql_dbg(ql_dbg_init, vha, 0x004c,
 937                    "Inconsistent FDT detected:"
 938                    " checksum=0x%x id=%c version0x%x.\n", chksum,
 939                    fdt->sig[0], le16_to_cpu(fdt->version));
 940                ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
 941                    (uint8_t *)fdt, sizeof(*fdt));
 942                goto no_flash_data;
 943        }
 944
 945        loc = locations[1];
 946        mid = le16_to_cpu(fdt->man_id);
 947        fid = le16_to_cpu(fdt->id);
 948        ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 949        ha->fdt_wrt_enable = fdt->wrt_enable_bits;
 950        ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd;
 951        if (IS_QLA8044(ha))
 952                ha->fdt_erase_cmd = fdt->erase_cmd;
 953        else
 954                ha->fdt_erase_cmd =
 955                    flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
 956        ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 957        if (fdt->unprotect_sec_cmd) {
 958                ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
 959                    fdt->unprotect_sec_cmd);
 960                ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 961                    flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
 962                    flash_conf_addr(ha, 0x0336);
 963        }
 964        goto done;
 965no_flash_data:
 966        loc = locations[0];
 967        if (IS_P3P_TYPE(ha)) {
 968                ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 969                goto done;
 970        }
 971        qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 972        mid = man_id;
 973        fid = flash_id;
 974        ha->fdt_wrt_disable = 0x9c;
 975        ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
 976        switch (man_id) {
 977        case 0xbf: /* STT flash. */
 978                if (flash_id == 0x8e)
 979                        ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 980                else
 981                        ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 982
 983                if (flash_id == 0x80)
 984                        ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
 985                break;
 986        case 0x13: /* ST M25P80. */
 987                ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 988                break;
 989        case 0x1f: /* Atmel 26DF081A. */
 990                ha->fdt_block_size = FLASH_BLK_SIZE_4K;
 991                ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
 992                ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
 993                ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
 994                break;
 995        default:
 996                /* Default to 64 kb sector size. */
 997                ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 998                break;
 999        }
1000done:
1001        ql_dbg(ql_dbg_init, vha, 0x004d,
1002            "FDT[%s]: (0x%x/0x%x) erase=0x%x "
1003            "pr=%x wrtd=0x%x blk=0x%x.\n",
1004            loc, mid, fid,
1005            ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
1006            ha->fdt_wrt_disable, ha->fdt_block_size);
1007
1008}
1009
1010static void
1011qla2xxx_get_idc_param(scsi_qla_host_t *vha)
1012{
1013#define QLA82XX_IDC_PARAM_ADDR       0x003e885c
1014        uint32_t *wptr;
1015        struct qla_hw_data *ha = vha->hw;
1016        struct req_que *req = ha->req_q_map[0];
1017
1018        if (!(IS_P3P_TYPE(ha)))
1019                return;
1020
1021        wptr = (uint32_t *)req->ring;
1022        ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
1023                QLA82XX_IDC_PARAM_ADDR , 8);
1024
1025        if (*wptr == cpu_to_le32(0xffffffff)) {
1026                ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
1027                ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
1028        } else {
1029                ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr);
1030                wptr++;
1031                ha->fcoe_reset_timeout = le32_to_cpu(*wptr);
1032        }
1033        ql_dbg(ql_dbg_init, vha, 0x004e,
1034            "fcoe_dev_init_timeout=%d "
1035            "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout,
1036            ha->fcoe_reset_timeout);
1037        return;
1038}
1039
1040int
1041qla2xxx_get_flash_info(scsi_qla_host_t *vha)
1042{
1043        int ret;
1044        uint32_t flt_addr;
1045        struct qla_hw_data *ha = vha->hw;
1046
1047        if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1048            !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLA27XX(ha))
1049                return QLA_SUCCESS;
1050
1051        ret = qla2xxx_find_flt_start(vha, &flt_addr);
1052        if (ret != QLA_SUCCESS)
1053                return ret;
1054
1055        qla2xxx_get_flt_info(vha, flt_addr);
1056        qla2xxx_get_fdt_info(vha);
1057        qla2xxx_get_idc_param(vha);
1058
1059        return QLA_SUCCESS;
1060}
1061
1062void
1063qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
1064{
1065#define NPIV_CONFIG_SIZE        (16*1024)
1066        void *data;
1067        uint16_t *wptr;
1068        uint16_t cnt, chksum;
1069        int i;
1070        struct qla_npiv_header hdr;
1071        struct qla_npiv_entry *entry;
1072        struct qla_hw_data *ha = vha->hw;
1073
1074        if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1075            !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
1076                return;
1077
1078        if (ha->flags.nic_core_reset_hdlr_active)
1079                return;
1080
1081        if (IS_QLA8044(ha))
1082                return;
1083
1084        ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
1085            ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
1086        if (hdr.version == cpu_to_le16(0xffff))
1087                return;
1088        if (hdr.version != cpu_to_le16(1)) {
1089                ql_dbg(ql_dbg_user, vha, 0x7090,
1090                    "Unsupported NPIV-Config "
1091                    "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1092                    le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1093                    le16_to_cpu(hdr.checksum));
1094                return;
1095        }
1096
1097        data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
1098        if (!data) {
1099                ql_log(ql_log_warn, vha, 0x7091,
1100                    "Unable to allocate memory for data.\n");
1101                return;
1102        }
1103
1104        ha->isp_ops->read_optrom(vha, (uint8_t *)data,
1105            ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
1106
1107        cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1;
1108        for (wptr = data, chksum = 0; cnt--; wptr++)
1109                chksum += le16_to_cpu(*wptr);
1110        if (chksum) {
1111                ql_dbg(ql_dbg_user, vha, 0x7092,
1112                    "Inconsistent NPIV-Config "
1113                    "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1114                    le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1115                    le16_to_cpu(hdr.checksum));
1116                goto done;
1117        }
1118
1119        entry = data + sizeof(struct qla_npiv_header);
1120        cnt = le16_to_cpu(hdr.entries);
1121        for (i = 0; cnt; cnt--, entry++, i++) {
1122                uint16_t flags;
1123                struct fc_vport_identifiers vid;
1124                struct fc_vport *vport;
1125
1126                memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1127
1128                flags = le16_to_cpu(entry->flags);
1129                if (flags == 0xffff)
1130                        continue;
1131                if ((flags & BIT_0) == 0)
1132                        continue;
1133
1134                memset(&vid, 0, sizeof(vid));
1135                vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1136                vid.vport_type = FC_PORTTYPE_NPIV;
1137                vid.disable = false;
1138                vid.port_name = wwn_to_u64(entry->port_name);
1139                vid.node_name = wwn_to_u64(entry->node_name);
1140
1141                ql_dbg(ql_dbg_user, vha, 0x7093,
1142                    "NPIV[%02x]: wwpn=%llx "
1143                    "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1144                    (unsigned long long)vid.port_name,
1145                    (unsigned long long)vid.node_name,
1146                    le16_to_cpu(entry->vf_id),
1147                    entry->q_qos, entry->f_qos);
1148
1149                if (i < QLA_PRECONFIG_VPORTS) {
1150                        vport = fc_vport_create(vha->host, 0, &vid);
1151                        if (!vport)
1152                                ql_log(ql_log_warn, vha, 0x7094,
1153                                    "NPIV-Config Failed to create vport [%02x]: "
1154                                    "wwpn=%llx wwnn=%llx.\n", cnt,
1155                                    (unsigned long long)vid.port_name,
1156                                    (unsigned long long)vid.node_name);
1157                }
1158        }
1159done:
1160        kfree(data);
1161}
1162
1163static int
1164qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1165{
1166        struct qla_hw_data *ha = vha->hw;
1167        struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1168
1169        if (ha->flags.fac_supported)
1170                return qla81xx_fac_do_write_enable(vha, 1);
1171
1172        /* Enable flash write. */
1173        WRT_REG_DWORD(&reg->ctrl_status,
1174            RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1175        RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1176
1177        if (!ha->fdt_wrt_disable)
1178                goto done;
1179
1180        /* Disable flash write-protection, first clear SR protection bit */
1181        qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1182        /* Then write zero again to clear remaining SR bits.*/
1183        qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1184done:
1185        return QLA_SUCCESS;
1186}
1187
1188static int
1189qla24xx_protect_flash(scsi_qla_host_t *vha)
1190{
1191        uint32_t cnt;
1192        struct qla_hw_data *ha = vha->hw;
1193        struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1194
1195        if (ha->flags.fac_supported)
1196                return qla81xx_fac_do_write_enable(vha, 0);
1197
1198        if (!ha->fdt_wrt_disable)
1199                goto skip_wrt_protect;
1200
1201        /* Enable flash write-protection and wait for completion. */
1202        qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1203            ha->fdt_wrt_disable);
1204        for (cnt = 300; cnt &&
1205            qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1206            cnt--) {
1207                udelay(10);
1208        }
1209
1210skip_wrt_protect:
1211        /* Disable flash write. */
1212        WRT_REG_DWORD(&reg->ctrl_status,
1213            RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1214        RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1215
1216        return QLA_SUCCESS;
1217}
1218
1219static int
1220qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1221{
1222        struct qla_hw_data *ha = vha->hw;
1223        uint32_t start, finish;
1224
1225        if (ha->flags.fac_supported) {
1226                start = fdata >> 2;
1227                finish = start + (ha->fdt_block_size >> 2) - 1;
1228                return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1229                    start), flash_data_addr(ha, finish));
1230        }
1231
1232        return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1233            (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1234            ((fdata >> 16) & 0xff));
1235}
1236
1237static int
1238qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1239    uint32_t dwords)
1240{
1241        int ret;
1242        uint32_t liter;
1243        uint32_t sec_mask, rest_addr;
1244        uint32_t fdata;
1245        dma_addr_t optrom_dma;
1246        void *optrom = NULL;
1247        struct qla_hw_data *ha = vha->hw;
1248
1249        /* Prepare burst-capable write on supported ISPs. */
1250        if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
1251            IS_QLA27XX(ha)) &&
1252            !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
1253                optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1254                    &optrom_dma, GFP_KERNEL);
1255                if (!optrom) {
1256                        ql_log(ql_log_warn, vha, 0x7095,
1257                            "Unable to allocate "
1258                            "memory for optrom burst write (%x KB).\n",
1259                            OPTROM_BURST_SIZE / 1024);
1260                }
1261        }
1262
1263        rest_addr = (ha->fdt_block_size >> 2) - 1;
1264        sec_mask = ~rest_addr;
1265
1266        ret = qla24xx_unprotect_flash(vha);
1267        if (ret != QLA_SUCCESS) {
1268                ql_log(ql_log_warn, vha, 0x7096,
1269                    "Unable to unprotect flash for update.\n");
1270                goto done;
1271        }
1272
1273        for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1274                fdata = (faddr & sec_mask) << 2;
1275
1276                /* Are we at the beginning of a sector? */
1277                if ((faddr & rest_addr) == 0) {
1278                        /* Do sector unprotect. */
1279                        if (ha->fdt_unprotect_sec_cmd)
1280                                qla24xx_write_flash_dword(ha,
1281                                    ha->fdt_unprotect_sec_cmd,
1282                                    (fdata & 0xff00) | ((fdata << 16) &
1283                                    0xff0000) | ((fdata >> 16) & 0xff));
1284                        ret = qla24xx_erase_sector(vha, fdata);
1285                        if (ret != QLA_SUCCESS) {
1286                                ql_dbg(ql_dbg_user, vha, 0x7007,
1287                                    "Unable to erase erase sector: address=%x.\n",
1288                                    faddr);
1289                                break;
1290                        }
1291                }
1292
1293                /* Go with burst-write. */
1294                if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1295                        /* Copy data to DMA'ble buffer. */
1296                        memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1297
1298                        ret = qla2x00_load_ram(vha, optrom_dma,
1299                            flash_data_addr(ha, faddr),
1300                            OPTROM_BURST_DWORDS);
1301                        if (ret != QLA_SUCCESS) {
1302                                ql_log(ql_log_warn, vha, 0x7097,
1303                                    "Unable to burst-write optrom segment "
1304                                    "(%x/%x/%llx).\n", ret,
1305                                    flash_data_addr(ha, faddr),
1306                                    (unsigned long long)optrom_dma);
1307                                ql_log(ql_log_warn, vha, 0x7098,
1308                                    "Reverting to slow-write.\n");
1309
1310                                dma_free_coherent(&ha->pdev->dev,
1311                                    OPTROM_BURST_SIZE, optrom, optrom_dma);
1312                                optrom = NULL;
1313                        } else {
1314                                liter += OPTROM_BURST_DWORDS - 1;
1315                                faddr += OPTROM_BURST_DWORDS - 1;
1316                                dwptr += OPTROM_BURST_DWORDS - 1;
1317                                continue;
1318                        }
1319                }
1320
1321                ret = qla24xx_write_flash_dword(ha,
1322                    flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1323                if (ret != QLA_SUCCESS) {
1324                        ql_dbg(ql_dbg_user, vha, 0x7006,
1325                            "Unable to program flash address=%x data=%x.\n",
1326                            faddr, *dwptr);
1327                        break;
1328                }
1329
1330                /* Do sector protect. */
1331                if (ha->fdt_unprotect_sec_cmd &&
1332                    ((faddr & rest_addr) == rest_addr))
1333                        qla24xx_write_flash_dword(ha,
1334                            ha->fdt_protect_sec_cmd,
1335                            (fdata & 0xff00) | ((fdata << 16) &
1336                            0xff0000) | ((fdata >> 16) & 0xff));
1337        }
1338
1339        ret = qla24xx_protect_flash(vha);
1340        if (ret != QLA_SUCCESS)
1341                ql_log(ql_log_warn, vha, 0x7099,
1342                    "Unable to protect flash after update.\n");
1343done:
1344        if (optrom)
1345                dma_free_coherent(&ha->pdev->dev,
1346                    OPTROM_BURST_SIZE, optrom, optrom_dma);
1347
1348        return ret;
1349}
1350
1351uint8_t *
1352qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1353    uint32_t bytes)
1354{
1355        uint32_t i;
1356        uint16_t *wptr;
1357        struct qla_hw_data *ha = vha->hw;
1358
1359        /* Word reads to NVRAM via registers. */
1360        wptr = (uint16_t *)buf;
1361        qla2x00_lock_nvram_access(ha);
1362        for (i = 0; i < bytes >> 1; i++, naddr++)
1363                wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1364                    naddr));
1365        qla2x00_unlock_nvram_access(ha);
1366
1367        return buf;
1368}
1369
1370uint8_t *
1371qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1372    uint32_t bytes)
1373{
1374        uint32_t i;
1375        uint32_t *dwptr;
1376        struct qla_hw_data *ha = vha->hw;
1377
1378        if (IS_P3P_TYPE(ha))
1379                return  buf;
1380
1381        /* Dword reads to flash. */
1382        dwptr = (uint32_t *)buf;
1383        for (i = 0; i < bytes >> 2; i++, naddr++)
1384                dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1385                    nvram_data_addr(ha, naddr)));
1386
1387        return buf;
1388}
1389
1390int
1391qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1392    uint32_t bytes)
1393{
1394        int ret, stat;
1395        uint32_t i;
1396        uint16_t *wptr;
1397        unsigned long flags;
1398        struct qla_hw_data *ha = vha->hw;
1399
1400        ret = QLA_SUCCESS;
1401
1402        spin_lock_irqsave(&ha->hardware_lock, flags);
1403        qla2x00_lock_nvram_access(ha);
1404
1405        /* Disable NVRAM write-protection. */
1406        stat = qla2x00_clear_nvram_protection(ha);
1407
1408        wptr = (uint16_t *)buf;
1409        for (i = 0; i < bytes >> 1; i++, naddr++) {
1410                qla2x00_write_nvram_word(ha, naddr,
1411                    cpu_to_le16(*wptr));
1412                wptr++;
1413        }
1414
1415        /* Enable NVRAM write-protection. */
1416        qla2x00_set_nvram_protection(ha, stat);
1417
1418        qla2x00_unlock_nvram_access(ha);
1419        spin_unlock_irqrestore(&ha->hardware_lock, flags);
1420
1421        return ret;
1422}
1423
1424int
1425qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1426    uint32_t bytes)
1427{
1428        int ret;
1429        uint32_t i;
1430        uint32_t *dwptr;
1431        struct qla_hw_data *ha = vha->hw;
1432        struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1433
1434        ret = QLA_SUCCESS;
1435
1436        if (IS_P3P_TYPE(ha))
1437                return ret;
1438
1439        /* Enable flash write. */
1440        WRT_REG_DWORD(&reg->ctrl_status,
1441            RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1442        RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1443
1444        /* Disable NVRAM write-protection. */
1445        qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1446        qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1447
1448        /* Dword writes to flash. */
1449        dwptr = (uint32_t *)buf;
1450        for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1451                ret = qla24xx_write_flash_dword(ha,
1452                    nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1453                if (ret != QLA_SUCCESS) {
1454                        ql_dbg(ql_dbg_user, vha, 0x709a,
1455                            "Unable to program nvram address=%x data=%x.\n",
1456                            naddr, *dwptr);
1457                        break;
1458                }
1459        }
1460
1461        /* Enable NVRAM write-protection. */
1462        qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1463
1464        /* Disable flash write. */
1465        WRT_REG_DWORD(&reg->ctrl_status,
1466            RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1467        RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1468
1469        return ret;
1470}
1471
1472uint8_t *
1473qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1474    uint32_t bytes)
1475{
1476        uint32_t i;
1477        uint32_t *dwptr;
1478        struct qla_hw_data *ha = vha->hw;
1479
1480        /* Dword reads to flash. */
1481        dwptr = (uint32_t *)buf;
1482        for (i = 0; i < bytes >> 2; i++, naddr++)
1483                dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1484                    flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1485
1486        return buf;
1487}
1488
1489int
1490qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1491    uint32_t bytes)
1492{
1493        struct qla_hw_data *ha = vha->hw;
1494#define RMW_BUFFER_SIZE (64 * 1024)
1495        uint8_t *dbuf;
1496
1497        dbuf = vmalloc(RMW_BUFFER_SIZE);
1498        if (!dbuf)
1499                return QLA_MEMORY_ALLOC_FAILED;
1500        ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1501            RMW_BUFFER_SIZE);
1502        memcpy(dbuf + (naddr << 2), buf, bytes);
1503        ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1504            RMW_BUFFER_SIZE);
1505        vfree(dbuf);
1506
1507        return QLA_SUCCESS;
1508}
1509
1510static inline void
1511qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1512{
1513        if (IS_QLA2322(ha)) {
1514                /* Flip all colors. */
1515                if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1516                        /* Turn off. */
1517                        ha->beacon_color_state = 0;
1518                        *pflags = GPIO_LED_ALL_OFF;
1519                } else {
1520                        /* Turn on. */
1521                        ha->beacon_color_state = QLA_LED_ALL_ON;
1522                        *pflags = GPIO_LED_RGA_ON;
1523                }
1524        } else {
1525                /* Flip green led only. */
1526                if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1527                        /* Turn off. */
1528                        ha->beacon_color_state = 0;
1529                        *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1530                } else {
1531                        /* Turn on. */
1532                        ha->beacon_color_state = QLA_LED_GRN_ON;
1533                        *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1534                }
1535        }
1536}
1537
1538#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1539
1540void
1541qla2x00_beacon_blink(struct scsi_qla_host *vha)
1542{
1543        uint16_t gpio_enable;
1544        uint16_t gpio_data;
1545        uint16_t led_color = 0;
1546        unsigned long flags;
1547        struct qla_hw_data *ha = vha->hw;
1548        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1549
1550        if (IS_P3P_TYPE(ha))
1551                return;
1552
1553        spin_lock_irqsave(&ha->hardware_lock, flags);
1554
1555        /* Save the Original GPIOE. */
1556        if (ha->pio_address) {
1557                gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1558                gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1559        } else {
1560                gpio_enable = RD_REG_WORD(&reg->gpioe);
1561                gpio_data = RD_REG_WORD(&reg->gpiod);
1562        }
1563
1564        /* Set the modified gpio_enable values */
1565        gpio_enable |= GPIO_LED_MASK;
1566
1567        if (ha->pio_address) {
1568                WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1569        } else {
1570                WRT_REG_WORD(&reg->gpioe, gpio_enable);
1571                RD_REG_WORD(&reg->gpioe);
1572        }
1573
1574        qla2x00_flip_colors(ha, &led_color);
1575
1576        /* Clear out any previously set LED color. */
1577        gpio_data &= ~GPIO_LED_MASK;
1578
1579        /* Set the new input LED color to GPIOD. */
1580        gpio_data |= led_color;
1581
1582        /* Set the modified gpio_data values */
1583        if (ha->pio_address) {
1584                WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1585        } else {
1586                WRT_REG_WORD(&reg->gpiod, gpio_data);
1587                RD_REG_WORD(&reg->gpiod);
1588        }
1589
1590        spin_unlock_irqrestore(&ha->hardware_lock, flags);
1591}
1592
1593int
1594qla2x00_beacon_on(struct scsi_qla_host *vha)
1595{
1596        uint16_t gpio_enable;
1597        uint16_t gpio_data;
1598        unsigned long flags;
1599        struct qla_hw_data *ha = vha->hw;
1600        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1601
1602        ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1603        ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1604
1605        if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1606                ql_log(ql_log_warn, vha, 0x709b,
1607                    "Unable to update fw options (beacon on).\n");
1608                return QLA_FUNCTION_FAILED;
1609        }
1610
1611        /* Turn off LEDs. */
1612        spin_lock_irqsave(&ha->hardware_lock, flags);
1613        if (ha->pio_address) {
1614                gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1615                gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1616        } else {
1617                gpio_enable = RD_REG_WORD(&reg->gpioe);
1618                gpio_data = RD_REG_WORD(&reg->gpiod);
1619        }
1620        gpio_enable |= GPIO_LED_MASK;
1621
1622        /* Set the modified gpio_enable values. */
1623        if (ha->pio_address) {
1624                WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1625        } else {
1626                WRT_REG_WORD(&reg->gpioe, gpio_enable);
1627                RD_REG_WORD(&reg->gpioe);
1628        }
1629
1630        /* Clear out previously set LED colour. */
1631        gpio_data &= ~GPIO_LED_MASK;
1632        if (ha->pio_address) {
1633                WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1634        } else {
1635                WRT_REG_WORD(&reg->gpiod, gpio_data);
1636                RD_REG_WORD(&reg->gpiod);
1637        }
1638        spin_unlock_irqrestore(&ha->hardware_lock, flags);
1639
1640        /*
1641         * Let the per HBA timer kick off the blinking process based on
1642         * the following flags. No need to do anything else now.
1643         */
1644        ha->beacon_blink_led = 1;
1645        ha->beacon_color_state = 0;
1646
1647        return QLA_SUCCESS;
1648}
1649
1650int
1651qla2x00_beacon_off(struct scsi_qla_host *vha)
1652{
1653        int rval = QLA_SUCCESS;
1654        struct qla_hw_data *ha = vha->hw;
1655
1656        ha->beacon_blink_led = 0;
1657
1658        /* Set the on flag so when it gets flipped it will be off. */
1659        if (IS_QLA2322(ha))
1660                ha->beacon_color_state = QLA_LED_ALL_ON;
1661        else
1662                ha->beacon_color_state = QLA_LED_GRN_ON;
1663
1664        ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1665
1666        ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1667        ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1668
1669        rval = qla2x00_set_fw_options(vha, ha->fw_options);
1670        if (rval != QLA_SUCCESS)
1671                ql_log(ql_log_warn, vha, 0x709c,
1672                    "Unable to update fw options (beacon off).\n");
1673        return rval;
1674}
1675
1676
1677static inline void
1678qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1679{
1680        /* Flip all colors. */
1681        if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1682                /* Turn off. */
1683                ha->beacon_color_state = 0;
1684                *pflags = 0;
1685        } else {
1686                /* Turn on. */
1687                ha->beacon_color_state = QLA_LED_ALL_ON;
1688                *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1689        }
1690}
1691
1692void
1693qla24xx_beacon_blink(struct scsi_qla_host *vha)
1694{
1695        uint16_t led_color = 0;
1696        uint32_t gpio_data;
1697        unsigned long flags;
1698        struct qla_hw_data *ha = vha->hw;
1699        struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1700
1701        /* Save the Original GPIOD. */
1702        spin_lock_irqsave(&ha->hardware_lock, flags);
1703        gpio_data = RD_REG_DWORD(&reg->gpiod);
1704
1705        /* Enable the gpio_data reg for update. */
1706        gpio_data |= GPDX_LED_UPDATE_MASK;
1707
1708        WRT_REG_DWORD(&reg->gpiod, gpio_data);
1709        gpio_data = RD_REG_DWORD(&reg->gpiod);
1710
1711        /* Set the color bits. */
1712        qla24xx_flip_colors(ha, &led_color);
1713
1714        /* Clear out any previously set LED color. */
1715        gpio_data &= ~GPDX_LED_COLOR_MASK;
1716
1717        /* Set the new input LED color to GPIOD. */
1718        gpio_data |= led_color;
1719
1720        /* Set the modified gpio_data values. */
1721        WRT_REG_DWORD(&reg->gpiod, gpio_data);
1722        gpio_data = RD_REG_DWORD(&reg->gpiod);
1723        spin_unlock_irqrestore(&ha->hardware_lock, flags);
1724}
1725
1726static uint32_t
1727qla83xx_select_led_port(struct qla_hw_data *ha)
1728{
1729        uint32_t led_select_value = 0;
1730
1731        if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
1732                goto out;
1733
1734        if (ha->port_no == 0)
1735                led_select_value = QLA83XX_LED_PORT0;
1736        else
1737                led_select_value = QLA83XX_LED_PORT1;
1738
1739out:
1740        return led_select_value;
1741}
1742
1743void
1744qla83xx_beacon_blink(struct scsi_qla_host *vha)
1745{
1746        uint32_t led_select_value;
1747        struct qla_hw_data *ha = vha->hw;
1748        uint16_t led_cfg[6];
1749        uint16_t orig_led_cfg[6];
1750        uint32_t led_10_value, led_43_value;
1751
1752        if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha))
1753                return;
1754
1755        if (!ha->beacon_blink_led)
1756                return;
1757
1758        if (IS_QLA27XX(ha)) {
1759                qla2x00_write_ram_word(vha, 0x1003, 0x40000230);
1760                qla2x00_write_ram_word(vha, 0x1004, 0x40000230);
1761        } else if (IS_QLA2031(ha)) {
1762                led_select_value = qla83xx_select_led_port(ha);
1763
1764                qla83xx_wr_reg(vha, led_select_value, 0x40000230);
1765                qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230);
1766        } else if (IS_QLA8031(ha)) {
1767                led_select_value = qla83xx_select_led_port(ha);
1768
1769                qla83xx_rd_reg(vha, led_select_value, &led_10_value);
1770                qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value);
1771                qla83xx_wr_reg(vha, led_select_value, 0x01f44000);
1772                msleep(500);
1773                qla83xx_wr_reg(vha, led_select_value, 0x400001f4);
1774                msleep(1000);
1775                qla83xx_wr_reg(vha, led_select_value, led_10_value);
1776                qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value);
1777        } else if (IS_QLA81XX(ha)) {
1778                int rval;
1779
1780                /* Save Current */
1781                rval = qla81xx_get_led_config(vha, orig_led_cfg);
1782                /* Do the blink */
1783                if (rval == QLA_SUCCESS) {
1784                        if (IS_QLA81XX(ha)) {
1785                                led_cfg[0] = 0x4000;
1786                                led_cfg[1] = 0x2000;
1787                                led_cfg[2] = 0;
1788                                led_cfg[3] = 0;
1789                                led_cfg[4] = 0;
1790                                led_cfg[5] = 0;
1791                        } else {
1792                                led_cfg[0] = 0x4000;
1793                                led_cfg[1] = 0x4000;
1794                                led_cfg[2] = 0x4000;
1795                                led_cfg[3] = 0x2000;
1796                                led_cfg[4] = 0;
1797                                led_cfg[5] = 0x2000;
1798                        }
1799                        rval = qla81xx_set_led_config(vha, led_cfg);
1800                        msleep(1000);
1801                        if (IS_QLA81XX(ha)) {
1802                                led_cfg[0] = 0x4000;
1803                                led_cfg[1] = 0x2000;
1804                                led_cfg[2] = 0;
1805                        } else {
1806                                led_cfg[0] = 0x4000;
1807                                led_cfg[1] = 0x2000;
1808                                led_cfg[2] = 0x4000;
1809                                led_cfg[3] = 0x4000;
1810                                led_cfg[4] = 0;
1811                                led_cfg[5] = 0x2000;
1812                        }
1813                        rval = qla81xx_set_led_config(vha, led_cfg);
1814                }
1815                /* On exit, restore original (presumes no status change) */
1816                qla81xx_set_led_config(vha, orig_led_cfg);
1817        }
1818}
1819
1820int
1821qla24xx_beacon_on(struct scsi_qla_host *vha)
1822{
1823        uint32_t gpio_data;
1824        unsigned long flags;
1825        struct qla_hw_data *ha = vha->hw;
1826        struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1827
1828        if (IS_P3P_TYPE(ha))
1829                return QLA_SUCCESS;
1830
1831        if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1832                goto skip_gpio; /* let blink handle it */
1833
1834        if (ha->beacon_blink_led == 0) {
1835                /* Enable firmware for update */
1836                ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1837
1838                if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1839                        return QLA_FUNCTION_FAILED;
1840
1841                if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1842                    QLA_SUCCESS) {
1843                        ql_log(ql_log_warn, vha, 0x7009,
1844                            "Unable to update fw options (beacon on).\n");
1845                        return QLA_FUNCTION_FAILED;
1846                }
1847
1848                if (IS_QLA2031(ha) || IS_QLA27XX(ha))
1849                        goto skip_gpio;
1850
1851                spin_lock_irqsave(&ha->hardware_lock, flags);
1852                gpio_data = RD_REG_DWORD(&reg->gpiod);
1853
1854                /* Enable the gpio_data reg for update. */
1855                gpio_data |= GPDX_LED_UPDATE_MASK;
1856                WRT_REG_DWORD(&reg->gpiod, gpio_data);
1857                RD_REG_DWORD(&reg->gpiod);
1858
1859                spin_unlock_irqrestore(&ha->hardware_lock, flags);
1860        }
1861
1862        /* So all colors blink together. */
1863        ha->beacon_color_state = 0;
1864
1865skip_gpio:
1866        /* Let the per HBA timer kick off the blinking process. */
1867        ha->beacon_blink_led = 1;
1868
1869        return QLA_SUCCESS;
1870}
1871
1872int
1873qla24xx_beacon_off(struct scsi_qla_host *vha)
1874{
1875        uint32_t gpio_data;
1876        unsigned long flags;
1877        struct qla_hw_data *ha = vha->hw;
1878        struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1879
1880        if (IS_P3P_TYPE(ha))
1881                return QLA_SUCCESS;
1882
1883        ha->beacon_blink_led = 0;
1884
1885        if (IS_QLA2031(ha) || IS_QLA27XX(ha))
1886                goto set_fw_options;
1887
1888        if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1889                return QLA_SUCCESS;
1890
1891        ha->beacon_color_state = QLA_LED_ALL_ON;
1892
1893        ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1894
1895        /* Give control back to firmware. */
1896        spin_lock_irqsave(&ha->hardware_lock, flags);
1897        gpio_data = RD_REG_DWORD(&reg->gpiod);
1898
1899        /* Disable the gpio_data reg for update. */
1900        gpio_data &= ~GPDX_LED_UPDATE_MASK;
1901        WRT_REG_DWORD(&reg->gpiod, gpio_data);
1902        RD_REG_DWORD(&reg->gpiod);
1903        spin_unlock_irqrestore(&ha->hardware_lock, flags);
1904
1905set_fw_options:
1906        ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1907
1908        if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1909                ql_log(ql_log_warn, vha, 0x704d,
1910                    "Unable to update fw options (beacon on).\n");
1911                return QLA_FUNCTION_FAILED;
1912        }
1913
1914        if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1915                ql_log(ql_log_warn, vha, 0x704e,
1916                    "Unable to update fw options (beacon on).\n");
1917                return QLA_FUNCTION_FAILED;
1918        }
1919
1920        return QLA_SUCCESS;
1921}
1922
1923
1924/*
1925 * Flash support routines
1926 */
1927
1928/**
1929 * qla2x00_flash_enable() - Setup flash for reading and writing.
1930 * @ha: HA context
1931 */
1932static void
1933qla2x00_flash_enable(struct qla_hw_data *ha)
1934{
1935        uint16_t data;
1936        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1937
1938        data = RD_REG_WORD(&reg->ctrl_status);
1939        data |= CSR_FLASH_ENABLE;
1940        WRT_REG_WORD(&reg->ctrl_status, data);
1941        RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1942}
1943
1944/**
1945 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1946 * @ha: HA context
1947 */
1948static void
1949qla2x00_flash_disable(struct qla_hw_data *ha)
1950{
1951        uint16_t data;
1952        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1953
1954        data = RD_REG_WORD(&reg->ctrl_status);
1955        data &= ~(CSR_FLASH_ENABLE);
1956        WRT_REG_WORD(&reg->ctrl_status, data);
1957        RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1958}
1959
1960/**
1961 * qla2x00_read_flash_byte() - Reads a byte from flash
1962 * @ha: HA context
1963 * @addr: Address in flash to read
1964 *
1965 * A word is read from the chip, but, only the lower byte is valid.
1966 *
1967 * Returns the byte read from flash @addr.
1968 */
1969static uint8_t
1970qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1971{
1972        uint16_t data;
1973        uint16_t bank_select;
1974        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1975
1976        bank_select = RD_REG_WORD(&reg->ctrl_status);
1977
1978        if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1979                /* Specify 64K address range: */
1980                /*  clear out Module Select and Flash Address bits [19:16]. */
1981                bank_select &= ~0xf8;
1982                bank_select |= addr >> 12 & 0xf0;
1983                bank_select |= CSR_FLASH_64K_BANK;
1984                WRT_REG_WORD(&reg->ctrl_status, bank_select);
1985                RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1986
1987                WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1988                data = RD_REG_WORD(&reg->flash_data);
1989
1990                return (uint8_t)data;
1991        }
1992
1993        /* Setup bit 16 of flash address. */
1994        if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1995                bank_select |= CSR_FLASH_64K_BANK;
1996                WRT_REG_WORD(&reg->ctrl_status, bank_select);
1997                RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1998        } else if (((addr & BIT_16) == 0) &&
1999            (bank_select & CSR_FLASH_64K_BANK)) {
2000                bank_select &= ~(CSR_FLASH_64K_BANK);
2001                WRT_REG_WORD(&reg->ctrl_status, bank_select);
2002                RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2003        }
2004
2005        /* Always perform IO mapped accesses to the FLASH registers. */
2006        if (ha->pio_address) {
2007                uint16_t data2;
2008
2009                WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2010                do {
2011                        data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
2012                        barrier();
2013                        cpu_relax();
2014                        data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
2015                } while (data != data2);
2016        } else {
2017                WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2018                data = qla2x00_debounce_register(&reg->flash_data);
2019        }
2020
2021        return (uint8_t)data;
2022}
2023
2024/**
2025 * qla2x00_write_flash_byte() - Write a byte to flash
2026 * @ha: HA context
2027 * @addr: Address in flash to write
2028 * @data: Data to write
2029 */
2030static void
2031qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
2032{
2033        uint16_t bank_select;
2034        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2035
2036        bank_select = RD_REG_WORD(&reg->ctrl_status);
2037        if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2038                /* Specify 64K address range: */
2039                /*  clear out Module Select and Flash Address bits [19:16]. */
2040                bank_select &= ~0xf8;
2041                bank_select |= addr >> 12 & 0xf0;
2042                bank_select |= CSR_FLASH_64K_BANK;
2043                WRT_REG_WORD(&reg->ctrl_status, bank_select);
2044                RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2045
2046                WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2047                RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
2048                WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
2049                RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
2050
2051                return;
2052        }
2053
2054        /* Setup bit 16 of flash address. */
2055        if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
2056                bank_select |= CSR_FLASH_64K_BANK;
2057                WRT_REG_WORD(&reg->ctrl_status, bank_select);
2058                RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2059        } else if (((addr & BIT_16) == 0) &&
2060            (bank_select & CSR_FLASH_64K_BANK)) {
2061                bank_select &= ~(CSR_FLASH_64K_BANK);
2062                WRT_REG_WORD(&reg->ctrl_status, bank_select);
2063                RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2064        }
2065
2066        /* Always perform IO mapped accesses to the FLASH registers. */
2067        if (ha->pio_address) {
2068                WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2069                WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
2070        } else {
2071                WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2072                RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
2073                WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
2074                RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
2075        }
2076}
2077
2078/**
2079 * qla2x00_poll_flash() - Polls flash for completion.
2080 * @ha: HA context
2081 * @addr: Address in flash to poll
2082 * @poll_data: Data to be polled
2083 * @man_id: Flash manufacturer ID
2084 * @flash_id: Flash ID
2085 *
2086 * This function polls the device until bit 7 of what is read matches data
2087 * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
2088 * out (a fatal error).  The flash book recommeds reading bit 7 again after
2089 * reading bit 5 as a 1.
2090 *
2091 * Returns 0 on success, else non-zero.
2092 */
2093static int
2094qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
2095    uint8_t man_id, uint8_t flash_id)
2096{
2097        int status;
2098        uint8_t flash_data;
2099        uint32_t cnt;
2100
2101        status = 1;
2102
2103        /* Wait for 30 seconds for command to finish. */
2104        poll_data &= BIT_7;
2105        for (cnt = 3000000; cnt; cnt--) {
2106                flash_data = qla2x00_read_flash_byte(ha, addr);
2107                if ((flash_data & BIT_7) == poll_data) {
2108                        status = 0;
2109                        break;
2110                }
2111
2112                if (man_id != 0x40 && man_id != 0xda) {
2113                        if ((flash_data & BIT_5) && cnt > 2)
2114                                cnt = 2;
2115                }
2116                udelay(10);
2117                barrier();
2118                cond_resched();
2119        }
2120        return status;
2121}
2122
2123/**
2124 * qla2x00_program_flash_address() - Programs a flash address
2125 * @ha: HA context
2126 * @addr: Address in flash to program
2127 * @data: Data to be written in flash
2128 * @man_id: Flash manufacturer ID
2129 * @flash_id: Flash ID
2130 *
2131 * Returns 0 on success, else non-zero.
2132 */
2133static int
2134qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
2135    uint8_t data, uint8_t man_id, uint8_t flash_id)
2136{
2137        /* Write Program Command Sequence. */
2138        if (IS_OEM_001(ha)) {
2139                qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2140                qla2x00_write_flash_byte(ha, 0x555, 0x55);
2141                qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
2142                qla2x00_write_flash_byte(ha, addr, data);
2143        } else {
2144                if (man_id == 0xda && flash_id == 0xc1) {
2145                        qla2x00_write_flash_byte(ha, addr, data);
2146                        if (addr & 0x7e)
2147                                return 0;
2148                } else {
2149                        qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2150                        qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2151                        qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
2152                        qla2x00_write_flash_byte(ha, addr, data);
2153                }
2154        }
2155
2156        udelay(150);
2157
2158        /* Wait for write to complete. */
2159        return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
2160}
2161
2162/**
2163 * qla2x00_erase_flash() - Erase the flash.
2164 * @ha: HA context
2165 * @man_id: Flash manufacturer ID
2166 * @flash_id: Flash ID
2167 *
2168 * Returns 0 on success, else non-zero.
2169 */
2170static int
2171qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
2172{
2173        /* Individual Sector Erase Command Sequence */
2174        if (IS_OEM_001(ha)) {
2175                qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2176                qla2x00_write_flash_byte(ha, 0x555, 0x55);
2177                qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
2178                qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2179                qla2x00_write_flash_byte(ha, 0x555, 0x55);
2180                qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
2181        } else {
2182                qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2183                qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2184                qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2185                qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2186                qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2187                qla2x00_write_flash_byte(ha, 0x5555, 0x10);
2188        }
2189
2190        udelay(150);
2191
2192        /* Wait for erase to complete. */
2193        return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
2194}
2195
2196/**
2197 * qla2x00_erase_flash_sector() - Erase a flash sector.
2198 * @ha: HA context
2199 * @addr: Flash sector to erase
2200 * @sec_mask: Sector address mask
2201 * @man_id: Flash manufacturer ID
2202 * @flash_id: Flash ID
2203 *
2204 * Returns 0 on success, else non-zero.
2205 */
2206static int
2207qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
2208    uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
2209{
2210        /* Individual Sector Erase Command Sequence */
2211        qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2212        qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2213        qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2214        qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2215        qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2216        if (man_id == 0x1f && flash_id == 0x13)
2217                qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2218        else
2219                qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2220
2221        udelay(150);
2222
2223        /* Wait for erase to complete. */
2224        return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2225}
2226
2227/**
2228 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2229 * @man_id: Flash manufacturer ID
2230 * @flash_id: Flash ID
2231 */
2232static void
2233qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
2234    uint8_t *flash_id)
2235{
2236        qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2237        qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2238        qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2239        *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2240        *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2241        qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2242        qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2243        qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2244}
2245
2246static void
2247qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2248        uint32_t saddr, uint32_t length)
2249{
2250        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2251        uint32_t midpoint, ilength;
2252        uint8_t data;
2253
2254        midpoint = length / 2;
2255
2256        WRT_REG_WORD(&reg->nvram, 0);
2257        RD_REG_WORD(&reg->nvram);
2258        for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2259                if (ilength == midpoint) {
2260                        WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2261                        RD_REG_WORD(&reg->nvram);
2262                }
2263                data = qla2x00_read_flash_byte(ha, saddr);
2264                if (saddr % 100)
2265                        udelay(10);
2266                *tmp_buf = data;
2267                cond_resched();
2268        }
2269}
2270
2271static inline void
2272qla2x00_suspend_hba(struct scsi_qla_host *vha)
2273{
2274        int cnt;
2275        unsigned long flags;
2276        struct qla_hw_data *ha = vha->hw;
2277        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2278
2279        /* Suspend HBA. */
2280        scsi_block_requests(vha->host);
2281        ha->isp_ops->disable_intrs(ha);
2282        set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2283
2284        /* Pause RISC. */
2285        spin_lock_irqsave(&ha->hardware_lock, flags);
2286        WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2287        RD_REG_WORD(&reg->hccr);
2288        if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2289                for (cnt = 0; cnt < 30000; cnt++) {
2290                        if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
2291                                break;
2292                        udelay(100);
2293                }
2294        } else {
2295                udelay(10);
2296        }
2297        spin_unlock_irqrestore(&ha->hardware_lock, flags);
2298}
2299
2300static inline void
2301qla2x00_resume_hba(struct scsi_qla_host *vha)
2302{
2303        struct qla_hw_data *ha = vha->hw;
2304
2305        /* Resume HBA. */
2306        clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2307        set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2308        qla2xxx_wake_dpc(vha);
2309        qla2x00_wait_for_chip_reset(vha);
2310        scsi_unblock_requests(vha->host);
2311}
2312
2313uint8_t *
2314qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2315    uint32_t offset, uint32_t length)
2316{
2317        uint32_t addr, midpoint;
2318        uint8_t *data;
2319        struct qla_hw_data *ha = vha->hw;
2320        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2321
2322        /* Suspend HBA. */
2323        qla2x00_suspend_hba(vha);
2324
2325        /* Go with read. */
2326        midpoint = ha->optrom_size / 2;
2327
2328        qla2x00_flash_enable(ha);
2329        WRT_REG_WORD(&reg->nvram, 0);
2330        RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
2331        for (addr = offset, data = buf; addr < length; addr++, data++) {
2332                if (addr == midpoint) {
2333                        WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2334                        RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
2335                }
2336
2337                *data = qla2x00_read_flash_byte(ha, addr);
2338        }
2339        qla2x00_flash_disable(ha);
2340
2341        /* Resume HBA. */
2342        qla2x00_resume_hba(vha);
2343
2344        return buf;
2345}
2346
2347int
2348qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2349    uint32_t offset, uint32_t length)
2350{
2351
2352        int rval;
2353        uint8_t man_id, flash_id, sec_number, data;
2354        uint16_t wd;
2355        uint32_t addr, liter, sec_mask, rest_addr;
2356        struct qla_hw_data *ha = vha->hw;
2357        struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2358
2359        /* Suspend HBA. */
2360        qla2x00_suspend_hba(vha);
2361
2362        rval = QLA_SUCCESS;
2363        sec_number = 0;
2364
2365        /* Reset ISP chip. */
2366        WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2367        pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2368
2369        /* Go with write. */
2370        qla2x00_flash_enable(ha);
2371        do {    /* Loop once to provide quick error exit */
2372                /* Structure of flash memory based on manufacturer */
2373                if (IS_OEM_001(ha)) {
2374                        /* OEM variant with special flash part. */
2375                        man_id = flash_id = 0;
2376                        rest_addr = 0xffff;
2377                        sec_mask   = 0x10000;
2378                        goto update_flash;
2379                }
2380                qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2381                switch (man_id) {
2382                case 0x20: /* ST flash. */
2383                        if (flash_id == 0xd2 || flash_id == 0xe3) {
2384                                /*
2385                                 * ST m29w008at part - 64kb sector size with
2386                                 * 32kb,8kb,8kb,16kb sectors at memory address
2387                                 * 0xf0000.
2388                                 */
2389                                rest_addr = 0xffff;
2390                                sec_mask = 0x10000;
2391                                break;
2392                        }
2393                        /*
2394                         * ST m29w010b part - 16kb sector size
2395                         * Default to 16kb sectors
2396                         */
2397                        rest_addr = 0x3fff;
2398                        sec_mask = 0x1c000;
2399                        break;
2400                case 0x40: /* Mostel flash. */
2401                        /* Mostel v29c51001 part - 512 byte sector size. */
2402                        rest_addr = 0x1ff;
2403                        sec_mask = 0x1fe00;
2404                        break;
2405                case 0xbf: /* SST flash. */
2406                        /* SST39sf10 part - 4kb sector size. */
2407                        rest_addr = 0xfff;
2408                        sec_mask = 0x1f000;
2409                        break;
2410                case 0xda: /* Winbond flash. */
2411                        /* Winbond W29EE011 part - 256 byte sector size. */
2412                        rest_addr = 0x7f;
2413                        sec_mask = 0x1ff80;
2414                        break;
2415                case 0xc2: /* Macronix flash. */
2416                        /* 64k sector size. */
2417                        if (flash_id == 0x38 || flash_id == 0x4f) {
2418                                rest_addr = 0xffff;
2419                                sec_mask = 0x10000;
2420                                break;
2421                        }
2422                        /* Fall through... */
2423
2424                case 0x1f: /* Atmel flash. */
2425                        /* 512k sector size. */
2426                        if (flash_id == 0x13) {
2427                                rest_addr = 0x7fffffff;
2428                                sec_mask =   0x80000000;
2429                                break;
2430                        }
2431                        /* Fall through... */
2432
2433                case 0x01: /* AMD flash. */
2434                        if (flash_id == 0x38 || flash_id == 0x40 ||
2435                            flash_id == 0x4f) {
2436                                /* Am29LV081 part - 64kb sector size. */
2437                                /* Am29LV002BT part - 64kb sector size. */
2438                                rest_addr = 0xffff;
2439                                sec_mask = 0x10000;
2440                                break;
2441                        } else if (flash_id == 0x3e) {
2442                                /*
2443                                 * Am29LV008b part - 64kb sector size with
2444                                 * 32kb,8kb,8kb,16kb sector at memory address
2445                                 * h0xf0000.
2446                                 */
2447                                rest_addr = 0xffff;
2448                                sec_mask = 0x10000;
2449                                break;
2450                        } else if (flash_id == 0x20 || flash_id == 0x6e) {
2451                                /*
2452                                 * Am29LV010 part or AM29f010 - 16kb sector
2453                                 * size.
2454                                 */
2455                                rest_addr = 0x3fff;
2456                                sec_mask = 0x1c000;
2457                                break;
2458                        } else if (flash_id == 0x6d) {
2459                                /* Am29LV001 part - 8kb sector size. */
2460                                rest_addr = 0x1fff;
2461                                sec_mask = 0x1e000;
2462                                break;
2463                        }
2464                default:
2465                        /* Default to 16 kb sector size. */
2466                        rest_addr = 0x3fff;
2467                        sec_mask = 0x1c000;
2468                        break;
2469                }
2470
2471update_flash:
2472                if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2473                        if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2474                                rval = QLA_FUNCTION_FAILED;
2475                                break;
2476                        }
2477                }
2478
2479                for (addr = offset, liter = 0; liter < length; liter++,
2480                    addr++) {
2481                        data = buf[liter];
2482                        /* Are we at the beginning of a sector? */
2483                        if ((addr & rest_addr) == 0) {
2484                                if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2485                                        if (addr >= 0x10000UL) {
2486                                                if (((addr >> 12) & 0xf0) &&
2487                                                    ((man_id == 0x01 &&
2488                                                        flash_id == 0x3e) ||
2489                                                     (man_id == 0x20 &&
2490                                                         flash_id == 0xd2))) {
2491                                                        sec_number++;
2492                                                        if (sec_number == 1) {
2493                                                                rest_addr =
2494                                                                    0x7fff;
2495                                                                sec_mask =
2496                                                                    0x18000;
2497                                                        } else if (
2498                                                            sec_number == 2 ||
2499                                                            sec_number == 3) {
2500                                                                rest_addr =
2501                                                                    0x1fff;
2502                                                                sec_mask =
2503                                                                    0x1e000;
2504                                                        } else if (
2505                                                            sec_number == 4) {
2506                                                                rest_addr =
2507                                                                    0x3fff;
2508                                                                sec_mask =
2509                                                                    0x1c000;
2510                                                        }
2511                                                }
2512                                        }
2513                                } else if (addr == ha->optrom_size / 2) {
2514                                        WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2515                                        RD_REG_WORD(&reg->nvram);
2516                                }
2517
2518                                if (flash_id == 0xda && man_id == 0xc1) {
2519                                        qla2x00_write_flash_byte(ha, 0x5555,
2520                                            0xaa);
2521                                        qla2x00_write_flash_byte(ha, 0x2aaa,
2522                                            0x55);
2523                                        qla2x00_write_flash_byte(ha, 0x5555,
2524                                            0xa0);
2525                                } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2526                                        /* Then erase it */
2527                                        if (qla2x00_erase_flash_sector(ha,
2528                                            addr, sec_mask, man_id,
2529                                            flash_id)) {
2530                                                rval = QLA_FUNCTION_FAILED;
2531                                                break;
2532                                        }
2533                                        if (man_id == 0x01 && flash_id == 0x6d)
2534                                                sec_number++;
2535                                }
2536                        }
2537
2538                        if (man_id == 0x01 && flash_id == 0x6d) {
2539                                if (sec_number == 1 &&
2540                                    addr == (rest_addr - 1)) {
2541                                        rest_addr = 0x0fff;
2542                                        sec_mask   = 0x1f000;
2543                                } else if (sec_number == 3 && (addr & 0x7ffe)) {
2544                                        rest_addr = 0x3fff;
2545                                        sec_mask   = 0x1c000;
2546                                }
2547                        }
2548
2549                        if (qla2x00_program_flash_address(ha, addr, data,
2550                            man_id, flash_id)) {
2551                                rval = QLA_FUNCTION_FAILED;
2552                                break;
2553                        }
2554                        cond_resched();
2555                }
2556        } while (0);
2557        qla2x00_flash_disable(ha);
2558
2559        /* Resume HBA. */
2560        qla2x00_resume_hba(vha);
2561
2562        return rval;
2563}
2564
2565uint8_t *
2566qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2567    uint32_t offset, uint32_t length)
2568{
2569        struct qla_hw_data *ha = vha->hw;
2570
2571        /* Suspend HBA. */
2572        scsi_block_requests(vha->host);
2573        set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2574
2575        /* Go with read. */
2576        qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2577
2578        /* Resume HBA. */
2579        clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2580        scsi_unblock_requests(vha->host);
2581
2582        return buf;
2583}
2584
2585int
2586qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2587    uint32_t offset, uint32_t length)
2588{
2589        int rval;
2590        struct qla_hw_data *ha = vha->hw;
2591
2592        /* Suspend HBA. */
2593        scsi_block_requests(vha->host);
2594        set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2595
2596        /* Go with write. */
2597        rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2598            length >> 2);
2599
2600        clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2601        scsi_unblock_requests(vha->host);
2602
2603        return rval;
2604}
2605
2606uint8_t *
2607qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2608    uint32_t offset, uint32_t length)
2609{
2610        int rval;
2611        dma_addr_t optrom_dma;
2612        void *optrom;
2613        uint8_t *pbuf;
2614        uint32_t faddr, left, burst;
2615        struct qla_hw_data *ha = vha->hw;
2616
2617        if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
2618            IS_QLA27XX(ha))
2619                goto try_fast;
2620        if (offset & 0xfff)
2621                goto slow_read;
2622        if (length < OPTROM_BURST_SIZE)
2623                goto slow_read;
2624
2625try_fast:
2626        optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2627            &optrom_dma, GFP_KERNEL);
2628        if (!optrom) {
2629                ql_log(ql_log_warn, vha, 0x00cc,
2630                    "Unable to allocate memory for optrom burst read (%x KB).\n",
2631                    OPTROM_BURST_SIZE / 1024);
2632                goto slow_read;
2633        }
2634
2635        pbuf = buf;
2636        faddr = offset >> 2;
2637        left = length >> 2;
2638        burst = OPTROM_BURST_DWORDS;
2639        while (left != 0) {
2640                if (burst > left)
2641                        burst = left;
2642
2643                rval = qla2x00_dump_ram(vha, optrom_dma,
2644                    flash_data_addr(ha, faddr), burst);
2645                if (rval) {
2646                        ql_log(ql_log_warn, vha, 0x00f5,
2647                            "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2648                            rval, flash_data_addr(ha, faddr),
2649                            (unsigned long long)optrom_dma);
2650                        ql_log(ql_log_warn, vha, 0x00f6,
2651                            "Reverting to slow-read.\n");
2652
2653                        dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2654                            optrom, optrom_dma);
2655                        goto slow_read;
2656                }
2657
2658                memcpy(pbuf, optrom, burst * 4);
2659
2660                left -= burst;
2661                faddr += burst;
2662                pbuf += burst * 4;
2663        }
2664
2665        dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2666            optrom_dma);
2667
2668        return buf;
2669
2670slow_read:
2671    return qla24xx_read_optrom_data(vha, buf, offset, length);
2672}
2673
2674/**
2675 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2676 * @ha: HA context
2677 * @pcids: Pointer to the FCODE PCI data structure
2678 *
2679 * The process of retrieving the FCODE version information is at best
2680 * described as interesting.
2681 *
2682 * Within the first 100h bytes of the image an ASCII string is present
2683 * which contains several pieces of information including the FCODE
2684 * version.  Unfortunately it seems the only reliable way to retrieve
2685 * the version is by scanning for another sentinel within the string,
2686 * the FCODE build date:
2687 *
2688 *      ... 2.00.02 10/17/02 ...
2689 *
2690 * Returns QLA_SUCCESS on successful retrieval of version.
2691 */
2692static void
2693qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2694{
2695        int ret = QLA_FUNCTION_FAILED;
2696        uint32_t istart, iend, iter, vend;
2697        uint8_t do_next, rbyte, *vbyte;
2698
2699        memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2700
2701        /* Skip the PCI data structure. */
2702        istart = pcids +
2703            ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2704                qla2x00_read_flash_byte(ha, pcids + 0x0A));
2705        iend = istart + 0x100;
2706        do {
2707                /* Scan for the sentinel date string...eeewww. */
2708                do_next = 0;
2709                iter = istart;
2710                while ((iter < iend) && !do_next) {
2711                        iter++;
2712                        if (qla2x00_read_flash_byte(ha, iter) == '/') {
2713                                if (qla2x00_read_flash_byte(ha, iter + 2) ==
2714                                    '/')
2715                                        do_next++;
2716                                else if (qla2x00_read_flash_byte(ha,
2717                                    iter + 3) == '/')
2718                                        do_next++;
2719                        }
2720                }
2721                if (!do_next)
2722                        break;
2723
2724                /* Backtrack to previous ' ' (space). */
2725                do_next = 0;
2726                while ((iter > istart) && !do_next) {
2727                        iter--;
2728                        if (qla2x00_read_flash_byte(ha, iter) == ' ')
2729                                do_next++;
2730                }
2731                if (!do_next)
2732                        break;
2733
2734                /*
2735                 * Mark end of version tag, and find previous ' ' (space) or
2736                 * string length (recent FCODE images -- major hack ahead!!!).
2737                 */
2738                vend = iter - 1;
2739                do_next = 0;
2740                while ((iter > istart) && !do_next) {
2741                        iter--;
2742                        rbyte = qla2x00_read_flash_byte(ha, iter);
2743                        if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2744                                do_next++;
2745                }
2746                if (!do_next)
2747                        break;
2748
2749                /* Mark beginning of version tag, and copy data. */
2750                iter++;
2751                if ((vend - iter) &&
2752                    ((vend - iter) < sizeof(ha->fcode_revision))) {
2753                        vbyte = ha->fcode_revision;
2754                        while (iter <= vend) {
2755                                *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2756                                iter++;
2757                        }
2758                        ret = QLA_SUCCESS;
2759                }
2760        } while (0);
2761
2762        if (ret != QLA_SUCCESS)
2763                memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2764}
2765
2766int
2767qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2768{
2769        int ret = QLA_SUCCESS;
2770        uint8_t code_type, last_image;
2771        uint32_t pcihdr, pcids;
2772        uint8_t *dbyte;
2773        uint16_t *dcode;
2774        struct qla_hw_data *ha = vha->hw;
2775
2776        if (!ha->pio_address || !mbuf)
2777                return QLA_FUNCTION_FAILED;
2778
2779        memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2780        memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2781        memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2782        memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2783
2784        qla2x00_flash_enable(ha);
2785
2786        /* Begin with first PCI expansion ROM header. */
2787        pcihdr = 0;
2788        last_image = 1;
2789        do {
2790                /* Verify PCI expansion ROM header. */
2791                if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2792                    qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2793                        /* No signature */
2794                        ql_log(ql_log_fatal, vha, 0x0050,
2795                            "No matching ROM signature.\n");
2796                        ret = QLA_FUNCTION_FAILED;
2797                        break;
2798                }
2799
2800                /* Locate PCI data structure. */
2801                pcids = pcihdr +
2802                    ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2803                        qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2804
2805                /* Validate signature of PCI data structure. */
2806                if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2807                    qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2808                    qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2809                    qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2810                        /* Incorrect header. */
2811                        ql_log(ql_log_fatal, vha, 0x0051,
2812                            "PCI data struct not found pcir_adr=%x.\n", pcids);
2813                        ret = QLA_FUNCTION_FAILED;
2814                        break;
2815                }
2816
2817                /* Read version */
2818                code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2819                switch (code_type) {
2820                case ROM_CODE_TYPE_BIOS:
2821                        /* Intel x86, PC-AT compatible. */
2822                        ha->bios_revision[0] =
2823                            qla2x00_read_flash_byte(ha, pcids + 0x12);
2824                        ha->bios_revision[1] =
2825                            qla2x00_read_flash_byte(ha, pcids + 0x13);
2826                        ql_dbg(ql_dbg_init, vha, 0x0052,
2827                            "Read BIOS %d.%d.\n",
2828                            ha->bios_revision[1], ha->bios_revision[0]);
2829                        break;
2830                case ROM_CODE_TYPE_FCODE:
2831                        /* Open Firmware standard for PCI (FCode). */
2832                        /* Eeeewww... */
2833                        qla2x00_get_fcode_version(ha, pcids);
2834                        break;
2835                case ROM_CODE_TYPE_EFI:
2836                        /* Extensible Firmware Interface (EFI). */
2837                        ha->efi_revision[0] =
2838                            qla2x00_read_flash_byte(ha, pcids + 0x12);
2839                        ha->efi_revision[1] =
2840                            qla2x00_read_flash_byte(ha, pcids + 0x13);
2841                        ql_dbg(ql_dbg_init, vha, 0x0053,
2842                            "Read EFI %d.%d.\n",
2843                            ha->efi_revision[1], ha->efi_revision[0]);
2844                        break;
2845                default:
2846                        ql_log(ql_log_warn, vha, 0x0054,
2847                            "Unrecognized code type %x at pcids %x.\n",
2848                            code_type, pcids);
2849                        break;
2850                }
2851
2852                last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2853
2854                /* Locate next PCI expansion ROM. */
2855                pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2856                    qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2857        } while (!last_image);
2858
2859        if (IS_QLA2322(ha)) {
2860                /* Read firmware image information. */
2861                memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2862                dbyte = mbuf;
2863                memset(dbyte, 0, 8);
2864                dcode = (uint16_t *)dbyte;
2865
2866                qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2867                    8);
2868                ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
2869                    "Dumping fw "
2870                    "ver from flash:.\n");
2871                ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2872                    (uint8_t *)dbyte, 8);
2873
2874                if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2875                    dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2876                    (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2877                    dcode[3] == 0)) {
2878                        ql_log(ql_log_warn, vha, 0x0057,
2879                            "Unrecognized fw revision at %x.\n",
2880                            ha->flt_region_fw * 4);
2881                } else {
2882                        /* values are in big endian */
2883                        ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2884                        ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2885                        ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2886                        ql_dbg(ql_dbg_init, vha, 0x0058,
2887                            "FW Version: "
2888                            "%d.%d.%d.\n", ha->fw_revision[0],
2889                            ha->fw_revision[1], ha->fw_revision[2]);
2890                }
2891        }
2892
2893        qla2x00_flash_disable(ha);
2894
2895        return ret;
2896}
2897
2898int
2899qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2900{
2901        int ret = QLA_SUCCESS;
2902        uint32_t pcihdr, pcids;
2903        uint32_t *dcode;
2904        uint8_t *bcode;
2905        uint8_t code_type, last_image;
2906        struct qla_hw_data *ha = vha->hw;
2907
2908        if (!mbuf)
2909                return QLA_FUNCTION_FAILED;
2910
2911        memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2912        memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2913        memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2914        memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2915
2916        dcode = mbuf;
2917
2918        /* Begin with first PCI expansion ROM header. */
2919        pcihdr = ha->flt_region_boot << 2;
2920        last_image = 1;
2921        do {
2922                /* Verify PCI expansion ROM header. */
2923                ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcihdr,
2924                    0x20 * 4);
2925                bcode = mbuf + (pcihdr % 4);
2926                if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2927                        /* No signature */
2928                        ql_log(ql_log_fatal, vha, 0x0154,
2929                            "No matching ROM signature.\n");
2930                        ret = QLA_FUNCTION_FAILED;
2931                        break;
2932                }
2933
2934                /* Locate PCI data structure. */
2935                pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2936
2937                ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcids,
2938                    0x20 * 4);
2939                bcode = mbuf + (pcihdr % 4);
2940
2941                /* Validate signature of PCI data structure. */
2942                if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2943                    bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2944                        /* Incorrect header. */
2945                        ql_log(ql_log_fatal, vha, 0x0155,
2946                            "PCI data struct not found pcir_adr=%x.\n", pcids);
2947                        ret = QLA_FUNCTION_FAILED;
2948                        break;
2949                }
2950
2951                /* Read version */
2952                code_type = bcode[0x14];
2953                switch (code_type) {
2954                case ROM_CODE_TYPE_BIOS:
2955                        /* Intel x86, PC-AT compatible. */
2956                        ha->bios_revision[0] = bcode[0x12];
2957                        ha->bios_revision[1] = bcode[0x13];
2958                        ql_dbg(ql_dbg_init, vha, 0x0156,
2959                            "Read BIOS %d.%d.\n",
2960                            ha->bios_revision[1], ha->bios_revision[0]);
2961                        break;
2962                case ROM_CODE_TYPE_FCODE:
2963                        /* Open Firmware standard for PCI (FCode). */
2964                        ha->fcode_revision[0] = bcode[0x12];
2965                        ha->fcode_revision[1] = bcode[0x13];
2966                        ql_dbg(ql_dbg_init, vha, 0x0157,
2967                            "Read FCODE %d.%d.\n",
2968                            ha->fcode_revision[1], ha->fcode_revision[0]);
2969                        break;
2970                case ROM_CODE_TYPE_EFI:
2971                        /* Extensible Firmware Interface (EFI). */
2972                        ha->efi_revision[0] = bcode[0x12];
2973                        ha->efi_revision[1] = bcode[0x13];
2974                        ql_dbg(ql_dbg_init, vha, 0x0158,
2975                            "Read EFI %d.%d.\n",
2976                            ha->efi_revision[1], ha->efi_revision[0]);
2977                        break;
2978                default:
2979                        ql_log(ql_log_warn, vha, 0x0159,
2980                            "Unrecognized code type %x at pcids %x.\n",
2981                            code_type, pcids);
2982                        break;
2983                }
2984
2985                last_image = bcode[0x15] & BIT_7;
2986
2987                /* Locate next PCI expansion ROM. */
2988                pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2989        } while (!last_image);
2990
2991        /* Read firmware image information. */
2992        memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2993        dcode = mbuf;
2994        ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, ha->flt_region_fw << 2,
2995            0x20);
2996        bcode = mbuf + (pcihdr % 4);
2997
2998        /* Validate signature of PCI data structure. */
2999        if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 &&
3000            bcode[0x2] == 0x40 && bcode[0x3] == 0x40) {
3001                ha->fw_revision[0] = bcode[0x4];
3002                ha->fw_revision[1] = bcode[0x5];
3003                ha->fw_revision[2] = bcode[0x6];
3004                ql_dbg(ql_dbg_init, vha, 0x0153,
3005                    "Firmware revision %d.%d.%d\n",
3006                    ha->fw_revision[0], ha->fw_revision[1],
3007                    ha->fw_revision[2]);
3008        }
3009
3010        return ret;
3011}
3012
3013int
3014qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
3015{
3016        int ret = QLA_SUCCESS;
3017        uint32_t pcihdr, pcids;
3018        uint32_t *dcode;
3019        uint8_t *bcode;
3020        uint8_t code_type, last_image;
3021        int i;
3022        struct qla_hw_data *ha = vha->hw;
3023        uint32_t faddr = 0;
3024
3025        pcihdr = pcids = 0;
3026
3027        if (IS_P3P_TYPE(ha))
3028                return ret;
3029
3030        if (!mbuf)
3031                return QLA_FUNCTION_FAILED;
3032
3033        memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
3034        memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
3035        memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3036        memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3037
3038        dcode = mbuf;
3039        pcihdr = ha->flt_region_boot << 2;
3040        if (IS_QLA27XX(ha) &&
3041            qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
3042                pcihdr = ha->flt_region_boot_sec << 2;
3043
3044        last_image = 1;
3045        do {
3046                /* Verify PCI expansion ROM header. */
3047                qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
3048                bcode = mbuf + (pcihdr % 4);
3049                if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
3050                        /* No signature */
3051                        ql_log(ql_log_fatal, vha, 0x0059,
3052                            "No matching ROM signature.\n");
3053                        ret = QLA_FUNCTION_FAILED;
3054                        break;
3055                }
3056
3057                /* Locate PCI data structure. */
3058                pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
3059
3060                qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
3061                bcode = mbuf + (pcihdr % 4);
3062
3063                /* Validate signature of PCI data structure. */
3064                if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
3065                    bcode[0x2] != 'I' || bcode[0x3] != 'R') {
3066                        /* Incorrect header. */
3067                        ql_log(ql_log_fatal, vha, 0x005a,
3068                            "PCI data struct not found pcir_adr=%x.\n", pcids);
3069                        ret = QLA_FUNCTION_FAILED;
3070                        break;
3071                }
3072
3073                /* Read version */
3074                code_type = bcode[0x14];
3075                switch (code_type) {
3076                case ROM_CODE_TYPE_BIOS:
3077                        /* Intel x86, PC-AT compatible. */
3078                        ha->bios_revision[0] = bcode[0x12];
3079                        ha->bios_revision[1] = bcode[0x13];
3080                        ql_dbg(ql_dbg_init, vha, 0x005b,
3081                            "Read BIOS %d.%d.\n",
3082                            ha->bios_revision[1], ha->bios_revision[0]);
3083                        break;
3084                case ROM_CODE_TYPE_FCODE:
3085                        /* Open Firmware standard for PCI (FCode). */
3086                        ha->fcode_revision[0] = bcode[0x12];
3087                        ha->fcode_revision[1] = bcode[0x13];
3088                        ql_dbg(ql_dbg_init, vha, 0x005c,
3089                            "Read FCODE %d.%d.\n",
3090                            ha->fcode_revision[1], ha->fcode_revision[0]);
3091                        break;
3092                case ROM_CODE_TYPE_EFI:
3093                        /* Extensible Firmware Interface (EFI). */
3094                        ha->efi_revision[0] = bcode[0x12];
3095                        ha->efi_revision[1] = bcode[0x13];
3096                        ql_dbg(ql_dbg_init, vha, 0x005d,
3097                            "Read EFI %d.%d.\n",
3098                            ha->efi_revision[1], ha->efi_revision[0]);
3099                        break;
3100                default:
3101                        ql_log(ql_log_warn, vha, 0x005e,
3102                            "Unrecognized code type %x at pcids %x.\n",
3103                            code_type, pcids);
3104                        break;
3105                }
3106
3107                last_image = bcode[0x15] & BIT_7;
3108
3109                /* Locate next PCI expansion ROM. */
3110                pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
3111        } while (!last_image);
3112
3113        /* Read firmware image information. */
3114        memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3115        dcode = mbuf;
3116        faddr = ha->flt_region_fw;
3117        if (IS_QLA27XX(ha) &&
3118            qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
3119                faddr = ha->flt_region_fw_sec;
3120
3121        qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
3122        for (i = 0; i < 4; i++)
3123                dcode[i] = be32_to_cpu(dcode[i]);
3124
3125        if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
3126            dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
3127            (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
3128            dcode[3] == 0)) {
3129                ql_log(ql_log_warn, vha, 0x005f,
3130                    "Unrecognized fw revision at %x.\n",
3131                    ha->flt_region_fw * 4);
3132        } else {
3133                ha->fw_revision[0] = dcode[0];
3134                ha->fw_revision[1] = dcode[1];
3135                ha->fw_revision[2] = dcode[2];
3136                ha->fw_revision[3] = dcode[3];
3137                ql_dbg(ql_dbg_init, vha, 0x0060,
3138                    "Firmware revision %d.%d.%d (%x).\n",
3139                    ha->fw_revision[0], ha->fw_revision[1],
3140                    ha->fw_revision[2], ha->fw_revision[3]);
3141        }
3142
3143        /* Check for golden firmware and get version if available */
3144        if (!IS_QLA81XX(ha)) {
3145                /* Golden firmware is not present in non 81XX adapters */
3146                return ret;
3147        }
3148
3149        memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
3150        dcode = mbuf;
3151        ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
3152            ha->flt_region_gold_fw << 2, 32);
3153
3154        if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
3155            dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
3156                ql_log(ql_log_warn, vha, 0x0056,
3157                    "Unrecognized golden fw at 0x%x.\n",
3158                    ha->flt_region_gold_fw * 4);
3159                return ret;
3160        }
3161
3162        for (i = 4; i < 8; i++)
3163                ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
3164
3165        return ret;
3166}
3167
3168static int
3169qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
3170{
3171        if (pos >= end || *pos != 0x82)
3172                return 0;
3173
3174        pos += 3 + pos[1];
3175        if (pos >= end || *pos != 0x90)
3176                return 0;
3177
3178        pos += 3 + pos[1];
3179        if (pos >= end || *pos != 0x78)
3180                return 0;
3181
3182        return 1;
3183}
3184
3185int
3186qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
3187{
3188        struct qla_hw_data *ha = vha->hw;
3189        uint8_t *pos = ha->vpd;
3190        uint8_t *end = pos + ha->vpd_size;
3191        int len = 0;
3192
3193        if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
3194                return 0;
3195
3196        while (pos < end && *pos != 0x78) {
3197                len = (*pos == 0x82) ? pos[1] : pos[2];
3198
3199                if (!strncmp(pos, key, strlen(key)))
3200                        break;
3201
3202                if (*pos != 0x90 && *pos != 0x91)
3203                        pos += len;
3204
3205                pos += 3;
3206        }
3207
3208        if (pos < end - len && *pos != 0x78)
3209                return scnprintf(str, size, "%.*s", len, pos + 3);
3210
3211        return 0;
3212}
3213
3214int
3215qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
3216{
3217        int len, max_len;
3218        uint32_t fcp_prio_addr;
3219        struct qla_hw_data *ha = vha->hw;
3220
3221        if (!ha->fcp_prio_cfg) {
3222                ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
3223                if (!ha->fcp_prio_cfg) {
3224                        ql_log(ql_log_warn, vha, 0x00d5,
3225                            "Unable to allocate memory for fcp priority data (%x).\n",
3226                            FCP_PRIO_CFG_SIZE);
3227                        return QLA_FUNCTION_FAILED;
3228                }
3229        }
3230        memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
3231
3232        fcp_prio_addr = ha->flt_region_fcp_prio;
3233
3234        /* first read the fcp priority data header from flash */
3235        ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
3236                        fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3237
3238        if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
3239                goto fail;
3240
3241        /* read remaining FCP CMD config data from flash */
3242        fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3243        len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
3244        max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3245
3246        ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
3247                        fcp_prio_addr << 2, (len < max_len ? len : max_len));
3248
3249        /* revalidate the entire FCP priority config data, including entries */
3250        if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
3251                goto fail;
3252
3253        ha->flags.fcp_prio_enabled = 1;
3254        return QLA_SUCCESS;
3255fail:
3256        vfree(ha->fcp_prio_cfg);
3257        ha->fcp_prio_cfg = NULL;
3258        return QLA_FUNCTION_FAILED;
3259}
3260