LXR linux/drivers/soc/fsl/qe/ucc

   1/*
   2 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
   3 *
   4 * Authors:     Shlomi Gridish <gridish@freescale.com>
   5 *              Li Yang <leoli@freescale.com>
   6 *
   7 * Description:
   8 * QE UCC Slow API Set - UCC Slow specific routines implementations.
   9 *
  10 * This program is free software; you can redistribute  it and/or modify it
  11 * under  the terms of  the GNU General  Public License as published by the
  12 * Free Software Foundation;  either version 2 of the  License, or (at your
  13 * option) any later version.
  14 */
  15#include <linux/kernel.h>
  16#include <linux/errno.h>
  17#include <linux/slab.h>
  18#include <linux/stddef.h>
  19#include <linux/interrupt.h>
  20#include <linux/err.h>
  21#include <linux/export.h>
  22
  23#include <asm/io.h>
  24#include <soc/fsl/qe/immap_qe.h>
  25#include <soc/fsl/qe/qe.h>
  26
  27#include <soc/fsl/qe/ucc.h>
  28#include <soc/fsl/qe/ucc_slow.h>
  29
  30u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
  31{
  32        switch (uccs_num) {
  33        case 0: return QE_CR_SUBBLOCK_UCCSLOW1;
  34        case 1: return QE_CR_SUBBLOCK_UCCSLOW2;
  35        case 2: return QE_CR_SUBBLOCK_UCCSLOW3;
  36        case 3: return QE_CR_SUBBLOCK_UCCSLOW4;
  37        case 4: return QE_CR_SUBBLOCK_UCCSLOW5;
  38        case 5: return QE_CR_SUBBLOCK_UCCSLOW6;
  39        case 6: return QE_CR_SUBBLOCK_UCCSLOW7;
  40        case 7: return QE_CR_SUBBLOCK_UCCSLOW8;
  41        default: return QE_CR_SUBBLOCK_INVALID;
  42        }
  43}
  44EXPORT_SYMBOL(ucc_slow_get_qe_cr_subblock);
  45
  46void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
  47{
  48        struct ucc_slow_info *us_info = uccs->us_info;
  49        u32 id;
  50
  51        id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  52        qe_issue_cmd(QE_GRACEFUL_STOP_TX, id,
  53                         QE_CR_PROTOCOL_UNSPECIFIED, 0);
  54}
  55EXPORT_SYMBOL(ucc_slow_graceful_stop_tx);
  56
  57void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
  58{
  59        struct ucc_slow_info *us_info = uccs->us_info;
  60        u32 id;
  61
  62        id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  63        qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
  64}
  65EXPORT_SYMBOL(ucc_slow_stop_tx);
  66
  67void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
  68{
  69        struct ucc_slow_info *us_info = uccs->us_info;
  70        u32 id;
  71
  72        id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  73        qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
  74}
  75EXPORT_SYMBOL(ucc_slow_restart_tx);
  76
  77void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
  78{
  79        struct ucc_slow *us_regs;
  80        u32 gumr_l;
  81
  82        us_regs = uccs->us_regs;
  83
  84        /* Enable reception and/or transmission on this UCC. */
  85        gumr_l = in_be32(&us_regs->gumr_l);
  86        if (mode & COMM_DIR_TX) {
  87                gumr_l |= UCC_SLOW_GUMR_L_ENT;
  88                uccs->enabled_tx = 1;
  89        }
  90        if (mode & COMM_DIR_RX) {
  91                gumr_l |= UCC_SLOW_GUMR_L_ENR;
  92                uccs->enabled_rx = 1;
  93        }
  94        out_be32(&us_regs->gumr_l, gumr_l);
  95}
  96EXPORT_SYMBOL(ucc_slow_enable);
  97
  98void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
  99{
 100        struct ucc_slow *us_regs;
 101        u32 gumr_l;
 102
 103        us_regs = uccs->us_regs;
 104
 105        /* Disable reception and/or transmission on this UCC. */
 106        gumr_l = in_be32(&us_regs->gumr_l);
 107        if (mode & COMM_DIR_TX) {
 108                gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
 109                uccs->enabled_tx = 0;
 110        }
 111        if (mode & COMM_DIR_RX) {
 112                gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
 113                uccs->enabled_rx = 0;
 114        }
 115        out_be32(&us_regs->gumr_l, gumr_l);
 116}
 117EXPORT_SYMBOL(ucc_slow_disable);
 118
 119/* Initialize the UCC for Slow operations
 120 *
 121 * The caller should initialize the following us_info
 122 */
 123int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
 124{
 125        struct ucc_slow_private *uccs;
 126        u32 i;
 127        struct ucc_slow __iomem *us_regs;
 128        u32 gumr;
 129        struct qe_bd *bd;
 130        u32 id;
 131        u32 command;
 132        int ret = 0;
 133
 134        if (!us_info)
 135                return -EINVAL;
 136
 137        /* check if the UCC port number is in range. */
 138        if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
 139                printk(KERN_ERR "%s: illegal UCC number\n", __func__);
 140                return -EINVAL;
 141        }
 142
 143        /*
 144         * Set mrblr
 145         * Check that 'max_rx_buf_length' is properly aligned (4), unless
 146         * rfw is 1, meaning that QE accepts one byte at a time, unlike normal
 147         * case when QE accepts 32 bits at a time.
 148         */
 149        if ((!us_info->rfw) &&
 150                (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
 151                printk(KERN_ERR "max_rx_buf_length not aligned.\n");
 152                return -EINVAL;
 153        }
 154
 155        uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
 156        if (!uccs) {
 157                printk(KERN_ERR "%s: Cannot allocate private data\n",
 158                        __func__);
 159                return -ENOMEM;
 160        }
 161
 162        /* Fill slow UCC structure */
 163        uccs->us_info = us_info;
 164        /* Set the PHY base address */
 165        uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
 166        if (uccs->us_regs == NULL) {
 167                printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
 168                kfree(uccs);
 169                return -ENOMEM;
 170        }
 171
 172        uccs->saved_uccm = 0;
 173        uccs->p_rx_frame = 0;
 174        us_regs = uccs->us_regs;
 175        uccs->p_ucce = (u16 *) & (us_regs->ucce);
 176        uccs->p_uccm = (u16 *) & (us_regs->uccm);
 177#ifdef STATISTICS
 178        uccs->rx_frames = 0;
 179        uccs->tx_frames = 0;
 180        uccs->rx_discarded = 0;
 181#endif                          /* STATISTICS */
 182
 183        /* Get PRAM base */
 184        uccs->us_pram_offset =
 185                qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
 186        if (IS_ERR_VALUE(uccs->us_pram_offset)) {
 187                printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
 188                ucc_slow_free(uccs);
 189                return -ENOMEM;
 190        }
 191        id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
 192        qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol,
 193                     uccs->us_pram_offset);
 194
 195        uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
 196
 197        /* Set UCC to slow type */
 198        ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
 199        if (ret) {
 200                printk(KERN_ERR "%s: cannot set UCC type", __func__);
 201                ucc_slow_free(uccs);
 202                return ret;
 203        }
 204
 205        out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
 206
 207        INIT_LIST_HEAD(&uccs->confQ);
 208
 209        /* Allocate BDs. */
 210        uccs->rx_base_offset =
 211                qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
 212                                QE_ALIGNMENT_OF_BD);
 213        if (IS_ERR_VALUE(uccs->rx_base_offset)) {
 214                printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
 215                        us_info->rx_bd_ring_len);
 216                uccs->rx_base_offset = 0;
 217                ucc_slow_free(uccs);
 218                return -ENOMEM;
 219        }
 220
 221        uccs->tx_base_offset =
 222                qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
 223                        QE_ALIGNMENT_OF_BD);
 224        if (IS_ERR_VALUE(uccs->tx_base_offset)) {
 225                printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
 226                uccs->tx_base_offset = 0;
 227                ucc_slow_free(uccs);
 228                return -ENOMEM;
 229        }
 230
 231        /* Init Tx bds */
 232        bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
 233        for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
 234                /* clear bd buffer */
 235                out_be32(&bd->buf, 0);
 236                /* set bd status and length */
 237                out_be32((u32 *) bd, 0);
 238                bd++;
 239        }
 240        /* for last BD set Wrap bit */
 241        out_be32(&bd->buf, 0);
 242        out_be32((u32 *) bd, cpu_to_be32(T_W));
 243
 244        /* Init Rx bds */
 245        bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
 246        for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
 247                /* set bd status and length */
 248                out_be32((u32*)bd, 0);
 249                /* clear bd buffer */
 250                out_be32(&bd->buf, 0);
 251                bd++;
 252        }
 253        /* for last BD set Wrap bit */
 254        out_be32((u32*)bd, cpu_to_be32(R_W));
 255        out_be32(&bd->buf, 0);
 256
 257        /* Set GUMR (For more details see the hardware spec.). */
 258        /* gumr_h */
 259        gumr = us_info->tcrc;
 260        if (us_info->cdp)
 261                gumr |= UCC_SLOW_GUMR_H_CDP;
 262        if (us_info->ctsp)
 263                gumr |= UCC_SLOW_GUMR_H_CTSP;
 264        if (us_info->cds)
 265                gumr |= UCC_SLOW_GUMR_H_CDS;
 266        if (us_info->ctss)
 267                gumr |= UCC_SLOW_GUMR_H_CTSS;
 268        if (us_info->tfl)
 269                gumr |= UCC_SLOW_GUMR_H_TFL;
 270        if (us_info->rfw)
 271                gumr |= UCC_SLOW_GUMR_H_RFW;
 272        if (us_info->txsy)
 273                gumr |= UCC_SLOW_GUMR_H_TXSY;
 274        if (us_info->rtsm)
 275                gumr |= UCC_SLOW_GUMR_H_RTSM;
 276        out_be32(&us_regs->gumr_h, gumr);
 277
 278        /* gumr_l */
 279        gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
 280                us_info->diag | us_info->mode;
 281        if (us_info->tci)
 282                gumr |= UCC_SLOW_GUMR_L_TCI;
 283        if (us_info->rinv)
 284                gumr |= UCC_SLOW_GUMR_L_RINV;
 285        if (us_info->tinv)
 286                gumr |= UCC_SLOW_GUMR_L_TINV;
 287        if (us_info->tend)
 288                gumr |= UCC_SLOW_GUMR_L_TEND;
 289        out_be32(&us_regs->gumr_l, gumr);
 290
 291        /* Function code registers */
 292
 293        /* if the data is in cachable memory, the 'global' */
 294        /* in the function code should be set. */
 295        uccs->us_pram->tbmr = UCC_BMR_BO_BE;
 296        uccs->us_pram->rbmr = UCC_BMR_BO_BE;
 297
 298        /* rbase, tbase are offsets from MURAM base */
 299        out_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);
 300        out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
 301
 302        /* Mux clocking */
 303        /* Grant Support */
 304        ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
 305        /* Breakpoint Support */
 306        ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
 307        /* Set Tsa or NMSI mode. */
 308        ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
 309        /* If NMSI (not Tsa), set Tx and Rx clock. */
 310        if (!us_info->tsa) {
 311                /* Rx clock routing */
 312                if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
 313                                        COMM_DIR_RX)) {
 314                        printk(KERN_ERR "%s: illegal value for RX clock\n",
 315                               __func__);
 316                        ucc_slow_free(uccs);
 317                        return -EINVAL;
 318                }
 319                /* Tx clock routing */
 320                if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
 321                                        COMM_DIR_TX)) {
 322                        printk(KERN_ERR "%s: illegal value for TX clock\n",
 323                               __func__);
 324                        ucc_slow_free(uccs);
 325                        return -EINVAL;
 326                }
 327        }
 328
 329        /* Set interrupt mask register at UCC level. */
 330        out_be16(&us_regs->uccm, us_info->uccm_mask);
 331
 332        /* First, clear anything pending at UCC level,
 333         * otherwise, old garbage may come through
 334         * as soon as the dam is opened. */
 335
 336        /* Writing '1' clears */
 337        out_be16(&us_regs->ucce, 0xffff);
 338
 339        /* Issue QE Init command */
 340        if (us_info->init_tx && us_info->init_rx)
 341                command = QE_INIT_TX_RX;
 342        else if (us_info->init_tx)
 343                command = QE_INIT_TX;
 344        else
 345                command = QE_INIT_RX;   /* We know at least one is TRUE */
 346
 347        qe_issue_cmd(command, id, us_info->protocol, 0);
 348
 349        *uccs_ret = uccs;
 350        return 0;
 351}
 352EXPORT_SYMBOL(ucc_slow_init);
 353
 354void ucc_slow_free(struct ucc_slow_private * uccs)
 355{
 356        if (!uccs)
 357                return;
 358
 359        if (uccs->rx_base_offset)
 360                qe_muram_free(uccs->rx_base_offset);
 361
 362        if (uccs->tx_base_offset)
 363                qe_muram_free(uccs->tx_base_offset);
 364
 365        if (uccs->us_pram)
 366                qe_muram_free(uccs->us_pram_offset);
 367
 368        if (uccs->us_regs)
 369                iounmap(uccs->us_regs);
 370
 371        kfree(uccs);
 372}
 373EXPORT_SYMBOL(ucc_slow_free);
 374
 375