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20#define pr_fmt(fmt) "tegra-pmc: " fmt
21
22#include <linux/kernel.h>
23#include <linux/clk.h>
24#include <linux/clk/tegra.h>
25#include <linux/debugfs.h>
26#include <linux/delay.h>
27#include <linux/err.h>
28#include <linux/export.h>
29#include <linux/init.h>
30#include <linux/io.h>
31#include <linux/iopoll.h>
32#include <linux/of.h>
33#include <linux/of_address.h>
34#include <linux/of_platform.h>
35#include <linux/platform_device.h>
36#include <linux/pm_domain.h>
37#include <linux/reboot.h>
38#include <linux/reset.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/spinlock.h>
42
43#include <soc/tegra/common.h>
44#include <soc/tegra/fuse.h>
45#include <soc/tegra/pmc.h>
46
47#define PMC_CNTRL 0x0
48#define PMC_CNTRL_INTR_POLARITY BIT(17)
49#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16)
50#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15)
51#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14)
52#define PMC_CNTRL_SYSCLK_OE BIT(11)
53#define PMC_CNTRL_SYSCLK_POLARITY BIT(10)
54#define PMC_CNTRL_MAIN_RST BIT(4)
55
56#define DPD_SAMPLE 0x020
57#define DPD_SAMPLE_ENABLE BIT(0)
58#define DPD_SAMPLE_DISABLE (0 << 0)
59
60#define PWRGATE_TOGGLE 0x30
61#define PWRGATE_TOGGLE_START BIT(8)
62
63#define REMOVE_CLAMPING 0x34
64
65#define PWRGATE_STATUS 0x38
66
67#define PMC_PWR_DET 0x48
68
69#define PMC_SCRATCH0 0x50
70#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
71#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
72#define PMC_SCRATCH0_MODE_RCM BIT(1)
73#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
74 PMC_SCRATCH0_MODE_BOOTLOADER | \
75 PMC_SCRATCH0_MODE_RCM)
76
77#define PMC_CPUPWRGOOD_TIMER 0xc8
78#define PMC_CPUPWROFF_TIMER 0xcc
79
80#define PMC_PWR_DET_VALUE 0xe4
81
82#define PMC_SCRATCH41 0x140
83
84#define PMC_SENSOR_CTRL 0x1b0
85#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
86#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
87
88#define PMC_RST_STATUS 0x1b4
89#define PMC_RST_STATUS_POR 0
90#define PMC_RST_STATUS_WATCHDOG 1
91#define PMC_RST_STATUS_SENSOR 2
92#define PMC_RST_STATUS_SW_MAIN 3
93#define PMC_RST_STATUS_LP0 4
94#define PMC_RST_STATUS_AOTAG 5
95
96#define IO_DPD_REQ 0x1b8
97#define IO_DPD_REQ_CODE_IDLE (0U << 30)
98#define IO_DPD_REQ_CODE_OFF (1U << 30)
99#define IO_DPD_REQ_CODE_ON (2U << 30)
100#define IO_DPD_REQ_CODE_MASK (3U << 30)
101
102#define IO_DPD_STATUS 0x1bc
103#define IO_DPD2_REQ 0x1c0
104#define IO_DPD2_STATUS 0x1c4
105#define SEL_DPD_TIM 0x1c8
106
107#define PMC_SCRATCH54 0x258
108#define PMC_SCRATCH54_DATA_SHIFT 8
109#define PMC_SCRATCH54_ADDR_SHIFT 0
110
111#define PMC_SCRATCH55 0x25c
112#define PMC_SCRATCH55_RESET_TEGRA BIT(31)
113#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
114#define PMC_SCRATCH55_PINMUX_SHIFT 24
115#define PMC_SCRATCH55_16BITOP BIT(15)
116#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
117#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
118
119#define GPU_RG_CNTRL 0x2d4
120
121struct tegra_powergate {
122 struct generic_pm_domain genpd;
123 struct tegra_pmc *pmc;
124 unsigned int id;
125 struct clk **clks;
126 unsigned int num_clks;
127 struct reset_control **resets;
128 unsigned int num_resets;
129};
130
131struct tegra_io_pad_soc {
132 enum tegra_io_pad id;
133 unsigned int dpd;
134 unsigned int voltage;
135};
136
137struct tegra_pmc_soc {
138 unsigned int num_powergates;
139 const char *const *powergates;
140 unsigned int num_cpu_powergates;
141 const u8 *cpu_powergates;
142
143 bool has_tsense_reset;
144 bool has_gpu_clamps;
145
146 const struct tegra_io_pad_soc *io_pads;
147 unsigned int num_io_pads;
148};
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172
173struct tegra_pmc {
174 struct device *dev;
175 void __iomem *base;
176 struct clk *clk;
177 struct dentry *debugfs;
178
179 const struct tegra_pmc_soc *soc;
180
181 unsigned long rate;
182
183 enum tegra_suspend_mode suspend_mode;
184 u32 cpu_good_time;
185 u32 cpu_off_time;
186 u32 core_osc_time;
187 u32 core_pmu_time;
188 u32 core_off_time;
189 bool corereq_high;
190 bool sysclkreq_high;
191 bool combined_req;
192 bool cpu_pwr_good_en;
193 u32 lp0_vec_phys;
194 u32 lp0_vec_size;
195 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
196
197 struct mutex powergates_lock;
198};
199
200static struct tegra_pmc *pmc = &(struct tegra_pmc) {
201 .base = NULL,
202 .suspend_mode = TEGRA_SUSPEND_NONE,
203};
204
205static inline struct tegra_powergate *
206to_powergate(struct generic_pm_domain *domain)
207{
208 return container_of(domain, struct tegra_powergate, genpd);
209}
210
211static u32 tegra_pmc_readl(unsigned long offset)
212{
213 return readl(pmc->base + offset);
214}
215
216static void tegra_pmc_writel(u32 value, unsigned long offset)
217{
218 writel(value, pmc->base + offset);
219}
220
221static inline bool tegra_powergate_state(int id)
222{
223 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
224 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0;
225 else
226 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0;
227}
228
229static inline bool tegra_powergate_is_valid(int id)
230{
231 return (pmc->soc && pmc->soc->powergates[id]);
232}
233
234static inline bool tegra_powergate_is_available(int id)
235{
236 return test_bit(id, pmc->powergates_available);
237}
238
239static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
240{
241 unsigned int i;
242
243 if (!pmc || !pmc->soc || !name)
244 return -EINVAL;
245
246 for (i = 0; i < pmc->soc->num_powergates; i++) {
247 if (!tegra_powergate_is_valid(i))
248 continue;
249
250 if (!strcmp(name, pmc->soc->powergates[i]))
251 return i;
252 }
253
254 return -ENODEV;
255}
256
257
258
259
260
261
262static int tegra_powergate_set(unsigned int id, bool new_state)
263{
264 bool status;
265 int err;
266
267 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
268 return -EINVAL;
269
270 mutex_lock(&pmc->powergates_lock);
271
272 if (tegra_powergate_state(id) == new_state) {
273 mutex_unlock(&pmc->powergates_lock);
274 return 0;
275 }
276
277 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
278
279 err = readx_poll_timeout(tegra_powergate_state, id, status,
280 status == new_state, 10, 100000);
281
282 mutex_unlock(&pmc->powergates_lock);
283
284 return err;
285}
286
287static int __tegra_powergate_remove_clamping(unsigned int id)
288{
289 u32 mask;
290
291 mutex_lock(&pmc->powergates_lock);
292
293
294
295
296
297 if (id == TEGRA_POWERGATE_3D) {
298 if (pmc->soc->has_gpu_clamps) {
299 tegra_pmc_writel(0, GPU_RG_CNTRL);
300 goto out;
301 }
302 }
303
304
305
306
307
308 if (id == TEGRA_POWERGATE_VDEC)
309 mask = (1 << TEGRA_POWERGATE_PCIE);
310 else if (id == TEGRA_POWERGATE_PCIE)
311 mask = (1 << TEGRA_POWERGATE_VDEC);
312 else
313 mask = (1 << id);
314
315 tegra_pmc_writel(mask, REMOVE_CLAMPING);
316
317out:
318 mutex_unlock(&pmc->powergates_lock);
319
320 return 0;
321}
322
323static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
324{
325 unsigned int i;
326
327 for (i = 0; i < pg->num_clks; i++)
328 clk_disable_unprepare(pg->clks[i]);
329}
330
331static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
332{
333 unsigned int i;
334 int err;
335
336 for (i = 0; i < pg->num_clks; i++) {
337 err = clk_prepare_enable(pg->clks[i]);
338 if (err)
339 goto out;
340 }
341
342 return 0;
343
344out:
345 while (i--)
346 clk_disable_unprepare(pg->clks[i]);
347
348 return err;
349}
350
351static int tegra_powergate_reset_assert(struct tegra_powergate *pg)
352{
353 unsigned int i;
354 int err;
355
356 for (i = 0; i < pg->num_resets; i++) {
357 err = reset_control_assert(pg->resets[i]);
358 if (err)
359 return err;
360 }
361
362 return 0;
363}
364
365static int tegra_powergate_reset_deassert(struct tegra_powergate *pg)
366{
367 unsigned int i;
368 int err;
369
370 for (i = 0; i < pg->num_resets; i++) {
371 err = reset_control_deassert(pg->resets[i]);
372 if (err)
373 return err;
374 }
375
376 return 0;
377}
378
379static int tegra_powergate_power_up(struct tegra_powergate *pg,
380 bool disable_clocks)
381{
382 int err;
383
384 err = tegra_powergate_reset_assert(pg);
385 if (err)
386 return err;
387
388 usleep_range(10, 20);
389
390 err = tegra_powergate_set(pg->id, true);
391 if (err < 0)
392 return err;
393
394 usleep_range(10, 20);
395
396 err = tegra_powergate_enable_clocks(pg);
397 if (err)
398 goto disable_clks;
399
400 usleep_range(10, 20);
401
402 err = __tegra_powergate_remove_clamping(pg->id);
403 if (err)
404 goto disable_clks;
405
406 usleep_range(10, 20);
407
408 err = tegra_powergate_reset_deassert(pg);
409 if (err)
410 goto powergate_off;
411
412 usleep_range(10, 20);
413
414 if (disable_clocks)
415 tegra_powergate_disable_clocks(pg);
416
417 return 0;
418
419disable_clks:
420 tegra_powergate_disable_clocks(pg);
421 usleep_range(10, 20);
422
423powergate_off:
424 tegra_powergate_set(pg->id, false);
425
426 return err;
427}
428
429static int tegra_powergate_power_down(struct tegra_powergate *pg)
430{
431 int err;
432
433 err = tegra_powergate_enable_clocks(pg);
434 if (err)
435 return err;
436
437 usleep_range(10, 20);
438
439 err = tegra_powergate_reset_assert(pg);
440 if (err)
441 goto disable_clks;
442
443 usleep_range(10, 20);
444
445 tegra_powergate_disable_clocks(pg);
446
447 usleep_range(10, 20);
448
449 err = tegra_powergate_set(pg->id, false);
450 if (err)
451 goto assert_resets;
452
453 return 0;
454
455assert_resets:
456 tegra_powergate_enable_clocks(pg);
457 usleep_range(10, 20);
458 tegra_powergate_reset_deassert(pg);
459 usleep_range(10, 20);
460
461disable_clks:
462 tegra_powergate_disable_clocks(pg);
463
464 return err;
465}
466
467static int tegra_genpd_power_on(struct generic_pm_domain *domain)
468{
469 struct tegra_powergate *pg = to_powergate(domain);
470 int err;
471
472 err = tegra_powergate_power_up(pg, true);
473 if (err)
474 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name,
475 err);
476
477 return err;
478}
479
480static int tegra_genpd_power_off(struct generic_pm_domain *domain)
481{
482 struct tegra_powergate *pg = to_powergate(domain);
483 int err;
484
485 err = tegra_powergate_power_down(pg);
486 if (err)
487 pr_err("failed to turn off PM domain %s: %d\n",
488 pg->genpd.name, err);
489
490 return err;
491}
492
493
494
495
496
497int tegra_powergate_power_on(unsigned int id)
498{
499 if (!tegra_powergate_is_available(id))
500 return -EINVAL;
501
502 return tegra_powergate_set(id, true);
503}
504
505
506
507
508
509int tegra_powergate_power_off(unsigned int id)
510{
511 if (!tegra_powergate_is_available(id))
512 return -EINVAL;
513
514 return tegra_powergate_set(id, false);
515}
516EXPORT_SYMBOL(tegra_powergate_power_off);
517
518
519
520
521
522int tegra_powergate_is_powered(unsigned int id)
523{
524 int status;
525
526 if (!tegra_powergate_is_valid(id))
527 return -EINVAL;
528
529 mutex_lock(&pmc->powergates_lock);
530 status = tegra_powergate_state(id);
531 mutex_unlock(&pmc->powergates_lock);
532
533 return status;
534}
535
536
537
538
539
540int tegra_powergate_remove_clamping(unsigned int id)
541{
542 if (!tegra_powergate_is_available(id))
543 return -EINVAL;
544
545 return __tegra_powergate_remove_clamping(id);
546}
547EXPORT_SYMBOL(tegra_powergate_remove_clamping);
548
549
550
551
552
553
554
555
556
557int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
558 struct reset_control *rst)
559{
560 struct tegra_powergate pg;
561 int err;
562
563 if (!tegra_powergate_is_available(id))
564 return -EINVAL;
565
566 pg.id = id;
567 pg.clks = &clk;
568 pg.num_clks = 1;
569 pg.resets = &rst;
570 pg.num_resets = 1;
571
572 err = tegra_powergate_power_up(&pg, false);
573 if (err)
574 pr_err("failed to turn on partition %d: %d\n", id, err);
575
576 return err;
577}
578EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
579
580#ifdef CONFIG_SMP
581
582
583
584
585
586
587
588static int tegra_get_cpu_powergate_id(unsigned int cpuid)
589{
590 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
591 return pmc->soc->cpu_powergates[cpuid];
592
593 return -EINVAL;
594}
595
596
597
598
599
600bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
601{
602 int id;
603
604 id = tegra_get_cpu_powergate_id(cpuid);
605 if (id < 0)
606 return false;
607
608 return tegra_powergate_is_powered(id);
609}
610
611
612
613
614
615int tegra_pmc_cpu_power_on(unsigned int cpuid)
616{
617 int id;
618
619 id = tegra_get_cpu_powergate_id(cpuid);
620 if (id < 0)
621 return id;
622
623 return tegra_powergate_set(id, true);
624}
625
626
627
628
629
630int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
631{
632 int id;
633
634 id = tegra_get_cpu_powergate_id(cpuid);
635 if (id < 0)
636 return id;
637
638 return tegra_powergate_remove_clamping(id);
639}
640#endif
641
642static int tegra_pmc_restart_notify(struct notifier_block *this,
643 unsigned long action, void *data)
644{
645 const char *cmd = data;
646 u32 value;
647
648 value = tegra_pmc_readl(PMC_SCRATCH0);
649 value &= ~PMC_SCRATCH0_MODE_MASK;
650
651 if (cmd) {
652 if (strcmp(cmd, "recovery") == 0)
653 value |= PMC_SCRATCH0_MODE_RECOVERY;
654
655 if (strcmp(cmd, "bootloader") == 0)
656 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
657
658 if (strcmp(cmd, "forced-recovery") == 0)
659 value |= PMC_SCRATCH0_MODE_RCM;
660 }
661
662 tegra_pmc_writel(value, PMC_SCRATCH0);
663
664
665 value = tegra_pmc_readl(PMC_CNTRL);
666 value |= PMC_CNTRL_MAIN_RST;
667 tegra_pmc_writel(value, PMC_CNTRL);
668
669 return NOTIFY_DONE;
670}
671
672static struct notifier_block tegra_pmc_restart_handler = {
673 .notifier_call = tegra_pmc_restart_notify,
674 .priority = 128,
675};
676
677static int powergate_show(struct seq_file *s, void *data)
678{
679 unsigned int i;
680 int status;
681
682 seq_printf(s, " powergate powered\n");
683 seq_printf(s, "------------------\n");
684
685 for (i = 0; i < pmc->soc->num_powergates; i++) {
686 status = tegra_powergate_is_powered(i);
687 if (status < 0)
688 continue;
689
690 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
691 status ? "yes" : "no");
692 }
693
694 return 0;
695}
696
697static int powergate_open(struct inode *inode, struct file *file)
698{
699 return single_open(file, powergate_show, inode->i_private);
700}
701
702static const struct file_operations powergate_fops = {
703 .open = powergate_open,
704 .read = seq_read,
705 .llseek = seq_lseek,
706 .release = single_release,
707};
708
709static int tegra_powergate_debugfs_init(void)
710{
711 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
712 &powergate_fops);
713 if (!pmc->debugfs)
714 return -ENOMEM;
715
716 return 0;
717}
718
719static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
720 struct device_node *np)
721{
722 struct clk *clk;
723 unsigned int i, count;
724 int err;
725
726 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
727 if (count == 0)
728 return -ENODEV;
729
730 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
731 if (!pg->clks)
732 return -ENOMEM;
733
734 for (i = 0; i < count; i++) {
735 pg->clks[i] = of_clk_get(np, i);
736 if (IS_ERR(pg->clks[i])) {
737 err = PTR_ERR(pg->clks[i]);
738 goto err;
739 }
740 }
741
742 pg->num_clks = count;
743
744 return 0;
745
746err:
747 while (i--)
748 clk_put(pg->clks[i]);
749
750 kfree(pg->clks);
751
752 return err;
753}
754
755static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
756 struct device_node *np, bool off)
757{
758 struct reset_control *rst;
759 unsigned int i, count;
760 int err;
761
762 count = of_count_phandle_with_args(np, "resets", "#reset-cells");
763 if (count == 0)
764 return -ENODEV;
765
766 pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL);
767 if (!pg->resets)
768 return -ENOMEM;
769
770 for (i = 0; i < count; i++) {
771 pg->resets[i] = of_reset_control_get_by_index(np, i);
772 if (IS_ERR(pg->resets[i])) {
773 err = PTR_ERR(pg->resets[i]);
774 goto error;
775 }
776
777 if (off)
778 err = reset_control_assert(pg->resets[i]);
779 else
780 err = reset_control_deassert(pg->resets[i]);
781
782 if (err) {
783 reset_control_put(pg->resets[i]);
784 goto error;
785 }
786 }
787
788 pg->num_resets = count;
789
790 return 0;
791
792error:
793 while (i--)
794 reset_control_put(pg->resets[i]);
795
796 kfree(pg->resets);
797
798 return err;
799}
800
801static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
802{
803 struct tegra_powergate *pg;
804 int id, err;
805 bool off;
806
807 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
808 if (!pg)
809 return;
810
811 id = tegra_powergate_lookup(pmc, np->name);
812 if (id < 0) {
813 pr_err("powergate lookup failed for %s: %d\n", np->name, id);
814 goto free_mem;
815 }
816
817
818
819
820
821 clear_bit(id, pmc->powergates_available);
822
823 pg->id = id;
824 pg->genpd.name = np->name;
825 pg->genpd.power_off = tegra_genpd_power_off;
826 pg->genpd.power_on = tegra_genpd_power_on;
827 pg->pmc = pmc;
828
829 off = !tegra_powergate_is_powered(pg->id);
830
831 err = tegra_powergate_of_get_clks(pg, np);
832 if (err < 0) {
833 pr_err("failed to get clocks for %s: %d\n", np->name, err);
834 goto set_available;
835 }
836
837 err = tegra_powergate_of_get_resets(pg, np, off);
838 if (err < 0) {
839 pr_err("failed to get resets for %s: %d\n", np->name, err);
840 goto remove_clks;
841 }
842
843 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
844 if (off)
845 WARN_ON(tegra_powergate_power_up(pg, true));
846
847 goto remove_resets;
848 }
849
850
851
852
853
854
855
856
857
858 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
859 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) {
860 if (off)
861 WARN_ON(tegra_powergate_power_up(pg, true));
862
863 goto remove_resets;
864 }
865
866 err = pm_genpd_init(&pg->genpd, NULL, off);
867 if (err < 0) {
868 pr_err("failed to initialise PM domain %s: %d\n", np->name,
869 err);
870 goto remove_resets;
871 }
872
873 err = of_genpd_add_provider_simple(np, &pg->genpd);
874 if (err < 0) {
875 pr_err("failed to add PM domain provider for %s: %d\n",
876 np->name, err);
877 goto remove_genpd;
878 }
879
880 pr_debug("added PM domain %s\n", pg->genpd.name);
881
882 return;
883
884remove_genpd:
885 pm_genpd_remove(&pg->genpd);
886
887remove_resets:
888 while (pg->num_resets--)
889 reset_control_put(pg->resets[pg->num_resets]);
890
891 kfree(pg->resets);
892
893remove_clks:
894 while (pg->num_clks--)
895 clk_put(pg->clks[pg->num_clks]);
896
897 kfree(pg->clks);
898
899set_available:
900 set_bit(id, pmc->powergates_available);
901
902free_mem:
903 kfree(pg);
904}
905
906static void tegra_powergate_init(struct tegra_pmc *pmc,
907 struct device_node *parent)
908{
909 struct device_node *np, *child;
910 unsigned int i;
911
912
913 for (i = 0; i < pmc->soc->num_powergates; i++)
914 if (pmc->soc->powergates[i])
915 set_bit(i, pmc->powergates_available);
916
917 np = of_get_child_by_name(parent, "powergates");
918 if (!np)
919 return;
920
921 for_each_child_of_node(np, child)
922 tegra_powergate_add(pmc, child);
923
924 of_node_put(np);
925}
926
927static const struct tegra_io_pad_soc *
928tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
929{
930 unsigned int i;
931
932 for (i = 0; i < pmc->soc->num_io_pads; i++)
933 if (pmc->soc->io_pads[i].id == id)
934 return &pmc->soc->io_pads[i];
935
936 return NULL;
937}
938
939static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
940 unsigned long *status, u32 *mask)
941{
942 const struct tegra_io_pad_soc *pad;
943 unsigned long rate, value;
944
945 pad = tegra_io_pad_find(pmc, id);
946 if (!pad) {
947 pr_err("invalid I/O pad ID %u\n", id);
948 return -ENOENT;
949 }
950
951 if (pad->dpd == UINT_MAX)
952 return -ENOTSUPP;
953
954 *mask = BIT(pad->dpd % 32);
955
956 if (pad->dpd < 32) {
957 *status = IO_DPD_STATUS;
958 *request = IO_DPD_REQ;
959 } else {
960 *status = IO_DPD2_STATUS;
961 *request = IO_DPD2_REQ;
962 }
963
964 rate = clk_get_rate(pmc->clk);
965 if (!rate) {
966 pr_err("failed to get clock rate\n");
967 return -ENODEV;
968 }
969
970 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
971
972
973 value = DIV_ROUND_UP(1000000000, rate);
974 value = DIV_ROUND_UP(200, value);
975 tegra_pmc_writel(value, SEL_DPD_TIM);
976
977 return 0;
978}
979
980static int tegra_io_pad_poll(unsigned long offset, u32 mask,
981 u32 val, unsigned long timeout)
982{
983 u32 value;
984
985 timeout = jiffies + msecs_to_jiffies(timeout);
986
987 while (time_after(timeout, jiffies)) {
988 value = tegra_pmc_readl(offset);
989 if ((value & mask) == val)
990 return 0;
991
992 usleep_range(250, 1000);
993 }
994
995 return -ETIMEDOUT;
996}
997
998static void tegra_io_pad_unprepare(void)
999{
1000 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1001}
1002
1003
1004
1005
1006
1007
1008
1009int tegra_io_pad_power_enable(enum tegra_io_pad id)
1010{
1011 unsigned long request, status;
1012 u32 mask;
1013 int err;
1014
1015 mutex_lock(&pmc->powergates_lock);
1016
1017 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1018 if (err < 0) {
1019 pr_err("failed to prepare I/O pad: %d\n", err);
1020 goto unlock;
1021 }
1022
1023 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request);
1024
1025 err = tegra_io_pad_poll(status, mask, 0, 250);
1026 if (err < 0) {
1027 pr_err("failed to enable I/O pad: %d\n", err);
1028 goto unlock;
1029 }
1030
1031 tegra_io_pad_unprepare();
1032
1033unlock:
1034 mutex_unlock(&pmc->powergates_lock);
1035 return err;
1036}
1037EXPORT_SYMBOL(tegra_io_pad_power_enable);
1038
1039
1040
1041
1042
1043
1044
1045int tegra_io_pad_power_disable(enum tegra_io_pad id)
1046{
1047 unsigned long request, status;
1048 u32 mask;
1049 int err;
1050
1051 mutex_lock(&pmc->powergates_lock);
1052
1053 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1054 if (err < 0) {
1055 pr_err("failed to prepare I/O pad: %d\n", err);
1056 goto unlock;
1057 }
1058
1059 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request);
1060
1061 err = tegra_io_pad_poll(status, mask, mask, 250);
1062 if (err < 0) {
1063 pr_err("failed to disable I/O pad: %d\n", err);
1064 goto unlock;
1065 }
1066
1067 tegra_io_pad_unprepare();
1068
1069unlock:
1070 mutex_unlock(&pmc->powergates_lock);
1071 return err;
1072}
1073EXPORT_SYMBOL(tegra_io_pad_power_disable);
1074
1075int tegra_io_pad_set_voltage(enum tegra_io_pad id,
1076 enum tegra_io_pad_voltage voltage)
1077{
1078 const struct tegra_io_pad_soc *pad;
1079 u32 value;
1080
1081 pad = tegra_io_pad_find(pmc, id);
1082 if (!pad)
1083 return -ENOENT;
1084
1085 if (pad->voltage == UINT_MAX)
1086 return -ENOTSUPP;
1087
1088 mutex_lock(&pmc->powergates_lock);
1089
1090
1091 value = tegra_pmc_readl(PMC_PWR_DET);
1092 value |= BIT(pad->voltage);
1093 tegra_pmc_writel(value, PMC_PWR_DET);
1094
1095
1096 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1097
1098 if (voltage == TEGRA_IO_PAD_1800000UV)
1099 value &= ~BIT(pad->voltage);
1100 else
1101 value |= BIT(pad->voltage);
1102
1103 tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
1104
1105 mutex_unlock(&pmc->powergates_lock);
1106
1107 usleep_range(100, 250);
1108
1109 return 0;
1110}
1111EXPORT_SYMBOL(tegra_io_pad_set_voltage);
1112
1113int tegra_io_pad_get_voltage(enum tegra_io_pad id)
1114{
1115 const struct tegra_io_pad_soc *pad;
1116 u32 value;
1117
1118 pad = tegra_io_pad_find(pmc, id);
1119 if (!pad)
1120 return -ENOENT;
1121
1122 if (pad->voltage == UINT_MAX)
1123 return -ENOTSUPP;
1124
1125 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1126
1127 if ((value & BIT(pad->voltage)) == 0)
1128 return TEGRA_IO_PAD_1800000UV;
1129
1130 return TEGRA_IO_PAD_3300000UV;
1131}
1132EXPORT_SYMBOL(tegra_io_pad_get_voltage);
1133
1134
1135
1136
1137
1138
1139
1140int tegra_io_rail_power_on(unsigned int id)
1141{
1142 return tegra_io_pad_power_enable(id);
1143}
1144EXPORT_SYMBOL(tegra_io_rail_power_on);
1145
1146
1147
1148
1149
1150
1151
1152int tegra_io_rail_power_off(unsigned int id)
1153{
1154 return tegra_io_pad_power_disable(id);
1155}
1156EXPORT_SYMBOL(tegra_io_rail_power_off);
1157
1158#ifdef CONFIG_PM_SLEEP
1159enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1160{
1161 return pmc->suspend_mode;
1162}
1163
1164void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1165{
1166 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1167 return;
1168
1169 pmc->suspend_mode = mode;
1170}
1171
1172void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1173{
1174 unsigned long long rate = 0;
1175 u32 value;
1176
1177 switch (mode) {
1178 case TEGRA_SUSPEND_LP1:
1179 rate = 32768;
1180 break;
1181
1182 case TEGRA_SUSPEND_LP2:
1183 rate = clk_get_rate(pmc->clk);
1184 break;
1185
1186 default:
1187 break;
1188 }
1189
1190 if (WARN_ON_ONCE(rate == 0))
1191 rate = 100000000;
1192
1193 if (rate != pmc->rate) {
1194 u64 ticks;
1195
1196 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1197 do_div(ticks, USEC_PER_SEC);
1198 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
1199
1200 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1201 do_div(ticks, USEC_PER_SEC);
1202 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
1203
1204 wmb();
1205
1206 pmc->rate = rate;
1207 }
1208
1209 value = tegra_pmc_readl(PMC_CNTRL);
1210 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1211 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1212 tegra_pmc_writel(value, PMC_CNTRL);
1213}
1214#endif
1215
1216static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1217{
1218 u32 value, values[2];
1219
1220 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1221 } else {
1222 switch (value) {
1223 case 0:
1224 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1225 break;
1226
1227 case 1:
1228 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1229 break;
1230
1231 case 2:
1232 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1233 break;
1234
1235 default:
1236 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1237 break;
1238 }
1239 }
1240
1241 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1242
1243 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1244 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1245
1246 pmc->cpu_good_time = value;
1247
1248 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1249 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1250
1251 pmc->cpu_off_time = value;
1252
1253 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1254 values, ARRAY_SIZE(values)))
1255 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1256
1257 pmc->core_osc_time = values[0];
1258 pmc->core_pmu_time = values[1];
1259
1260 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1261 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1262
1263 pmc->core_off_time = value;
1264
1265 pmc->corereq_high = of_property_read_bool(np,
1266 "nvidia,core-power-req-active-high");
1267
1268 pmc->sysclkreq_high = of_property_read_bool(np,
1269 "nvidia,sys-clock-req-active-high");
1270
1271 pmc->combined_req = of_property_read_bool(np,
1272 "nvidia,combined-power-req");
1273
1274 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1275 "nvidia,cpu-pwr-good-en");
1276
1277 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1278 ARRAY_SIZE(values)))
1279 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1280 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1281
1282 pmc->lp0_vec_phys = values[0];
1283 pmc->lp0_vec_size = values[1];
1284
1285 return 0;
1286}
1287
1288static void tegra_pmc_init(struct tegra_pmc *pmc)
1289{
1290 u32 value;
1291
1292
1293 value = tegra_pmc_readl(PMC_CNTRL);
1294 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1295 tegra_pmc_writel(value, PMC_CNTRL);
1296
1297 value = tegra_pmc_readl(PMC_CNTRL);
1298
1299 if (pmc->sysclkreq_high)
1300 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
1301 else
1302 value |= PMC_CNTRL_SYSCLK_POLARITY;
1303
1304
1305 tegra_pmc_writel(value, PMC_CNTRL);
1306
1307
1308 value = tegra_pmc_readl(PMC_CNTRL);
1309 value |= PMC_CNTRL_SYSCLK_OE;
1310 tegra_pmc_writel(value, PMC_CNTRL);
1311}
1312
1313static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1314{
1315 static const char disabled[] = "emergency thermal reset disabled";
1316 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1317 struct device *dev = pmc->dev;
1318 struct device_node *np;
1319 u32 value, checksum;
1320
1321 if (!pmc->soc->has_tsense_reset)
1322 return;
1323
1324 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip");
1325 if (!np) {
1326 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1327 return;
1328 }
1329
1330 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1331 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1332 goto out;
1333 }
1334
1335 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1336 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1337 goto out;
1338 }
1339
1340 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1341 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1342 goto out;
1343 }
1344
1345 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1346 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1347 goto out;
1348 }
1349
1350 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1351 pinmux = 0;
1352
1353 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1354 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1355 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1356
1357 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1358 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1359 tegra_pmc_writel(value, PMC_SCRATCH54);
1360
1361 value = PMC_SCRATCH55_RESET_TEGRA;
1362 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1363 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1364 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1365
1366
1367
1368
1369
1370 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1371 + ((value >> 24) & 0xff);
1372 checksum &= 0xff;
1373 checksum = 0x100 - checksum;
1374
1375 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1376
1377 tegra_pmc_writel(value, PMC_SCRATCH55);
1378
1379 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1380 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1381 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1382
1383 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1384
1385out:
1386 of_node_put(np);
1387}
1388
1389static int tegra_pmc_probe(struct platform_device *pdev)
1390{
1391 void __iomem *base;
1392 struct resource *res;
1393 int err;
1394
1395
1396
1397
1398
1399
1400 if (WARN_ON(!pmc->base || !pmc->soc))
1401 return -ENODEV;
1402
1403 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
1404 if (err < 0)
1405 return err;
1406
1407
1408 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1409 base = devm_ioremap_resource(&pdev->dev, res);
1410 if (IS_ERR(base))
1411 return PTR_ERR(base);
1412
1413 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
1414 if (IS_ERR(pmc->clk)) {
1415 err = PTR_ERR(pmc->clk);
1416 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
1417 return err;
1418 }
1419
1420 pmc->dev = &pdev->dev;
1421
1422 tegra_pmc_init(pmc);
1423
1424 tegra_pmc_init_tsense_reset(pmc);
1425
1426 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1427 err = tegra_powergate_debugfs_init();
1428 if (err < 0)
1429 return err;
1430 }
1431
1432 err = register_restart_handler(&tegra_pmc_restart_handler);
1433 if (err) {
1434 debugfs_remove(pmc->debugfs);
1435 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
1436 err);
1437 return err;
1438 }
1439
1440 mutex_lock(&pmc->powergates_lock);
1441 iounmap(pmc->base);
1442 pmc->base = base;
1443 mutex_unlock(&pmc->powergates_lock);
1444
1445 return 0;
1446}
1447
1448#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1449static int tegra_pmc_suspend(struct device *dev)
1450{
1451 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
1452
1453 return 0;
1454}
1455
1456static int tegra_pmc_resume(struct device *dev)
1457{
1458 tegra_pmc_writel(0x0, PMC_SCRATCH41);
1459
1460 return 0;
1461}
1462
1463static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
1464
1465#endif
1466
1467static const char * const tegra20_powergates[] = {
1468 [TEGRA_POWERGATE_CPU] = "cpu",
1469 [TEGRA_POWERGATE_3D] = "3d",
1470 [TEGRA_POWERGATE_VENC] = "venc",
1471 [TEGRA_POWERGATE_VDEC] = "vdec",
1472 [TEGRA_POWERGATE_PCIE] = "pcie",
1473 [TEGRA_POWERGATE_L2] = "l2",
1474 [TEGRA_POWERGATE_MPE] = "mpe",
1475};
1476
1477static const struct tegra_pmc_soc tegra20_pmc_soc = {
1478 .num_powergates = ARRAY_SIZE(tegra20_powergates),
1479 .powergates = tegra20_powergates,
1480 .num_cpu_powergates = 0,
1481 .cpu_powergates = NULL,
1482 .has_tsense_reset = false,
1483 .has_gpu_clamps = false,
1484};
1485
1486static const char * const tegra30_powergates[] = {
1487 [TEGRA_POWERGATE_CPU] = "cpu0",
1488 [TEGRA_POWERGATE_3D] = "3d0",
1489 [TEGRA_POWERGATE_VENC] = "venc",
1490 [TEGRA_POWERGATE_VDEC] = "vdec",
1491 [TEGRA_POWERGATE_PCIE] = "pcie",
1492 [TEGRA_POWERGATE_L2] = "l2",
1493 [TEGRA_POWERGATE_MPE] = "mpe",
1494 [TEGRA_POWERGATE_HEG] = "heg",
1495 [TEGRA_POWERGATE_SATA] = "sata",
1496 [TEGRA_POWERGATE_CPU1] = "cpu1",
1497 [TEGRA_POWERGATE_CPU2] = "cpu2",
1498 [TEGRA_POWERGATE_CPU3] = "cpu3",
1499 [TEGRA_POWERGATE_CELP] = "celp",
1500 [TEGRA_POWERGATE_3D1] = "3d1",
1501};
1502
1503static const u8 tegra30_cpu_powergates[] = {
1504 TEGRA_POWERGATE_CPU,
1505 TEGRA_POWERGATE_CPU1,
1506 TEGRA_POWERGATE_CPU2,
1507 TEGRA_POWERGATE_CPU3,
1508};
1509
1510static const struct tegra_pmc_soc tegra30_pmc_soc = {
1511 .num_powergates = ARRAY_SIZE(tegra30_powergates),
1512 .powergates = tegra30_powergates,
1513 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
1514 .cpu_powergates = tegra30_cpu_powergates,
1515 .has_tsense_reset = true,
1516 .has_gpu_clamps = false,
1517};
1518
1519static const char * const tegra114_powergates[] = {
1520 [TEGRA_POWERGATE_CPU] = "crail",
1521 [TEGRA_POWERGATE_3D] = "3d",
1522 [TEGRA_POWERGATE_VENC] = "venc",
1523 [TEGRA_POWERGATE_VDEC] = "vdec",
1524 [TEGRA_POWERGATE_MPE] = "mpe",
1525 [TEGRA_POWERGATE_HEG] = "heg",
1526 [TEGRA_POWERGATE_CPU1] = "cpu1",
1527 [TEGRA_POWERGATE_CPU2] = "cpu2",
1528 [TEGRA_POWERGATE_CPU3] = "cpu3",
1529 [TEGRA_POWERGATE_CELP] = "celp",
1530 [TEGRA_POWERGATE_CPU0] = "cpu0",
1531 [TEGRA_POWERGATE_C0NC] = "c0nc",
1532 [TEGRA_POWERGATE_C1NC] = "c1nc",
1533 [TEGRA_POWERGATE_DIS] = "dis",
1534 [TEGRA_POWERGATE_DISB] = "disb",
1535 [TEGRA_POWERGATE_XUSBA] = "xusba",
1536 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1537 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1538};
1539
1540static const u8 tegra114_cpu_powergates[] = {
1541 TEGRA_POWERGATE_CPU0,
1542 TEGRA_POWERGATE_CPU1,
1543 TEGRA_POWERGATE_CPU2,
1544 TEGRA_POWERGATE_CPU3,
1545};
1546
1547static const struct tegra_pmc_soc tegra114_pmc_soc = {
1548 .num_powergates = ARRAY_SIZE(tegra114_powergates),
1549 .powergates = tegra114_powergates,
1550 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
1551 .cpu_powergates = tegra114_cpu_powergates,
1552 .has_tsense_reset = true,
1553 .has_gpu_clamps = false,
1554};
1555
1556static const char * const tegra124_powergates[] = {
1557 [TEGRA_POWERGATE_CPU] = "crail",
1558 [TEGRA_POWERGATE_3D] = "3d",
1559 [TEGRA_POWERGATE_VENC] = "venc",
1560 [TEGRA_POWERGATE_PCIE] = "pcie",
1561 [TEGRA_POWERGATE_VDEC] = "vdec",
1562 [TEGRA_POWERGATE_MPE] = "mpe",
1563 [TEGRA_POWERGATE_HEG] = "heg",
1564 [TEGRA_POWERGATE_SATA] = "sata",
1565 [TEGRA_POWERGATE_CPU1] = "cpu1",
1566 [TEGRA_POWERGATE_CPU2] = "cpu2",
1567 [TEGRA_POWERGATE_CPU3] = "cpu3",
1568 [TEGRA_POWERGATE_CELP] = "celp",
1569 [TEGRA_POWERGATE_CPU0] = "cpu0",
1570 [TEGRA_POWERGATE_C0NC] = "c0nc",
1571 [TEGRA_POWERGATE_C1NC] = "c1nc",
1572 [TEGRA_POWERGATE_SOR] = "sor",
1573 [TEGRA_POWERGATE_DIS] = "dis",
1574 [TEGRA_POWERGATE_DISB] = "disb",
1575 [TEGRA_POWERGATE_XUSBA] = "xusba",
1576 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1577 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1578 [TEGRA_POWERGATE_VIC] = "vic",
1579 [TEGRA_POWERGATE_IRAM] = "iram",
1580};
1581
1582static const u8 tegra124_cpu_powergates[] = {
1583 TEGRA_POWERGATE_CPU0,
1584 TEGRA_POWERGATE_CPU1,
1585 TEGRA_POWERGATE_CPU2,
1586 TEGRA_POWERGATE_CPU3,
1587};
1588
1589static const struct tegra_io_pad_soc tegra124_io_pads[] = {
1590 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1591 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
1592 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
1593 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
1594 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1595 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1596 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1597 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1598 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1599 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1600 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1601 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1602 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1603 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
1604 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1605 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1606 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
1607 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1608 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1609 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1610 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1611 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
1612 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
1613 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
1614 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
1615 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1616 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1617 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1618 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1619 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1620};
1621
1622static const struct tegra_pmc_soc tegra124_pmc_soc = {
1623 .num_powergates = ARRAY_SIZE(tegra124_powergates),
1624 .powergates = tegra124_powergates,
1625 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
1626 .cpu_powergates = tegra124_cpu_powergates,
1627 .has_tsense_reset = true,
1628 .has_gpu_clamps = true,
1629 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
1630 .io_pads = tegra124_io_pads,
1631};
1632
1633static const char * const tegra210_powergates[] = {
1634 [TEGRA_POWERGATE_CPU] = "crail",
1635 [TEGRA_POWERGATE_3D] = "3d",
1636 [TEGRA_POWERGATE_VENC] = "venc",
1637 [TEGRA_POWERGATE_PCIE] = "pcie",
1638 [TEGRA_POWERGATE_MPE] = "mpe",
1639 [TEGRA_POWERGATE_SATA] = "sata",
1640 [TEGRA_POWERGATE_CPU1] = "cpu1",
1641 [TEGRA_POWERGATE_CPU2] = "cpu2",
1642 [TEGRA_POWERGATE_CPU3] = "cpu3",
1643 [TEGRA_POWERGATE_CPU0] = "cpu0",
1644 [TEGRA_POWERGATE_C0NC] = "c0nc",
1645 [TEGRA_POWERGATE_SOR] = "sor",
1646 [TEGRA_POWERGATE_DIS] = "dis",
1647 [TEGRA_POWERGATE_DISB] = "disb",
1648 [TEGRA_POWERGATE_XUSBA] = "xusba",
1649 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1650 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1651 [TEGRA_POWERGATE_VIC] = "vic",
1652 [TEGRA_POWERGATE_IRAM] = "iram",
1653 [TEGRA_POWERGATE_NVDEC] = "nvdec",
1654 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
1655 [TEGRA_POWERGATE_AUD] = "aud",
1656 [TEGRA_POWERGATE_DFD] = "dfd",
1657 [TEGRA_POWERGATE_VE2] = "ve2",
1658};
1659
1660static const u8 tegra210_cpu_powergates[] = {
1661 TEGRA_POWERGATE_CPU0,
1662 TEGRA_POWERGATE_CPU1,
1663 TEGRA_POWERGATE_CPU2,
1664 TEGRA_POWERGATE_CPU3,
1665};
1666
1667static const struct tegra_io_pad_soc tegra210_io_pads[] = {
1668 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
1669 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
1670 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
1671 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1672 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1673 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
1674 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
1675 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1676 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
1677 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
1678 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
1679 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
1680 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
1681 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1682 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1683 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1684 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1685 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
1686 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
1687 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
1688 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1689 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1690 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1691 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1692 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1693 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1694 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1695 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
1696 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
1697 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
1698 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
1699 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
1700 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
1701 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1702 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1703 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1704 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
1705 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1706};
1707
1708static const struct tegra_pmc_soc tegra210_pmc_soc = {
1709 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1710 .powergates = tegra210_powergates,
1711 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1712 .cpu_powergates = tegra210_cpu_powergates,
1713 .has_tsense_reset = true,
1714 .has_gpu_clamps = true,
1715 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
1716 .io_pads = tegra210_io_pads,
1717};
1718
1719static const struct of_device_id tegra_pmc_match[] = {
1720 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1721 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1722 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1723 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1724 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
1725 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
1726 { }
1727};
1728
1729static struct platform_driver tegra_pmc_driver = {
1730 .driver = {
1731 .name = "tegra-pmc",
1732 .suppress_bind_attrs = true,
1733 .of_match_table = tegra_pmc_match,
1734#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1735 .pm = &tegra_pmc_pm_ops,
1736#endif
1737 },
1738 .probe = tegra_pmc_probe,
1739};
1740builtin_platform_driver(tegra_pmc_driver);
1741
1742
1743
1744
1745
1746static int __init tegra_pmc_early_init(void)
1747{
1748 const struct of_device_id *match;
1749 struct device_node *np;
1750 struct resource regs;
1751 bool invert;
1752 u32 value;
1753
1754 mutex_init(&pmc->powergates_lock);
1755
1756 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
1757 if (!np) {
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
1769 pr_warn("DT node not found, powergating disabled\n");
1770
1771 regs.start = 0x7000e400;
1772 regs.end = 0x7000e7ff;
1773 regs.flags = IORESOURCE_MEM;
1774
1775 pr_warn("Using memory region %pR\n", ®s);
1776 } else {
1777
1778
1779
1780
1781 return 0;
1782 }
1783 } else {
1784
1785
1786
1787
1788 if (of_address_to_resource(np, 0, ®s) < 0) {
1789 pr_err("failed to get PMC registers\n");
1790 of_node_put(np);
1791 return -ENXIO;
1792 }
1793 }
1794
1795 pmc->base = ioremap_nocache(regs.start, resource_size(®s));
1796 if (!pmc->base) {
1797 pr_err("failed to map PMC registers\n");
1798 of_node_put(np);
1799 return -ENXIO;
1800 }
1801
1802 if (np) {
1803 pmc->soc = match->data;
1804
1805 tegra_powergate_init(pmc, np);
1806
1807
1808
1809
1810
1811 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
1812
1813 value = tegra_pmc_readl(PMC_CNTRL);
1814
1815 if (invert)
1816 value |= PMC_CNTRL_INTR_POLARITY;
1817 else
1818 value &= ~PMC_CNTRL_INTR_POLARITY;
1819
1820 tegra_pmc_writel(value, PMC_CNTRL);
1821
1822 of_node_put(np);
1823 }
1824
1825 return 0;
1826}
1827early_initcall(tegra_pmc_early_init);
1828
