1
2
3
4
5
6
7
8
9#include <linux/interrupt.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/sysfs.h>
14#include <linux/i2c.h>
15#include <linux/module.h>
16#include <linux/delay.h>
17
18#include <linux/iio/iio.h>
19#include <linux/iio/sysfs.h>
20
21
22
23
24
25
26
27
28#define AD7152_REG_STATUS 0
29#define AD7152_REG_CH1_DATA_HIGH 1
30#define AD7152_REG_CH2_DATA_HIGH 3
31#define AD7152_REG_CH1_OFFS_HIGH 5
32#define AD7152_REG_CH2_OFFS_HIGH 7
33#define AD7152_REG_CH1_GAIN_HIGH 9
34#define AD7152_REG_CH1_SETUP 11
35#define AD7152_REG_CH2_GAIN_HIGH 12
36#define AD7152_REG_CH2_SETUP 14
37#define AD7152_REG_CFG 15
38#define AD7152_REG_RESEVERD 16
39#define AD7152_REG_CAPDAC_POS 17
40#define AD7152_REG_CAPDAC_NEG 18
41#define AD7152_REG_CFG2 26
42
43
44#define AD7152_STATUS_RDY1 BIT(0)
45#define AD7152_STATUS_RDY2 BIT(1)
46#define AD7152_STATUS_C1C2 BIT(2)
47#define AD7152_STATUS_PWDN BIT(7)
48
49
50#define AD7152_SETUP_CAPDIFF (1 << 5)
51#define AD7152_SETUP_RANGE_2pF (0 << 6)
52#define AD7152_SETUP_RANGE_0_5pF (1 << 6)
53#define AD7152_SETUP_RANGE_1pF (2 << 6)
54#define AD7152_SETUP_RANGE_4pF (3 << 6)
55#define AD7152_SETUP_RANGE(x) ((x) << 6)
56
57
58#define AD7152_CONF_CH2EN (1 << 3)
59#define AD7152_CONF_CH1EN (1 << 4)
60#define AD7152_CONF_MODE_IDLE (0 << 0)
61#define AD7152_CONF_MODE_CONT_CONV (1 << 0)
62#define AD7152_CONF_MODE_SINGLE_CONV (2 << 0)
63#define AD7152_CONF_MODE_OFFS_CAL (5 << 0)
64#define AD7152_CONF_MODE_GAIN_CAL (6 << 0)
65
66
67#define AD7152_CAPDAC_DACEN (1 << 7)
68#define AD7152_CAPDAC_DACP(x) ((x) & 0x1F)
69
70
71#define AD7152_CFG2_OSR(x) (((x) & 0x3) << 4)
72
73enum {
74 AD7152_DATA,
75 AD7152_OFFS,
76 AD7152_GAIN,
77 AD7152_SETUP
78};
79
80
81
82
83
84struct ad7152_chip_info {
85 struct i2c_client *client;
86
87
88
89
90 u8 filter_rate_setup;
91 u8 setup[2];
92 struct mutex state_lock;
93};
94
95static inline ssize_t ad7152_start_calib(struct device *dev,
96 struct device_attribute *attr,
97 const char *buf,
98 size_t len,
99 u8 regval)
100{
101 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
102 struct ad7152_chip_info *chip = iio_priv(indio_dev);
103 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
104 bool doit;
105 int ret, timeout = 10;
106
107 ret = strtobool(buf, &doit);
108 if (ret < 0)
109 return ret;
110
111 if (!doit)
112 return 0;
113
114 if (this_attr->address == 0)
115 regval |= AD7152_CONF_CH1EN;
116 else
117 regval |= AD7152_CONF_CH2EN;
118
119 mutex_lock(&chip->state_lock);
120 ret = i2c_smbus_write_byte_data(chip->client, AD7152_REG_CFG, regval);
121 if (ret < 0) {
122 mutex_unlock(&chip->state_lock);
123 return ret;
124 }
125
126 do {
127 mdelay(20);
128 ret = i2c_smbus_read_byte_data(chip->client, AD7152_REG_CFG);
129 if (ret < 0) {
130 mutex_unlock(&chip->state_lock);
131 return ret;
132 }
133 } while ((ret == regval) && timeout--);
134
135 mutex_unlock(&chip->state_lock);
136 return len;
137}
138
139static ssize_t ad7152_start_offset_calib(struct device *dev,
140 struct device_attribute *attr,
141 const char *buf,
142 size_t len)
143{
144 return ad7152_start_calib(dev, attr, buf, len,
145 AD7152_CONF_MODE_OFFS_CAL);
146}
147
148static ssize_t ad7152_start_gain_calib(struct device *dev,
149 struct device_attribute *attr,
150 const char *buf,
151 size_t len)
152{
153 return ad7152_start_calib(dev, attr, buf, len,
154 AD7152_CONF_MODE_GAIN_CAL);
155}
156
157static IIO_DEVICE_ATTR(in_capacitance0_calibbias_calibration,
158 0200, NULL, ad7152_start_offset_calib, 0);
159static IIO_DEVICE_ATTR(in_capacitance1_calibbias_calibration,
160 0200, NULL, ad7152_start_offset_calib, 1);
161static IIO_DEVICE_ATTR(in_capacitance0_calibscale_calibration,
162 0200, NULL, ad7152_start_gain_calib, 0);
163static IIO_DEVICE_ATTR(in_capacitance1_calibscale_calibration,
164 0200, NULL, ad7152_start_gain_calib, 1);
165
166
167static const unsigned char ad7152_filter_rate_table[][2] = {
168 {200, 5 + 1}, {50, 20 + 1}, {20, 50 + 1}, {17, 60 + 1},
169};
170
171static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("200 50 20 17");
172
173static IIO_CONST_ATTR(in_capacitance_scale_available,
174 "0.000061050 0.000030525 0.000015263 0.000007631");
175
176static struct attribute *ad7152_attributes[] = {
177 &iio_dev_attr_in_capacitance0_calibbias_calibration.dev_attr.attr,
178 &iio_dev_attr_in_capacitance1_calibbias_calibration.dev_attr.attr,
179 &iio_dev_attr_in_capacitance0_calibscale_calibration.dev_attr.attr,
180 &iio_dev_attr_in_capacitance1_calibscale_calibration.dev_attr.attr,
181 &iio_const_attr_in_capacitance_scale_available.dev_attr.attr,
182 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
183 NULL,
184};
185
186static const struct attribute_group ad7152_attribute_group = {
187 .attrs = ad7152_attributes,
188};
189
190static const u8 ad7152_addresses[][4] = {
191 { AD7152_REG_CH1_DATA_HIGH, AD7152_REG_CH1_OFFS_HIGH,
192 AD7152_REG_CH1_GAIN_HIGH, AD7152_REG_CH1_SETUP },
193 { AD7152_REG_CH2_DATA_HIGH, AD7152_REG_CH2_OFFS_HIGH,
194 AD7152_REG_CH2_GAIN_HIGH, AD7152_REG_CH2_SETUP },
195};
196
197
198static const int ad7152_scale_table[] = {
199 30525, 7631, 15263, 61050
200};
201
202
203
204
205
206
207static int ad7152_read_raw_samp_freq(struct device *dev, int *val)
208{
209 struct ad7152_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
210
211 *val = ad7152_filter_rate_table[chip->filter_rate_setup][0];
212
213 return 0;
214}
215
216
217
218
219
220
221static int ad7152_write_raw_samp_freq(struct device *dev, int val)
222{
223 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
224 struct ad7152_chip_info *chip = iio_priv(indio_dev);
225 int ret, i;
226
227 for (i = 0; i < ARRAY_SIZE(ad7152_filter_rate_table); i++)
228 if (val >= ad7152_filter_rate_table[i][0])
229 break;
230
231 if (i >= ARRAY_SIZE(ad7152_filter_rate_table))
232 i = ARRAY_SIZE(ad7152_filter_rate_table) - 1;
233
234 ret = i2c_smbus_write_byte_data(chip->client,
235 AD7152_REG_CFG2, AD7152_CFG2_OSR(i));
236 if (ret < 0)
237 return ret;
238
239 chip->filter_rate_setup = i;
240
241 return ret;
242}
243
244static int ad7152_write_raw(struct iio_dev *indio_dev,
245 struct iio_chan_spec const *chan,
246 int val,
247 int val2,
248 long mask)
249{
250 struct ad7152_chip_info *chip = iio_priv(indio_dev);
251 int ret, i;
252
253 mutex_lock(&chip->state_lock);
254
255 switch (mask) {
256 case IIO_CHAN_INFO_CALIBSCALE:
257 if (val != 1) {
258 ret = -EINVAL;
259 goto out;
260 }
261
262 val = (val2 * 1024) / 15625;
263
264 ret = i2c_smbus_write_word_data(chip->client,
265 ad7152_addresses[chan->channel][AD7152_GAIN],
266 swab16(val));
267 if (ret < 0)
268 goto out;
269
270 ret = 0;
271 break;
272
273 case IIO_CHAN_INFO_CALIBBIAS:
274 if ((val < 0) | (val > 0xFFFF)) {
275 ret = -EINVAL;
276 goto out;
277 }
278 ret = i2c_smbus_write_word_data(chip->client,
279 ad7152_addresses[chan->channel][AD7152_OFFS],
280 swab16(val));
281 if (ret < 0)
282 goto out;
283
284 ret = 0;
285 break;
286 case IIO_CHAN_INFO_SCALE:
287 if (val) {
288 ret = -EINVAL;
289 goto out;
290 }
291 for (i = 0; i < ARRAY_SIZE(ad7152_scale_table); i++)
292 if (val2 == ad7152_scale_table[i])
293 break;
294
295 chip->setup[chan->channel] &= ~AD7152_SETUP_RANGE_4pF;
296 chip->setup[chan->channel] |= AD7152_SETUP_RANGE(i);
297
298 ret = i2c_smbus_write_byte_data(chip->client,
299 ad7152_addresses[chan->channel][AD7152_SETUP],
300 chip->setup[chan->channel]);
301 if (ret < 0)
302 goto out;
303
304 ret = 0;
305 break;
306 case IIO_CHAN_INFO_SAMP_FREQ:
307 if (val2) {
308 ret = -EINVAL;
309 goto out;
310 }
311 ret = ad7152_write_raw_samp_freq(&indio_dev->dev, val);
312 if (ret < 0)
313 goto out;
314
315 ret = 0;
316 break;
317 default:
318 ret = -EINVAL;
319 }
320
321out:
322 mutex_unlock(&chip->state_lock);
323 return ret;
324}
325
326static int ad7152_read_raw(struct iio_dev *indio_dev,
327 struct iio_chan_spec const *chan,
328 int *val, int *val2,
329 long mask)
330{
331 struct ad7152_chip_info *chip = iio_priv(indio_dev);
332 int ret;
333 u8 regval = 0;
334
335 mutex_lock(&chip->state_lock);
336
337 switch (mask) {
338 case IIO_CHAN_INFO_RAW:
339
340
341 regval = chip->setup[chan->channel];
342
343 if (chan->differential)
344 chip->setup[chan->channel] |= AD7152_SETUP_CAPDIFF;
345 else
346 chip->setup[chan->channel] &= ~AD7152_SETUP_CAPDIFF;
347
348 if (regval != chip->setup[chan->channel]) {
349 ret = i2c_smbus_write_byte_data(chip->client,
350 ad7152_addresses[chan->channel][AD7152_SETUP],
351 chip->setup[chan->channel]);
352 if (ret < 0)
353 goto out;
354 }
355
356 if (chan->channel == 0)
357 regval = AD7152_CONF_CH1EN;
358 else
359 regval = AD7152_CONF_CH2EN;
360
361
362 regval |= AD7152_CONF_MODE_SINGLE_CONV;
363 ret = i2c_smbus_write_byte_data(chip->client, AD7152_REG_CFG,
364 regval);
365 if (ret < 0)
366 goto out;
367
368 msleep(ad7152_filter_rate_table[chip->filter_rate_setup][1]);
369
370 ret = i2c_smbus_read_word_data(chip->client,
371 ad7152_addresses[chan->channel][AD7152_DATA]);
372 if (ret < 0)
373 goto out;
374 *val = swab16(ret);
375
376 if (chan->differential)
377 *val -= 0x8000;
378
379 ret = IIO_VAL_INT;
380 break;
381 case IIO_CHAN_INFO_CALIBSCALE:
382
383 ret = i2c_smbus_read_word_data(chip->client,
384 ad7152_addresses[chan->channel][AD7152_GAIN]);
385 if (ret < 0)
386 goto out;
387
388 *val = 1;
389 *val2 = (15625 * swab16(ret)) / 1024;
390
391 ret = IIO_VAL_INT_PLUS_MICRO;
392 break;
393 case IIO_CHAN_INFO_CALIBBIAS:
394 ret = i2c_smbus_read_word_data(chip->client,
395 ad7152_addresses[chan->channel][AD7152_OFFS]);
396 if (ret < 0)
397 goto out;
398 *val = swab16(ret);
399
400 ret = IIO_VAL_INT;
401 break;
402 case IIO_CHAN_INFO_SCALE:
403 ret = i2c_smbus_read_byte_data(chip->client,
404 ad7152_addresses[chan->channel][AD7152_SETUP]);
405 if (ret < 0)
406 goto out;
407 *val = 0;
408 *val2 = ad7152_scale_table[ret >> 6];
409
410 ret = IIO_VAL_INT_PLUS_NANO;
411 break;
412 case IIO_CHAN_INFO_SAMP_FREQ:
413 ret = ad7152_read_raw_samp_freq(&indio_dev->dev, val);
414 if (ret < 0)
415 goto out;
416
417 ret = IIO_VAL_INT;
418 break;
419 default:
420 ret = -EINVAL;
421 }
422out:
423 mutex_unlock(&chip->state_lock);
424 return ret;
425}
426
427static int ad7152_write_raw_get_fmt(struct iio_dev *indio_dev,
428 struct iio_chan_spec const *chan,
429 long mask)
430{
431 switch (mask) {
432 case IIO_CHAN_INFO_SCALE:
433 return IIO_VAL_INT_PLUS_NANO;
434 default:
435 return IIO_VAL_INT_PLUS_MICRO;
436 }
437}
438
439static const struct iio_info ad7152_info = {
440 .attrs = &ad7152_attribute_group,
441 .read_raw = ad7152_read_raw,
442 .write_raw = ad7152_write_raw,
443 .write_raw_get_fmt = ad7152_write_raw_get_fmt,
444};
445
446static const struct iio_chan_spec ad7152_channels[] = {
447 {
448 .type = IIO_CAPACITANCE,
449 .indexed = 1,
450 .channel = 0,
451 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
452 BIT(IIO_CHAN_INFO_CALIBSCALE) |
453 BIT(IIO_CHAN_INFO_CALIBBIAS) |
454 BIT(IIO_CHAN_INFO_SCALE),
455 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
456 }, {
457 .type = IIO_CAPACITANCE,
458 .differential = 1,
459 .indexed = 1,
460 .channel = 0,
461 .channel2 = 2,
462 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
463 BIT(IIO_CHAN_INFO_CALIBSCALE) |
464 BIT(IIO_CHAN_INFO_CALIBBIAS) |
465 BIT(IIO_CHAN_INFO_SCALE),
466 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
467 }, {
468 .type = IIO_CAPACITANCE,
469 .indexed = 1,
470 .channel = 1,
471 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
472 BIT(IIO_CHAN_INFO_CALIBSCALE) |
473 BIT(IIO_CHAN_INFO_CALIBBIAS) |
474 BIT(IIO_CHAN_INFO_SCALE),
475 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
476 }, {
477 .type = IIO_CAPACITANCE,
478 .differential = 1,
479 .indexed = 1,
480 .channel = 1,
481 .channel2 = 3,
482 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
483 BIT(IIO_CHAN_INFO_CALIBSCALE) |
484 BIT(IIO_CHAN_INFO_CALIBBIAS) |
485 BIT(IIO_CHAN_INFO_SCALE),
486 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
487 }
488};
489
490
491
492
493
494static int ad7152_probe(struct i2c_client *client,
495 const struct i2c_device_id *id)
496{
497 int ret = 0;
498 struct ad7152_chip_info *chip;
499 struct iio_dev *indio_dev;
500
501 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
502 if (!indio_dev)
503 return -ENOMEM;
504 chip = iio_priv(indio_dev);
505
506 i2c_set_clientdata(client, indio_dev);
507
508 chip->client = client;
509 mutex_init(&chip->state_lock);
510
511
512 indio_dev->name = id->name;
513 indio_dev->dev.parent = &client->dev;
514 indio_dev->info = &ad7152_info;
515 indio_dev->channels = ad7152_channels;
516 if (id->driver_data == 0)
517 indio_dev->num_channels = ARRAY_SIZE(ad7152_channels);
518 else
519 indio_dev->num_channels = 2;
520 indio_dev->num_channels = ARRAY_SIZE(ad7152_channels);
521 indio_dev->modes = INDIO_DIRECT_MODE;
522
523 ret = devm_iio_device_register(indio_dev->dev.parent, indio_dev);
524 if (ret)
525 return ret;
526
527 dev_err(&client->dev, "%s capacitive sensor registered\n", id->name);
528
529 return 0;
530}
531
532static const struct i2c_device_id ad7152_id[] = {
533 { "ad7152", 0 },
534 { "ad7153", 1 },
535 {}
536};
537
538MODULE_DEVICE_TABLE(i2c, ad7152_id);
539
540static struct i2c_driver ad7152_driver = {
541 .driver = {
542 .name = KBUILD_MODNAME,
543 },
544 .probe = ad7152_probe,
545 .id_table = ad7152_id,
546};
547module_i2c_driver(ad7152_driver);
548
549MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
550MODULE_DESCRIPTION("Analog Devices AD7152/3 capacitive sensor driver");
551MODULE_LICENSE("GPL v2");
552
