1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * core.h - DesignWare HS OTG Controller common declarations 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#ifndef __DWC2_CORE_H__ 39#define __DWC2_CORE_H__ 40 41#include <linux/phy/phy.h> 42#include <linux/regulator/consumer.h> 43#include <linux/usb/gadget.h> 44#include <linux/usb/otg.h> 45#include <linux/usb/phy.h> 46#include "hw.h" 47 48/* 49 * Suggested defines for tracers: 50 * - no_printk: Disable tracing 51 * - pr_info: Print this info to the console 52 * - trace_printk: Print this info to trace buffer (good for verbose logging) 53 */ 54 55#define DWC2_TRACE_SCHEDULER no_printk 56#define DWC2_TRACE_SCHEDULER_VB no_printk 57 58/* Detailed scheduler tracing, but won't overwhelm console */ 59#define dwc2_sch_dbg(hsotg, fmt, ...) \ 60 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 61 dev_name(hsotg->dev), ##__VA_ARGS__) 62 63/* Verbose scheduler tracing */ 64#define dwc2_sch_vdbg(hsotg, fmt, ...) \ 65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 66 dev_name(hsotg->dev), ##__VA_ARGS__) 67 68#ifdef CONFIG_MIPS 69/* 70 * There are some MIPS machines that can run in either big-endian 71 * or little-endian mode and that use the dwc2 register without 72 * a byteswap in both ways. 73 * Unlike other architectures, MIPS apparently does not require a 74 * barrier before the __raw_writel() to synchronize with DMA but does 75 * require the barrier after the __raw_writel() to serialize a set of 76 * writes. This set of operations was added specifically for MIPS and 77 * should only be used there. 78 */ 79static inline u32 dwc2_readl(const void __iomem *addr) 80{ 81 u32 value = __raw_readl(addr); 82 83 /* In order to preserve endianness __raw_* operation is used. Therefore 84 * a barrier is needed to ensure IO access is not re-ordered across 85 * reads or writes 86 */ 87 mb(); 88 return value; 89} 90 91static inline void dwc2_writel(u32 value, void __iomem *addr) 92{ 93 __raw_writel(value, addr); 94 95 /* 96 * In order to preserve endianness __raw_* operation is used. Therefore 97 * a barrier is needed to ensure IO access is not re-ordered across 98 * reads or writes 99 */ 100 mb(); 101#ifdef DWC2_LOG_WRITES 102 pr_info("INFO:: wrote %08x to %p\n", value, addr); 103#endif 104} 105#else 106/* Normal architectures just use readl/write */ 107static inline u32 dwc2_readl(const void __iomem *addr) 108{ 109 return readl(addr); 110} 111 112static inline void dwc2_writel(u32 value, void __iomem *addr) 113{ 114 writel(value, addr); 115 116#ifdef DWC2_LOG_WRITES 117 pr_info("info:: wrote %08x to %p\n", value, addr); 118#endif 119} 120#endif 121 122/* Maximum number of Endpoints/HostChannels */ 123#define MAX_EPS_CHANNELS 16 124 125/* dwc2-hsotg declarations */ 126static const char * const dwc2_hsotg_supply_names[] = { 127 "vusb_d", /* digital USB supply, 1.2V */ 128 "vusb_a", /* analog USB supply, 1.1V */ 129}; 130 131#define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 132 133/* 134 * EP0_MPS_LIMIT 135 * 136 * Unfortunately there seems to be a limit of the amount of data that can 137 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 138 * packets (which practically means 1 packet and 63 bytes of data) when the 139 * MPS is set to 64. 140 * 141 * This means if we are wanting to move >127 bytes of data, we need to 142 * split the transactions up, but just doing one packet at a time does 143 * not work (this may be an implicit DATA0 PID on first packet of the 144 * transaction) and doing 2 packets is outside the controller's limits. 145 * 146 * If we try to lower the MPS size for EP0, then no transfers work properly 147 * for EP0, and the system will fail basic enumeration. As no cause for this 148 * has currently been found, we cannot support any large IN transfers for 149 * EP0. 150 */ 151#define EP0_MPS_LIMIT 64 152 153struct dwc2_hsotg; 154struct dwc2_hsotg_req; 155 156/** 157 * struct dwc2_hsotg_ep - driver endpoint definition. 158 * @ep: The gadget layer representation of the endpoint. 159 * @name: The driver generated name for the endpoint. 160 * @queue: Queue of requests for this endpoint. 161 * @parent: Reference back to the parent device structure. 162 * @req: The current request that the endpoint is processing. This is 163 * used to indicate an request has been loaded onto the endpoint 164 * and has yet to be completed (maybe due to data move, or simply 165 * awaiting an ack from the core all the data has been completed). 166 * @debugfs: File entry for debugfs file for this endpoint. 167 * @lock: State lock to protect contents of endpoint. 168 * @dir_in: Set to true if this endpoint is of the IN direction, which 169 * means that it is sending data to the Host. 170 * @index: The index for the endpoint registers. 171 * @mc: Multi Count - number of transactions per microframe 172 * @interval - Interval for periodic endpoints, in frames or microframes. 173 * @name: The name array passed to the USB core. 174 * @halted: Set if the endpoint has been halted. 175 * @periodic: Set if this is a periodic ep, such as Interrupt 176 * @isochronous: Set if this is a isochronous ep 177 * @send_zlp: Set if we need to send a zero-length packet. 178 * @desc_list_dma: The DMA address of descriptor chain currently in use. 179 * @desc_list: Pointer to descriptor DMA chain head currently in use. 180 * @desc_count: Count of entries within the DMA descriptor chain of EP. 181 * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1. 182 * @next_desc: index of next free descriptor in the ISOC chain under SW control. 183 * @total_data: The total number of data bytes done. 184 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 185 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 186 * @last_load: The offset of data for the last start of request. 187 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 188 * @target_frame: Targeted frame num to setup next ISOC transfer 189 * @frame_overrun: Indicates SOF number overrun in DSTS 190 * 191 * This is the driver's state for each registered enpoint, allowing it 192 * to keep track of transactions that need doing. Each endpoint has a 193 * lock to protect the state, to try and avoid using an overall lock 194 * for the host controller as much as possible. 195 * 196 * For periodic IN endpoints, we have fifo_size and fifo_load to try 197 * and keep track of the amount of data in the periodic FIFO for each 198 * of these as we don't have a status register that tells us how much 199 * is in each of them. (note, this may actually be useless information 200 * as in shared-fifo mode periodic in acts like a single-frame packet 201 * buffer than a fifo) 202 */ 203struct dwc2_hsotg_ep { 204 struct usb_ep ep; 205 struct list_head queue; 206 struct dwc2_hsotg *parent; 207 struct dwc2_hsotg_req *req; 208 struct dentry *debugfs; 209 210 unsigned long total_data; 211 unsigned int size_loaded; 212 unsigned int last_load; 213 unsigned int fifo_load; 214 unsigned short fifo_size; 215 unsigned short fifo_index; 216 217 unsigned char dir_in; 218 unsigned char index; 219 unsigned char mc; 220 unsigned char interval; 221 222 unsigned int halted:1; 223 unsigned int periodic:1; 224 unsigned int isochronous:1; 225 unsigned int send_zlp:1; 226 unsigned int target_frame; 227#define TARGET_FRAME_INITIAL 0xFFFFFFFF 228 bool frame_overrun; 229 230 dma_addr_t desc_list_dma; 231 struct dwc2_dma_desc *desc_list; 232 u8 desc_count; 233 234 unsigned char isoc_chain_num; 235 unsigned int next_desc; 236 237 char name[10]; 238}; 239 240/** 241 * struct dwc2_hsotg_req - data transfer request 242 * @req: The USB gadget request 243 * @queue: The list of requests for the endpoint this is queued for. 244 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 245 */ 246struct dwc2_hsotg_req { 247 struct usb_request req; 248 struct list_head queue; 249 void *saved_req_buf; 250}; 251 252#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 253 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 254#define call_gadget(_hs, _entry) \ 255do { \ 256 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 257 (_hs)->driver && (_hs)->driver->_entry) { \ 258 spin_unlock(&_hs->lock); \ 259 (_hs)->driver->_entry(&(_hs)->gadget); \ 260 spin_lock(&_hs->lock); \ 261 } \ 262} while (0) 263#else 264#define call_gadget(_hs, _entry) do {} while (0) 265#endif 266 267struct dwc2_hsotg; 268struct dwc2_host_chan; 269 270/* Device States */ 271enum dwc2_lx_state { 272 DWC2_L0, /* On state */ 273 DWC2_L1, /* LPM sleep state */ 274 DWC2_L2, /* USB suspend state */ 275 DWC2_L3, /* Off state */ 276}; 277 278/* Gadget ep0 states */ 279enum dwc2_ep0_state { 280 DWC2_EP0_SETUP, 281 DWC2_EP0_DATA_IN, 282 DWC2_EP0_DATA_OUT, 283 DWC2_EP0_STATUS_IN, 284 DWC2_EP0_STATUS_OUT, 285}; 286 287/** 288 * struct dwc2_core_params - Parameters for configuring the core 289 * 290 * @otg_cap: Specifies the OTG capabilities. 291 * 0 - HNP and SRP capable 292 * 1 - SRP Only capable 293 * 2 - No HNP/SRP capable (always available) 294 * Defaults to best available option (0, 1, then 2) 295 * @host_dma: Specifies whether to use slave or DMA mode for accessing 296 * the data FIFOs. The driver will automatically detect the 297 * value for this parameter if none is specified. 298 * 0 - Slave (always available) 299 * 1 - DMA (default, if available) 300 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 301 * address DMA mode or descriptor DMA mode for accessing 302 * the data FIFOs. The driver will automatically detect the 303 * value for this if none is specified. 304 * 0 - Address DMA 305 * 1 - Descriptor DMA (default, if available) 306 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 307 * address DMA mode or descriptor DMA mode for accessing 308 * the data FIFOs in Full Speed mode only. The driver 309 * will automatically detect the value for this if none is 310 * specified. 311 * 0 - Address DMA 312 * 1 - Descriptor DMA in FS (default, if available) 313 * @speed: Specifies the maximum speed of operation in host and 314 * device mode. The actual speed depends on the speed of 315 * the attached device and the value of phy_type. 316 * 0 - High Speed 317 * (default when phy_type is UTMI+ or ULPI) 318 * 1 - Full Speed 319 * (default when phy_type is Full Speed) 320 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 321 * 1 - Allow dynamic FIFO sizing (default, if available) 322 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 323 * are enabled for non-periodic IN endpoints in device 324 * mode. 325 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 326 * dynamic FIFO sizing is enabled 327 * 16 to 32768 328 * Actual maximum value is autodetected and also 329 * the default. 330 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 331 * in host mode when dynamic FIFO sizing is enabled 332 * 16 to 32768 333 * Actual maximum value is autodetected and also 334 * the default. 335 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 336 * host mode when dynamic FIFO sizing is enabled 337 * 16 to 32768 338 * Actual maximum value is autodetected and also 339 * the default. 340 * @max_transfer_size: The maximum transfer size supported, in bytes 341 * 2047 to 65,535 342 * Actual maximum value is autodetected and also 343 * the default. 344 * @max_packet_count: The maximum number of packets in a transfer 345 * 15 to 511 346 * Actual maximum value is autodetected and also 347 * the default. 348 * @host_channels: The number of host channel registers to use 349 * 1 to 16 350 * Actual maximum value is autodetected and also 351 * the default. 352 * @phy_type: Specifies the type of PHY interface to use. By default, 353 * the driver will automatically detect the phy_type. 354 * 0 - Full Speed Phy 355 * 1 - UTMI+ Phy 356 * 2 - ULPI Phy 357 * Defaults to best available option (2, 1, then 0) 358 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 359 * is applicable for a phy_type of UTMI+ or ULPI. (For a 360 * ULPI phy_type, this parameter indicates the data width 361 * between the MAC and the ULPI Wrapper.) Also, this 362 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 363 * parameter was set to "8 and 16 bits", meaning that the 364 * core has been configured to work at either data path 365 * width. 366 * 8 or 16 (default 16 if available) 367 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 368 * data rate. This parameter is only applicable if phy_type 369 * is ULPI. 370 * 0 - single data rate ULPI interface with 8 bit wide 371 * data bus (default) 372 * 1 - double data rate ULPI interface with 4 bit wide 373 * data bus 374 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 375 * external supply to drive the VBus 376 * 0 - Internal supply (default) 377 * 1 - External supply 378 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 379 * speed PHY. This parameter is only applicable if phy_type 380 * is FS. 381 * 0 - No (default) 382 * 1 - Yes 383 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 384 * 0 - No (default) 385 * 1 - Yes 386 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 387 * when attached to a Full Speed or Low Speed device in 388 * host mode. 389 * 0 - Don't support low power mode (default) 390 * 1 - Support low power mode 391 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 392 * when connected to a Low Speed device in host 393 * mode. This parameter is applicable only if 394 * host_support_fs_ls_low_power is enabled. 395 * 0 - 48 MHz 396 * (default when phy_type is UTMI+ or ULPI) 397 * 1 - 6 MHz 398 * (default when phy_type is Full Speed) 399 * @oc_disable: Flag to disable overcurrent condition. 400 * 0 - Allow overcurrent condition to get detected 401 * 1 - Disable overcurrent condtion to get detected 402 * @ts_dline: Enable Term Select Dline pulsing 403 * 0 - No (default) 404 * 1 - Yes 405 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 406 * 0 - No (default for core < 2.92a) 407 * 1 - Yes (default for core >= 2.92a) 408 * @ahbcfg: This field allows the default value of the GAHBCFG 409 * register to be overridden 410 * -1 - GAHBCFG value will be set to 0x06 411 * (INCR4, default) 412 * all others - GAHBCFG value will be overridden with 413 * this value 414 * Not all bits can be controlled like this, the 415 * bits defined by GAHBCFG_CTRL_MASK are controlled 416 * by the driver and are ignored in this 417 * configuration value. 418 * @uframe_sched: True to enable the microframe scheduler 419 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 420 * Disable CONIDSTSCHNG controller interrupt in such 421 * case. 422 * 0 - No (default) 423 * 1 - Yes 424 * @hibernation: Specifies whether the controller support hibernation. 425 * If hibernation is enabled, the controller will enter 426 * hibernation in both peripheral and host mode when 427 * needed. 428 * 0 - No (default) 429 * 1 - Yes 430 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 431 * register. 432 * 0 - Deactivate the transceiver (default) 433 * 1 - Activate the transceiver 434 * @g_dma: Enables gadget dma usage (default: autodetect). 435 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 436 * @g_rx_fifo_size: The periodic rx fifo size for the device, in 437 * DWORDS from 16-32768 (default: 2048 if 438 * possible, otherwise autodetect). 439 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 440 * DWORDS from 16-32768 (default: 1024 if 441 * possible, otherwise autodetect). 442 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 443 * mode. Each value corresponds to one EP 444 * starting from EP1 (max 15 values). Sizes are 445 * in DWORDS with possible values from from 446 * 16-32768 (default: 256, 256, 256, 256, 768, 447 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 448 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 449 * while full&low speed device connect. And change speed 450 * back to DWC2_SPEED_PARAM_HIGH while device is gone. 451 * 0 - No (default) 452 * 1 - Yes 453 * 454 * The following parameters may be specified when starting the module. These 455 * parameters define how the DWC_otg controller should be configured. A 456 * value of -1 (or any other out of range value) for any parameter means 457 * to read the value from hardware (if possible) or use the builtin 458 * default described above. 459 */ 460struct dwc2_core_params { 461 u8 otg_cap; 462#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 463#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 464#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 465 466 u8 phy_type; 467#define DWC2_PHY_TYPE_PARAM_FS 0 468#define DWC2_PHY_TYPE_PARAM_UTMI 1 469#define DWC2_PHY_TYPE_PARAM_ULPI 2 470 471 u8 speed; 472#define DWC2_SPEED_PARAM_HIGH 0 473#define DWC2_SPEED_PARAM_FULL 1 474#define DWC2_SPEED_PARAM_LOW 2 475 476 u8 phy_utmi_width; 477 bool phy_ulpi_ddr; 478 bool phy_ulpi_ext_vbus; 479 bool enable_dynamic_fifo; 480 bool en_multiple_tx_fifo; 481 bool i2c_enable; 482 bool ulpi_fs_ls; 483 bool ts_dline; 484 bool reload_ctl; 485 bool uframe_sched; 486 bool external_id_pin_ctl; 487 bool hibernation; 488 bool activate_stm_fs_transceiver; 489 u16 max_packet_count; 490 u32 max_transfer_size; 491 u32 ahbcfg; 492 493 /* Host parameters */ 494 bool host_dma; 495 bool dma_desc_enable; 496 bool dma_desc_fs_enable; 497 bool host_support_fs_ls_low_power; 498 bool host_ls_low_power_phy_clk; 499 bool oc_disable; 500 501 u8 host_channels; 502 u16 host_rx_fifo_size; 503 u16 host_nperio_tx_fifo_size; 504 u16 host_perio_tx_fifo_size; 505 506 /* Gadget parameters */ 507 bool g_dma; 508 bool g_dma_desc; 509 u32 g_rx_fifo_size; 510 u32 g_np_tx_fifo_size; 511 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 512 513 bool change_speed_quirk; 514}; 515 516/** 517 * struct dwc2_hw_params - Autodetected parameters. 518 * 519 * These parameters are the various parameters read from hardware 520 * registers during initialization. They typically contain the best 521 * supported or maximum value that can be configured in the 522 * corresponding dwc2_core_params value. 523 * 524 * The values that are not in dwc2_core_params are documented below. 525 * 526 * @op_mode Mode of Operation 527 * 0 - HNP- and SRP-Capable OTG (Host & Device) 528 * 1 - SRP-Capable OTG (Host & Device) 529 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 530 * 3 - SRP-Capable Device 531 * 4 - Non-OTG Device 532 * 5 - SRP-Capable Host 533 * 6 - Non-OTG Host 534 * @arch Architecture 535 * 0 - Slave only 536 * 1 - External DMA 537 * 2 - Internal DMA 538 * @power_optimized Are power optimizations enabled? 539 * @num_dev_ep Number of device endpoints available 540 * @num_dev_in_eps Number of device IN endpoints available 541 * @num_dev_perio_in_ep Number of device periodic IN endpoints 542 * available 543 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 544 * Depth 545 * 0 to 30 546 * @host_perio_tx_q_depth 547 * Host Mode Periodic Request Queue Depth 548 * 2, 4 or 8 549 * @nperio_tx_q_depth 550 * Non-Periodic Request Queue Depth 551 * 2, 4 or 8 552 * @hs_phy_type High-speed PHY interface type 553 * 0 - High-speed interface not supported 554 * 1 - UTMI+ 555 * 2 - ULPI 556 * 3 - UTMI+ and ULPI 557 * @fs_phy_type Full-speed PHY interface type 558 * 0 - Full speed interface not supported 559 * 1 - Dedicated full speed interface 560 * 2 - FS pins shared with UTMI+ pins 561 * 3 - FS pins shared with ULPI pins 562 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 563 * @utmi_phy_data_width UTMI+ PHY data width 564 * 0 - 8 bits 565 * 1 - 16 bits 566 * 2 - 8 or 16 bits 567 * @snpsid: Value from SNPSID register 568 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 569 * @g_tx_fifo_size[] Power-on values of TxFIFO sizes 570 */ 571struct dwc2_hw_params { 572 unsigned op_mode:3; 573 unsigned arch:2; 574 unsigned dma_desc_enable:1; 575 unsigned enable_dynamic_fifo:1; 576 unsigned en_multiple_tx_fifo:1; 577 unsigned rx_fifo_size:16; 578 unsigned host_nperio_tx_fifo_size:16; 579 unsigned dev_nperio_tx_fifo_size:16; 580 unsigned host_perio_tx_fifo_size:16; 581 unsigned nperio_tx_q_depth:3; 582 unsigned host_perio_tx_q_depth:3; 583 unsigned dev_token_q_depth:5; 584 unsigned max_transfer_size:26; 585 unsigned max_packet_count:11; 586 unsigned host_channels:5; 587 unsigned hs_phy_type:2; 588 unsigned fs_phy_type:2; 589 unsigned i2c_enable:1; 590 unsigned num_dev_ep:4; 591 unsigned num_dev_in_eps : 4; 592 unsigned num_dev_perio_in_ep:4; 593 unsigned total_fifo_size:16; 594 unsigned power_optimized:1; 595 unsigned utmi_phy_data_width:2; 596 u32 snpsid; 597 u32 dev_ep_dirs; 598 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 599}; 600 601/* Size of control and EP0 buffers */ 602#define DWC2_CTRL_BUFF_SIZE 8 603 604/** 605 * struct dwc2_gregs_backup - Holds global registers state before 606 * entering partial power down 607 * @gotgctl: Backup of GOTGCTL register 608 * @gintmsk: Backup of GINTMSK register 609 * @gahbcfg: Backup of GAHBCFG register 610 * @gusbcfg: Backup of GUSBCFG register 611 * @grxfsiz: Backup of GRXFSIZ register 612 * @gnptxfsiz: Backup of GNPTXFSIZ register 613 * @gi2cctl: Backup of GI2CCTL register 614 * @hptxfsiz: Backup of HPTXFSIZ register 615 * @gdfifocfg: Backup of GDFIFOCFG register 616 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 617 * @gpwrdn: Backup of GPWRDN register 618 */ 619struct dwc2_gregs_backup { 620 u32 gotgctl; 621 u32 gintmsk; 622 u32 gahbcfg; 623 u32 gusbcfg; 624 u32 grxfsiz; 625 u32 gnptxfsiz; 626 u32 gi2cctl; 627 u32 hptxfsiz; 628 u32 pcgcctl; 629 u32 gdfifocfg; 630 u32 dtxfsiz[MAX_EPS_CHANNELS]; 631 u32 gpwrdn; 632 bool valid; 633}; 634 635/** 636 * struct dwc2_dregs_backup - Holds device registers state before 637 * entering partial power down 638 * @dcfg: Backup of DCFG register 639 * @dctl: Backup of DCTL register 640 * @daintmsk: Backup of DAINTMSK register 641 * @diepmsk: Backup of DIEPMSK register 642 * @doepmsk: Backup of DOEPMSK register 643 * @diepctl: Backup of DIEPCTL register 644 * @dieptsiz: Backup of DIEPTSIZ register 645 * @diepdma: Backup of DIEPDMA register 646 * @doepctl: Backup of DOEPCTL register 647 * @doeptsiz: Backup of DOEPTSIZ register 648 * @doepdma: Backup of DOEPDMA register 649 */ 650struct dwc2_dregs_backup { 651 u32 dcfg; 652 u32 dctl; 653 u32 daintmsk; 654 u32 diepmsk; 655 u32 doepmsk; 656 u32 diepctl[MAX_EPS_CHANNELS]; 657 u32 dieptsiz[MAX_EPS_CHANNELS]; 658 u32 diepdma[MAX_EPS_CHANNELS]; 659 u32 doepctl[MAX_EPS_CHANNELS]; 660 u32 doeptsiz[MAX_EPS_CHANNELS]; 661 u32 doepdma[MAX_EPS_CHANNELS]; 662 bool valid; 663}; 664 665/** 666 * struct dwc2_hregs_backup - Holds host registers state before 667 * entering partial power down 668 * @hcfg: Backup of HCFG register 669 * @haintmsk: Backup of HAINTMSK register 670 * @hcintmsk: Backup of HCINTMSK register 671 * @hptr0: Backup of HPTR0 register 672 * @hfir: Backup of HFIR register 673 */ 674struct dwc2_hregs_backup { 675 u32 hcfg; 676 u32 haintmsk; 677 u32 hcintmsk[MAX_EPS_CHANNELS]; 678 u32 hprt0; 679 u32 hfir; 680 bool valid; 681}; 682 683/* 684 * Constants related to high speed periodic scheduling 685 * 686 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 687 * reservation point of view it's assumed that the schedule goes right back to 688 * the beginning after the end of the schedule. 689 * 690 * What does that mean for scheduling things with a long interval? It means 691 * we'll reserve time for them in every possible microframe that they could 692 * ever be scheduled in. ...but we'll still only actually schedule them as 693 * often as they were requested. 694 * 695 * We keep our schedule in a "bitmap" structure. This simplifies having 696 * to keep track of and merge intervals: we just let the bitmap code do most 697 * of the heavy lifting. In a way scheduling is much like memory allocation. 698 * 699 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 700 * supposed to schedule for periodic transfers). That's according to spec. 701 * 702 * Note that though we only schedule 80% of each microframe, the bitmap that we 703 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 704 * space for each uFrame). 705 * 706 * Requirements: 707 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 708 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 709 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 710 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 711 */ 712#define DWC2_US_PER_UFRAME 125 713#define DWC2_HS_PERIODIC_US_PER_UFRAME 100 714 715#define DWC2_HS_SCHEDULE_UFRAMES 8 716#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 717 DWC2_HS_PERIODIC_US_PER_UFRAME) 718 719/* 720 * Constants related to low speed scheduling 721 * 722 * For high speed we schedule every 1us. For low speed that's a bit overkill, 723 * so we make up a unit called a "slice" that's worth 25us. There are 40 724 * slices in a full frame and we can schedule 36 of those (90%) for periodic 725 * transfers. 726 * 727 * Our low speed schedule can be as short as 1 frame or could be longer. When 728 * we only schedule 1 frame it means that we'll need to reserve a time every 729 * frame even for things that only transfer very rarely, so something that runs 730 * every 2048 frames will get time reserved in every frame. Our low speed 731 * schedule can be longer and we'll be able to handle more overlap, but that 732 * will come at increased memory cost and increased time to schedule. 733 * 734 * Note: one other advantage of a short low speed schedule is that if we mess 735 * up and miss scheduling we can jump in and use any of the slots that we 736 * happened to reserve. 737 * 738 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 739 * the schedule. There will be one schedule per TT. 740 * 741 * Requirements: 742 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 743 */ 744#define DWC2_US_PER_SLICE 25 745#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 746 747#define DWC2_ROUND_US_TO_SLICE(us) \ 748 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 749 DWC2_US_PER_SLICE) 750 751#define DWC2_LS_PERIODIC_US_PER_FRAME \ 752 900 753#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 754 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 755 DWC2_US_PER_SLICE) 756 757#define DWC2_LS_SCHEDULE_FRAMES 1 758#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 759 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 760 761/** 762 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 763 * and periodic schedules 764 * 765 * These are common for both host and peripheral modes: 766 * 767 * @dev: The struct device pointer 768 * @regs: Pointer to controller regs 769 * @hw_params: Parameters that were autodetected from the 770 * hardware registers 771 * @core_params: Parameters that define how the core should be configured 772 * @op_state: The operational State, during transitions (a_host=> 773 * a_peripheral and b_device=>b_host) this may not match 774 * the core, but allows the software to determine 775 * transitions 776 * @dr_mode: Requested mode of operation, one of following: 777 * - USB_DR_MODE_PERIPHERAL 778 * - USB_DR_MODE_HOST 779 * - USB_DR_MODE_OTG 780 * @hcd_enabled Host mode sub-driver initialization indicator. 781 * @gadget_enabled Peripheral mode sub-driver initialization indicator. 782 * @ll_hw_enabled Status of low-level hardware resources. 783 * @phy: The otg phy transceiver structure for phy control. 784 * @uphy: The otg phy transceiver structure for old USB phy 785 * control. 786 * @plat: The platform specific configuration data. This can be 787 * removed once all SoCs support usb transceiver. 788 * @supplies: Definition of USB power supplies 789 * @phyif: PHY interface width 790 * @lock: Spinlock that protects all the driver data structures 791 * @priv: Stores a pointer to the struct usb_hcd 792 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 793 * transfer are in process of being queued 794 * @srp_success: Stores status of SRP request in the case of a FS PHY 795 * with an I2C interface 796 * @wq_otg: Workqueue object used for handling of some interrupts 797 * @wf_otg: Work object for handling Connector ID Status Change 798 * interrupt 799 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 800 * @lx_state: Lx state of connected device 801 * @gregs_backup: Backup of global registers during suspend 802 * @dregs_backup: Backup of device registers during suspend 803 * @hregs_backup: Backup of host registers during suspend 804 * 805 * These are for host mode: 806 * 807 * @flags: Flags for handling root port state changes 808 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 809 * Transfers associated with these QHs are not currently 810 * assigned to a host channel. 811 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 812 * Transfers associated with these QHs are currently 813 * assigned to a host channel. 814 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 815 * non-periodic schedule 816 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 817 * list of QHs for periodic transfers that are _not_ 818 * scheduled for the next frame. Each QH in the list has an 819 * interval counter that determines when it needs to be 820 * scheduled for execution. This scheduling mechanism 821 * allows only a simple calculation for periodic bandwidth 822 * used (i.e. must assume that all periodic transfers may 823 * need to execute in the same frame). However, it greatly 824 * simplifies scheduling and should be sufficient for the 825 * vast majority of OTG hosts, which need to connect to a 826 * small number of peripherals at one time. Items move from 827 * this list to periodic_sched_ready when the QH interval 828 * counter is 0 at SOF. 829 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 830 * the next frame, but have not yet been assigned to host 831 * channels. Items move from this list to 832 * periodic_sched_assigned as host channels become 833 * available during the current frame. 834 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 835 * frame that are assigned to host channels. Items move 836 * from this list to periodic_sched_queued as the 837 * transactions for the QH are queued to the DWC_otg 838 * controller. 839 * @periodic_sched_queued: List of periodic QHs that have been queued for 840 * execution. Items move from this list to either 841 * periodic_sched_inactive or periodic_sched_ready when the 842 * channel associated with the transfer is released. If the 843 * interval for the QH is 1, the item moves to 844 * periodic_sched_ready because it must be rescheduled for 845 * the next frame. Otherwise, the item moves to 846 * periodic_sched_inactive. 847 * @split_order: List keeping track of channels doing splits, in order. 848 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 849 * This value is in microseconds per (micro)frame. The 850 * assumption is that all periodic transfers may occur in 851 * the same (micro)frame. 852 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 853 * host is in high speed mode; low speed schedules are 854 * stored elsewhere since we need one per TT. 855 * @frame_number: Frame number read from the core at SOF. The value ranges 856 * from 0 to HFNUM_MAX_FRNUM. 857 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 858 * SOF enable/disable. 859 * @free_hc_list: Free host channels in the controller. This is a list of 860 * struct dwc2_host_chan items. 861 * @periodic_channels: Number of host channels assigned to periodic transfers. 862 * Currently assuming that there is a dedicated host 863 * channel for each periodic transaction and at least one 864 * host channel is available for non-periodic transactions. 865 * @non_periodic_channels: Number of host channels assigned to non-periodic 866 * transfers 867 * @available_host_channels Number of host channels available for the microframe 868 * scheduler to use 869 * @hc_ptr_array: Array of pointers to the host channel descriptors. 870 * Allows accessing a host channel descriptor given the 871 * host channel number. This is useful in interrupt 872 * handlers. 873 * @status_buf: Buffer used for data received during the status phase of 874 * a control transfer. 875 * @status_buf_dma: DMA address for status_buf 876 * @start_work: Delayed work for handling host A-cable connection 877 * @reset_work: Delayed work for handling a port reset 878 * @otg_port: OTG port number 879 * @frame_list: Frame list 880 * @frame_list_dma: Frame list DMA address 881 * @frame_list_sz: Frame list size 882 * @desc_gen_cache: Kmem cache for generic descriptors 883 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 884 * 885 * These are for peripheral mode: 886 * 887 * @driver: USB gadget driver 888 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 889 * @num_of_eps: Number of available EPs (excluding EP0) 890 * @debug_root: Root directrory for debugfs. 891 * @debug_file: Main status file for debugfs. 892 * @debug_testmode: Testmode status file for debugfs. 893 * @debug_fifo: FIFO status file for debugfs. 894 * @ep0_reply: Request used for ep0 reply. 895 * @ep0_buff: Buffer for EP0 reply data, if needed. 896 * @ctrl_buff: Buffer for EP0 control requests. 897 * @ctrl_req: Request for EP0 control packets. 898 * @ep0_state: EP0 control transfers state 899 * @test_mode: USB test mode requested by the host 900 * @setup_desc_dma: EP0 setup stage desc chain DMA address 901 * @setup_desc: EP0 setup stage desc chain pointer 902 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 903 * @ctrl_in_desc: EP0 IN data phase desc chain pointer 904 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 905 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 906 * @eps: The endpoints being supplied to the gadget framework 907 */ 908struct dwc2_hsotg { 909 struct device *dev; 910 void __iomem *regs; 911 /** Params detected from hardware */ 912 struct dwc2_hw_params hw_params; 913 /** Params to actually use */ 914 struct dwc2_core_params params; 915 enum usb_otg_state op_state; 916 enum usb_dr_mode dr_mode; 917 unsigned int hcd_enabled:1; 918 unsigned int gadget_enabled:1; 919 unsigned int ll_hw_enabled:1; 920 921 struct phy *phy; 922 struct usb_phy *uphy; 923 struct dwc2_hsotg_plat *plat; 924 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 925 u32 phyif; 926 927 spinlock_t lock; 928 void *priv; 929 int irq; 930 struct clk *clk; 931 struct reset_control *reset; 932 933 unsigned int queuing_high_bandwidth:1; 934 unsigned int srp_success:1; 935 936 struct workqueue_struct *wq_otg; 937 struct work_struct wf_otg; 938 struct timer_list wkp_timer; 939 enum dwc2_lx_state lx_state; 940 struct dwc2_gregs_backup gr_backup; 941 struct dwc2_dregs_backup dr_backup; 942 struct dwc2_hregs_backup hr_backup; 943 944 struct dentry *debug_root; 945 struct debugfs_regset32 *regset; 946 947 /* DWC OTG HW Release versions */ 948#define DWC2_CORE_REV_2_71a 0x4f54271a 949#define DWC2_CORE_REV_2_90a 0x4f54290a 950#define DWC2_CORE_REV_2_91a 0x4f54291a 951#define DWC2_CORE_REV_2_92a 0x4f54292a 952#define DWC2_CORE_REV_2_94a 0x4f54294a 953#define DWC2_CORE_REV_3_00a 0x4f54300a 954#define DWC2_CORE_REV_3_10a 0x4f54310a 955#define DWC2_FS_IOT_REV_1_00a 0x5531100a 956#define DWC2_HS_IOT_REV_1_00a 0x5532100a 957 958#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 959 union dwc2_hcd_internal_flags { 960 u32 d32; 961 struct { 962 unsigned port_connect_status_change:1; 963 unsigned port_connect_status:1; 964 unsigned port_reset_change:1; 965 unsigned port_enable_change:1; 966 unsigned port_suspend_change:1; 967 unsigned port_over_current_change:1; 968 unsigned port_l1_change:1; 969 unsigned reserved:25; 970 } b; 971 } flags; 972 973 struct list_head non_periodic_sched_inactive; 974 struct list_head non_periodic_sched_active; 975 struct list_head *non_periodic_qh_ptr; 976 struct list_head periodic_sched_inactive; 977 struct list_head periodic_sched_ready; 978 struct list_head periodic_sched_assigned; 979 struct list_head periodic_sched_queued; 980 struct list_head split_order; 981 u16 periodic_usecs; 982 unsigned long hs_periodic_bitmap[ 983 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 984 u16 frame_number; 985 u16 periodic_qh_count; 986 bool bus_suspended; 987 bool new_connection; 988 989 u16 last_frame_num; 990 991#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 992#define FRAME_NUM_ARRAY_SIZE 1000 993 u16 *frame_num_array; 994 u16 *last_frame_num_array; 995 int frame_num_idx; 996 int dumped_frame_num_array; 997#endif 998 999 struct list_head free_hc_list; 1000 int periodic_channels;
1001 int non_periodic_channels; 1002 int available_host_channels; 1003 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1004 u8 *status_buf; 1005 dma_addr_t status_buf_dma; 1006#define DWC2_HCD_STATUS_BUF_SIZE 64 1007 1008 struct delayed_work start_work; 1009 struct delayed_work reset_work; 1010 u8 otg_port; 1011 u32 *frame_list; 1012 dma_addr_t frame_list_dma; 1013 u32 frame_list_sz; 1014 struct kmem_cache *desc_gen_cache; 1015 struct kmem_cache *desc_hsisoc_cache; 1016 1017#ifdef DEBUG 1018 u32 frrem_samples; 1019 u64 frrem_accum; 1020 1021 u32 hfnum_7_samples_a; 1022 u64 hfnum_7_frrem_accum_a; 1023 u32 hfnum_0_samples_a; 1024 u64 hfnum_0_frrem_accum_a; 1025 u32 hfnum_other_samples_a; 1026 u64 hfnum_other_frrem_accum_a; 1027 1028 u32 hfnum_7_samples_b; 1029 u64 hfnum_7_frrem_accum_b; 1030 u32 hfnum_0_samples_b; 1031 u64 hfnum_0_frrem_accum_b; 1032 u32 hfnum_other_samples_b; 1033 u64 hfnum_other_frrem_accum_b; 1034#endif 1035#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1036 1037#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1038 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1039 /* Gadget structures */ 1040 struct usb_gadget_driver *driver; 1041 int fifo_mem; 1042 unsigned int dedicated_fifos:1; 1043 unsigned char num_of_eps; 1044 u32 fifo_map; 1045 1046 struct usb_request *ep0_reply; 1047 struct usb_request *ctrl_req; 1048 void *ep0_buff; 1049 void *ctrl_buff; 1050 enum dwc2_ep0_state ep0_state; 1051 u8 test_mode; 1052 1053 dma_addr_t setup_desc_dma[2]; 1054 struct dwc2_dma_desc *setup_desc[2]; 1055 dma_addr_t ctrl_in_desc_dma; 1056 struct dwc2_dma_desc *ctrl_in_desc; 1057 dma_addr_t ctrl_out_desc_dma; 1058 struct dwc2_dma_desc *ctrl_out_desc; 1059 1060 struct usb_gadget gadget; 1061 unsigned int enabled:1; 1062 unsigned int connected:1; 1063 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 1064 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1065#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1066}; 1067 1068/* Reasons for halting a host channel */ 1069enum dwc2_halt_status { 1070 DWC2_HC_XFER_NO_HALT_STATUS, 1071 DWC2_HC_XFER_COMPLETE, 1072 DWC2_HC_XFER_URB_COMPLETE, 1073 DWC2_HC_XFER_ACK, 1074 DWC2_HC_XFER_NAK, 1075 DWC2_HC_XFER_NYET, 1076 DWC2_HC_XFER_STALL, 1077 DWC2_HC_XFER_XACT_ERR, 1078 DWC2_HC_XFER_FRAME_OVERRUN, 1079 DWC2_HC_XFER_BABBLE_ERR, 1080 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1081 DWC2_HC_XFER_AHB_ERR, 1082 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1083 DWC2_HC_XFER_URB_DEQUEUE, 1084}; 1085 1086/* Core version information */ 1087static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 1088{ 1089 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 1090} 1091 1092static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 1093{ 1094 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 1095} 1096 1097static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 1098{ 1099 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 1100} 1101 1102/* 1103 * The following functions support initialization of the core driver component 1104 * and the DWC_otg controller 1105 */ 1106int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 1107int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 1108int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 1109int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 1110 1111bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host); 1112void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg); 1113void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1114 1115bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1116 1117/* 1118 * Common core Functions. 1119 * The following functions support managing the DWC_otg controller in either 1120 * device or host mode. 1121 */ 1122void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1123void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1124void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1125 1126void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1127void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1128 1129/* This function should be called on every hardware interrupt. */ 1130irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1131 1132/* The device ID match table */ 1133extern const struct of_device_id dwc2_of_match_table[]; 1134 1135int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1136int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1137 1138/* Parameters */ 1139int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1140int dwc2_init_params(struct dwc2_hsotg *hsotg); 1141 1142/* 1143 * The following functions check the controller's OTG operation mode 1144 * capability (GHWCFG2.OTG_MODE). 1145 * 1146 * These functions can be used before the internal hsotg->hw_params 1147 * are read in and cached so they always read directly from the 1148 * GHWCFG2 register. 1149 */ 1150unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 1151bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1152bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1153bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1154 1155/* 1156 * Returns the mode of operation, host or device 1157 */ 1158static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1159{ 1160 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1161} 1162 1163static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1164{ 1165 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1166} 1167 1168/* 1169 * Dump core registers and SPRAM 1170 */ 1171void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1172void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1173void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1174 1175/* Gadget defines */ 1176#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1177 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1178int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1179int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1180int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1181int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1182void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1183 bool reset); 1184void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1185void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1186int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1187#define dwc2_is_device_connected(hsotg) (hsotg->connected) 1188int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1189int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); 1190int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1191int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1192int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 1193#else 1194static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1195{ return 0; } 1196static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1197{ return 0; } 1198static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1199{ return 0; } 1200static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1201{ return 0; } 1202static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1203 bool reset) {} 1204static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1205static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1206static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1207 int testmode) 1208{ return 0; } 1209#define dwc2_is_device_connected(hsotg) (0) 1210static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1211{ return 0; } 1212static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 1213{ return 0; } 1214static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1215{ return 0; } 1216static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1217{ return 0; } 1218static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1219{ return 0; } 1220#endif 1221 1222#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1223int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1224int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1225void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1226void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1227void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1228int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1229int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1230#else 1231static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1232{ return 0; } 1233static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1234 int us) 1235{ return 0; } 1236static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1237static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1238static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1239static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1240static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1241{ return 0; } 1242static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1243{ return 0; } 1244static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1245{ return 0; } 1246 1247#endif 1248 1249#endif /* __DWC2_CORE_H__ */ 1250