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14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/of_platform.h>
26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29#include <linux/usb/phy.h>
30
31#include "core.h"
32#include "hw.h"
33
34
35static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
36{
37 return container_of(req, struct dwc2_hsotg_req, req);
38}
39
40static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
41{
42 return container_of(ep, struct dwc2_hsotg_ep, ep);
43}
44
45static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
46{
47 return container_of(gadget, struct dwc2_hsotg, gadget);
48}
49
50static inline void __orr32(void __iomem *ptr, u32 val)
51{
52 dwc2_writel(dwc2_readl(ptr) | val, ptr);
53}
54
55static inline void __bic32(void __iomem *ptr, u32 val)
56{
57 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
58}
59
60static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
61 u32 ep_index, u32 dir_in)
62{
63 if (dir_in)
64 return hsotg->eps_in[ep_index];
65 else
66 return hsotg->eps_out[ep_index];
67}
68
69
70static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
71
72
73
74
75
76
77
78
79
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88
89
90
91static inline bool using_dma(struct dwc2_hsotg *hsotg)
92{
93 return hsotg->params.g_dma;
94}
95
96
97
98
99
100
101
102static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
103{
104 return hsotg->params.g_dma_desc;
105}
106
107
108
109
110
111
112
113
114
115static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
116{
117 hs_ep->target_frame += hs_ep->interval;
118 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
119 hs_ep->frame_overrun = 1;
120 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
121 } else {
122 hs_ep->frame_overrun = 0;
123 }
124}
125
126
127
128
129
130
131static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
132{
133 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
134 u32 new_gsintmsk;
135
136 new_gsintmsk = gsintmsk | ints;
137
138 if (new_gsintmsk != gsintmsk) {
139 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
140 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
141 }
142}
143
144
145
146
147
148
149static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
150{
151 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
152 u32 new_gsintmsk;
153
154 new_gsintmsk = gsintmsk & ~ints;
155
156 if (new_gsintmsk != gsintmsk)
157 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
158}
159
160
161
162
163
164
165
166
167
168
169
170static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
171 unsigned int ep, unsigned int dir_in,
172 unsigned int en)
173{
174 unsigned long flags;
175 u32 bit = 1 << ep;
176 u32 daint;
177
178 if (!dir_in)
179 bit <<= 16;
180
181 local_irq_save(flags);
182 daint = dwc2_readl(hsotg->regs + DAINTMSK);
183 if (en)
184 daint |= bit;
185 else
186 daint &= ~bit;
187 dwc2_writel(daint, hsotg->regs + DAINTMSK);
188 local_irq_restore(flags);
189}
190
191
192
193
194int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
195{
196 if (hsotg->hw_params.en_multiple_tx_fifo)
197
198 return hsotg->hw_params.num_dev_in_eps;
199 else
200
201 return hsotg->hw_params.num_dev_perio_in_ep;
202}
203
204
205
206
207
208int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
209{
210 int addr;
211 int tx_addr_max;
212 u32 np_tx_fifo_size;
213
214 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
215 hsotg->params.g_np_tx_fifo_size);
216
217
218 tx_addr_max = hsotg->hw_params.total_fifo_size;
219
220 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
221 if (tx_addr_max <= addr)
222 return 0;
223
224 return tx_addr_max - addr;
225}
226
227
228
229
230
231int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
232{
233 int tx_fifo_count;
234 int tx_fifo_depth;
235
236 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
237
238 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
239
240 if (!tx_fifo_count)
241 return tx_fifo_depth;
242 else
243 return tx_fifo_depth / tx_fifo_count;
244}
245
246
247
248
249
250static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
251{
252 unsigned int ep;
253 unsigned int addr;
254 int timeout;
255 u32 val;
256 u32 *txfsz = hsotg->params.g_tx_fifo_size;
257
258
259 WARN_ON(hsotg->fifo_map);
260 hsotg->fifo_map = 0;
261
262
263 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ);
264 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) |
265 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
266 hsotg->regs + GNPTXFSIZ);
267
268
269
270
271
272
273
274
275
276 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
277
278
279
280
281
282
283 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
284 if (!txfsz[ep])
285 continue;
286 val = addr;
287 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
288 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
289 "insufficient fifo memory");
290 addr += txfsz[ep];
291
292 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
293 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
294 }
295
296 dwc2_writel(hsotg->hw_params.total_fifo_size |
297 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
298 hsotg->regs + GDFIFOCFG);
299
300
301
302
303
304 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
305 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
306
307
308 timeout = 100;
309 while (1) {
310 val = dwc2_readl(hsotg->regs + GRSTCTL);
311
312 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
313 break;
314
315 if (--timeout == 0) {
316 dev_err(hsotg->dev,
317 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
318 __func__, val);
319 break;
320 }
321
322 udelay(1);
323 }
324
325 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
326}
327
328
329
330
331
332
333
334static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
335 gfp_t flags)
336{
337 struct dwc2_hsotg_req *req;
338
339 req = kzalloc(sizeof(*req), flags);
340 if (!req)
341 return NULL;
342
343 INIT_LIST_HEAD(&req->queue);
344
345 return &req->req;
346}
347
348
349
350
351
352
353
354
355static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
356{
357 return hs_ep->periodic;
358}
359
360
361
362
363
364
365
366
367
368
369static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
370 struct dwc2_hsotg_ep *hs_ep,
371 struct dwc2_hsotg_req *hs_req)
372{
373 struct usb_request *req = &hs_req->req;
374
375 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
376}
377
378
379
380
381
382
383
384
385
386static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
387{
388 hsotg->setup_desc[0] =
389 dmam_alloc_coherent(hsotg->dev,
390 sizeof(struct dwc2_dma_desc),
391 &hsotg->setup_desc_dma[0],
392 GFP_KERNEL);
393 if (!hsotg->setup_desc[0])
394 goto fail;
395
396 hsotg->setup_desc[1] =
397 dmam_alloc_coherent(hsotg->dev,
398 sizeof(struct dwc2_dma_desc),
399 &hsotg->setup_desc_dma[1],
400 GFP_KERNEL);
401 if (!hsotg->setup_desc[1])
402 goto fail;
403
404 hsotg->ctrl_in_desc =
405 dmam_alloc_coherent(hsotg->dev,
406 sizeof(struct dwc2_dma_desc),
407 &hsotg->ctrl_in_desc_dma,
408 GFP_KERNEL);
409 if (!hsotg->ctrl_in_desc)
410 goto fail;
411
412 hsotg->ctrl_out_desc =
413 dmam_alloc_coherent(hsotg->dev,
414 sizeof(struct dwc2_dma_desc),
415 &hsotg->ctrl_out_desc_dma,
416 GFP_KERNEL);
417 if (!hsotg->ctrl_out_desc)
418 goto fail;
419
420 return 0;
421
422fail:
423 return -ENOMEM;
424}
425
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440
441
442static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
443 struct dwc2_hsotg_ep *hs_ep,
444 struct dwc2_hsotg_req *hs_req)
445{
446 bool periodic = is_ep_periodic(hs_ep);
447 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
448 int buf_pos = hs_req->req.actual;
449 int to_write = hs_ep->size_loaded;
450 void *data;
451 int can_write;
452 int pkt_round;
453 int max_transfer;
454
455 to_write -= (buf_pos - hs_ep->last_load);
456
457
458 if (to_write == 0)
459 return 0;
460
461 if (periodic && !hsotg->dedicated_fifos) {
462 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
463 int size_left;
464 int size_done;
465
466
467
468
469
470
471 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
472
473
474
475
476
477 if (hs_ep->fifo_load != 0) {
478 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
479 return -ENOSPC;
480 }
481
482 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
483 __func__, size_left,
484 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
485
486
487 size_done = hs_ep->size_loaded - size_left;
488
489
490 can_write = hs_ep->fifo_load - size_done;
491 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
492 __func__, can_write);
493
494 can_write = hs_ep->fifo_size - can_write;
495 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
496 __func__, can_write);
497
498 if (can_write <= 0) {
499 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
500 return -ENOSPC;
501 }
502 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
503 can_write = dwc2_readl(hsotg->regs +
504 DTXFSTS(hs_ep->fifo_index));
505
506 can_write &= 0xffff;
507 can_write *= 4;
508 } else {
509 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
510 dev_dbg(hsotg->dev,
511 "%s: no queue slots available (0x%08x)\n",
512 __func__, gnptxsts);
513
514 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
515 return -ENOSPC;
516 }
517
518 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
519 can_write *= 4;
520 }
521
522 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
523
524 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
525 __func__, gnptxsts, can_write, to_write, max_transfer);
526
527
528
529
530
531
532 if (can_write > 512 && !periodic)
533 can_write = 512;
534
535
536
537
538
539
540 if (to_write > max_transfer) {
541 to_write = max_transfer;
542
543
544 if (!hsotg->dedicated_fifos)
545 dwc2_hsotg_en_gsint(hsotg,
546 periodic ? GINTSTS_PTXFEMP :
547 GINTSTS_NPTXFEMP);
548 }
549
550
551
552 if (to_write > can_write) {
553 to_write = can_write;
554 pkt_round = to_write % max_transfer;
555
556
557
558
559
560
561
562
563
564 if (pkt_round)
565 to_write -= pkt_round;
566
567
568
569
570
571
572
573 if (!hsotg->dedicated_fifos)
574 dwc2_hsotg_en_gsint(hsotg,
575 periodic ? GINTSTS_PTXFEMP :
576 GINTSTS_NPTXFEMP);
577 }
578
579 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
580 to_write, hs_req->req.length, can_write, buf_pos);
581
582 if (to_write <= 0)
583 return -ENOSPC;
584
585 hs_req->req.actual = buf_pos + to_write;
586 hs_ep->total_data += to_write;
587
588 if (periodic)
589 hs_ep->fifo_load += to_write;
590
591 to_write = DIV_ROUND_UP(to_write, 4);
592 data = hs_req->req.buf + buf_pos;
593
594 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
595
596 return (to_write >= can_write) ? -ENOSPC : 0;
597}
598
599
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601
602
603
604
605
606static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
607{
608 int index = hs_ep->index;
609 unsigned int maxsize;
610 unsigned int maxpkt;
611
612 if (index != 0) {
613 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
614 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
615 } else {
616 maxsize = 64 + 64;
617 if (hs_ep->dir_in)
618 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
619 else
620 maxpkt = 2;
621 }
622
623
624 maxpkt--;
625 maxsize--;
626
627
628
629
630
631
632 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
633 maxsize = maxpkt * hs_ep->ep.maxpacket;
634
635 return maxsize;
636}
637
638
639
640
641
642
643
644static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
645{
646 u32 dsts;
647
648 dsts = dwc2_readl(hsotg->regs + DSTS);
649 dsts &= DSTS_SOFFN_MASK;
650 dsts >>= DSTS_SOFFN_SHIFT;
651
652 return dsts;
653}
654
655
656
657
658
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661
662
663
664static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
665{
666 int is_isoc = hs_ep->isochronous;
667 unsigned int maxsize;
668
669 if (is_isoc)
670 maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
671 DEV_DMA_ISOC_RX_NBYTES_LIMIT;
672 else
673 maxsize = DEV_DMA_NBYTES_LIMIT;
674
675
676 maxsize *= MAX_DMA_DESC_NUM_GENERIC;
677
678 return maxsize;
679}
680
681
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689
690
691
692
693
694
695
696static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
697{
698 u32 mps = hs_ep->ep.maxpacket;
699 int dir_in = hs_ep->dir_in;
700 u32 desc_size = 0;
701
702 if (!hs_ep->index && !dir_in) {
703 desc_size = mps;
704 *mask = DEV_DMA_NBYTES_MASK;
705 } else if (hs_ep->isochronous) {
706 if (dir_in) {
707 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
708 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
709 } else {
710 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
711 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
712 }
713 } else {
714 desc_size = DEV_DMA_NBYTES_LIMIT;
715 *mask = DEV_DMA_NBYTES_MASK;
716
717
718 desc_size -= desc_size % mps;
719 }
720
721 return desc_size;
722}
723
724
725
726
727
728
729
730
731
732
733static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
734 dma_addr_t dma_buff,
735 unsigned int len)
736{
737 struct dwc2_hsotg *hsotg = hs_ep->parent;
738 int dir_in = hs_ep->dir_in;
739 struct dwc2_dma_desc *desc = hs_ep->desc_list;
740 u32 mps = hs_ep->ep.maxpacket;
741 u32 maxsize = 0;
742 u32 offset = 0;
743 u32 mask = 0;
744 int i;
745
746 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
747
748 hs_ep->desc_count = (len / maxsize) +
749 ((len % maxsize) ? 1 : 0);
750 if (len == 0)
751 hs_ep->desc_count = 1;
752
753 for (i = 0; i < hs_ep->desc_count; ++i) {
754 desc->status = 0;
755 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
756 << DEV_DMA_BUFF_STS_SHIFT);
757
758 if (len > maxsize) {
759 if (!hs_ep->index && !dir_in)
760 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
761
762 desc->status |= (maxsize <<
763 DEV_DMA_NBYTES_SHIFT & mask);
764 desc->buf = dma_buff + offset;
765
766 len -= maxsize;
767 offset += maxsize;
768 } else {
769 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
770
771 if (dir_in)
772 desc->status |= (len % mps) ? DEV_DMA_SHORT :
773 ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
774 if (len > maxsize)
775 dev_err(hsotg->dev, "wrong len %d\n", len);
776
777 desc->status |=
778 len << DEV_DMA_NBYTES_SHIFT & mask;
779 desc->buf = dma_buff + offset;
780 }
781
782 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
783 desc->status |= (DEV_DMA_BUFF_STS_HREADY
784 << DEV_DMA_BUFF_STS_SHIFT);
785 desc++;
786 }
787}
788
789
790
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795
796
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799
800
801
802static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
803 dma_addr_t dma_buff, unsigned int len)
804{
805 struct dwc2_dma_desc *desc;
806 struct dwc2_hsotg *hsotg = hs_ep->parent;
807 u32 index;
808 u32 maxsize = 0;
809 u32 mask = 0;
810
811 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
812 if (len > maxsize) {
813 dev_err(hsotg->dev, "wrong len %d\n", len);
814 return -EINVAL;
815 }
816
817
818
819
820
821 if (hs_ep->next_desc == MAX_DMA_DESC_NUM_GENERIC / 2)
822 return -EBUSY;
823
824
825 if (hs_ep->dir_in)
826 dwc2_gadget_incr_frame_num(hs_ep);
827
828 index = (MAX_DMA_DESC_NUM_GENERIC / 2) * hs_ep->isoc_chain_num +
829 hs_ep->next_desc;
830
831
832 if ((hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC) ||
833 (!hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC / 2)) {
834 dev_err(hsotg->dev, "wrong index %d for iso chain\n", index);
835 return -EINVAL;
836 }
837
838 desc = &hs_ep->desc_list[index];
839
840
841 if (hs_ep->next_desc)
842 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
843
844 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
845 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
846
847 desc->status = 0;
848 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
849
850 desc->buf = dma_buff;
851 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
852 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
853
854 if (hs_ep->dir_in) {
855 desc->status |= ((hs_ep->mc << DEV_DMA_ISOC_PID_SHIFT) &
856 DEV_DMA_ISOC_PID_MASK) |
857 ((len % hs_ep->ep.maxpacket) ?
858 DEV_DMA_SHORT : 0) |
859 ((hs_ep->target_frame <<
860 DEV_DMA_ISOC_FRNUM_SHIFT) &
861 DEV_DMA_ISOC_FRNUM_MASK);
862 }
863
864 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
865 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
866
867
868 hs_ep->next_desc++;
869
870 return 0;
871}
872
873
874
875
876
877
878
879
880
881
882
883static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
884{
885 struct dwc2_hsotg *hsotg = hs_ep->parent;
886 struct dwc2_hsotg_req *hs_req, *treq;
887 int index = hs_ep->index;
888 int ret;
889 u32 dma_reg;
890 u32 depctl;
891 u32 ctrl;
892
893 if (list_empty(&hs_ep->queue)) {
894 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
895 return;
896 }
897
898 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
899 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
900 hs_req->req.length);
901 if (ret) {
902 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
903 break;
904 }
905 }
906
907 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
908 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
909
910
911 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
912
913 ctrl = dwc2_readl(hsotg->regs + depctl);
914 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
915 dwc2_writel(ctrl, hsotg->regs + depctl);
916
917
918 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
919 hs_ep->next_desc = 0;
920}
921
922
923
924
925
926
927
928
929
930
931
932static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
933 struct dwc2_hsotg_ep *hs_ep,
934 struct dwc2_hsotg_req *hs_req,
935 bool continuing)
936{
937 struct usb_request *ureq = &hs_req->req;
938 int index = hs_ep->index;
939 int dir_in = hs_ep->dir_in;
940 u32 epctrl_reg;
941 u32 epsize_reg;
942 u32 epsize;
943 u32 ctrl;
944 unsigned int length;
945 unsigned int packets;
946 unsigned int maxreq;
947 unsigned int dma_reg;
948
949 if (index != 0) {
950 if (hs_ep->req && !continuing) {
951 dev_err(hsotg->dev, "%s: active request\n", __func__);
952 WARN_ON(1);
953 return;
954 } else if (hs_ep->req != hs_req && continuing) {
955 dev_err(hsotg->dev,
956 "%s: continue different req\n", __func__);
957 WARN_ON(1);
958 return;
959 }
960 }
961
962 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
963 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
964 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
965
966 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
967 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
968 hs_ep->dir_in ? "in" : "out");
969
970
971 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
972
973 if (index && ctrl & DXEPCTL_STALL) {
974 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
975 return;
976 }
977
978 length = ureq->length - ureq->actual;
979 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
980 ureq->length, ureq->actual);
981
982 if (!using_desc_dma(hsotg))
983 maxreq = get_ep_limit(hs_ep);
984 else
985 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
986
987 if (length > maxreq) {
988 int round = maxreq % hs_ep->ep.maxpacket;
989
990 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
991 __func__, length, maxreq, round);
992
993
994 if (round)
995 maxreq -= round;
996
997 length = maxreq;
998 }
999
1000 if (length)
1001 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1002 else
1003 packets = 1;
1004
1005 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1006 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
1007 return;
1008 }
1009
1010 if (dir_in && index != 0)
1011 if (hs_ep->isochronous)
1012 epsize = DXEPTSIZ_MC(packets);
1013 else
1014 epsize = DXEPTSIZ_MC(1);
1015 else
1016 epsize = 0;
1017
1018
1019
1020
1021
1022 if (dir_in && ureq->zero && !continuing) {
1023
1024 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1025 !(ureq->length % hs_ep->ep.maxpacket))
1026 hs_ep->send_zlp = 1;
1027 }
1028
1029 epsize |= DXEPTSIZ_PKTCNT(packets);
1030 epsize |= DXEPTSIZ_XFERSIZE(length);
1031
1032 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1033 __func__, packets, length, ureq->length, epsize, epsize_reg);
1034
1035
1036 hs_ep->req = hs_req;
1037
1038 if (using_desc_dma(hsotg)) {
1039 u32 offset = 0;
1040 u32 mps = hs_ep->ep.maxpacket;
1041
1042
1043 if (!dir_in) {
1044 if (!index)
1045 length = mps;
1046 else if (length % mps)
1047 length += (mps - (length % mps));
1048 }
1049
1050
1051
1052
1053
1054
1055 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1056 continuing)
1057 offset = ureq->actual;
1058
1059
1060 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1061 length);
1062
1063
1064 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
1065
1066 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1067 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1068 } else {
1069
1070 dwc2_writel(epsize, hsotg->regs + epsize_reg);
1071
1072 if (using_dma(hsotg) && !continuing && (length != 0)) {
1073
1074
1075
1076
1077
1078 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
1079
1080 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1081 __func__, &ureq->dma, dma_reg);
1082 }
1083 }
1084
1085 if (hs_ep->isochronous && hs_ep->interval == 1) {
1086 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1087 dwc2_gadget_incr_frame_num(hs_ep);
1088
1089 if (hs_ep->target_frame & 0x1)
1090 ctrl |= DXEPCTL_SETODDFR;
1091 else
1092 ctrl |= DXEPCTL_SETEVENFR;
1093 }
1094
1095 ctrl |= DXEPCTL_EPENA;
1096
1097 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1098
1099
1100 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1101 ctrl |= DXEPCTL_CNAK;
1102
1103 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1104 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
1105
1106
1107
1108
1109
1110
1111 hs_ep->size_loaded = length;
1112 hs_ep->last_load = ureq->actual;
1113
1114 if (dir_in && !using_dma(hsotg)) {
1115
1116 hs_ep->fifo_load = 0;
1117
1118 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1119 }
1120
1121
1122
1123
1124
1125
1126
1127 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1128 dev_dbg(hsotg->dev,
1129 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1130 index, dwc2_readl(hsotg->regs + epctrl_reg));
1131
1132 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1133 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
1134
1135
1136 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1137}
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1152 struct dwc2_hsotg_ep *hs_ep,
1153 struct usb_request *req)
1154{
1155 int ret;
1156
1157 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1158 if (ret)
1159 goto dma_error;
1160
1161 return 0;
1162
1163dma_error:
1164 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1165 __func__, req->buf, req->length);
1166
1167 return -EIO;
1168}
1169
1170static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1171 struct dwc2_hsotg_ep *hs_ep,
1172 struct dwc2_hsotg_req *hs_req)
1173{
1174 void *req_buf = hs_req->req.buf;
1175
1176
1177 if (!using_dma(hsotg) || !((long)req_buf & 3))
1178 return 0;
1179
1180 WARN_ON(hs_req->saved_req_buf);
1181
1182 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1183 hs_ep->ep.name, req_buf, hs_req->req.length);
1184
1185 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1186 if (!hs_req->req.buf) {
1187 hs_req->req.buf = req_buf;
1188 dev_err(hsotg->dev,
1189 "%s: unable to allocate memory for bounce buffer\n",
1190 __func__);
1191 return -ENOMEM;
1192 }
1193
1194
1195 hs_req->saved_req_buf = req_buf;
1196
1197 if (hs_ep->dir_in)
1198 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1199 return 0;
1200}
1201
1202static void
1203dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1204 struct dwc2_hsotg_ep *hs_ep,
1205 struct dwc2_hsotg_req *hs_req)
1206{
1207
1208 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1209 return;
1210
1211 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1212 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1213
1214
1215 if (!hs_ep->dir_in && !hs_req->req.status)
1216 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1217 hs_req->req.actual);
1218
1219
1220 kfree(hs_req->req.buf);
1221
1222 hs_req->req.buf = hs_req->saved_req_buf;
1223 hs_req->saved_req_buf = NULL;
1224}
1225
1226
1227
1228
1229
1230
1231
1232
1233static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1234{
1235 struct dwc2_hsotg *hsotg = hs_ep->parent;
1236 u32 target_frame = hs_ep->target_frame;
1237 u32 current_frame = dwc2_hsotg_read_frameno(hsotg);
1238 bool frame_overrun = hs_ep->frame_overrun;
1239
1240 if (!frame_overrun && current_frame >= target_frame)
1241 return true;
1242
1243 if (frame_overrun && current_frame >= target_frame &&
1244 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1245 return true;
1246
1247 return false;
1248}
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1259 struct dwc2_hsotg_ep *hs_ep)
1260{
1261 switch (hsotg->ep0_state) {
1262 case DWC2_EP0_SETUP:
1263 case DWC2_EP0_STATUS_OUT:
1264 hs_ep->desc_list = hsotg->setup_desc[0];
1265 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1266 break;
1267 case DWC2_EP0_DATA_IN:
1268 case DWC2_EP0_STATUS_IN:
1269 hs_ep->desc_list = hsotg->ctrl_in_desc;
1270 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1271 break;
1272 case DWC2_EP0_DATA_OUT:
1273 hs_ep->desc_list = hsotg->ctrl_out_desc;
1274 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1275 break;
1276 default:
1277 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1278 hsotg->ep0_state);
1279 return -EINVAL;
1280 }
1281
1282 return 0;
1283}
1284
1285static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1286 gfp_t gfp_flags)
1287{
1288 struct dwc2_hsotg_req *hs_req = our_req(req);
1289 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1290 struct dwc2_hsotg *hs = hs_ep->parent;
1291 bool first;
1292 int ret;
1293
1294 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1295 ep->name, req, req->length, req->buf, req->no_interrupt,
1296 req->zero, req->short_not_ok);
1297
1298
1299 if (hs->lx_state == DWC2_L2) {
1300 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
1301 __func__);
1302 return -EAGAIN;
1303 }
1304
1305
1306 INIT_LIST_HEAD(&hs_req->queue);
1307 req->actual = 0;
1308 req->status = -EINPROGRESS;
1309
1310 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1311 if (ret)
1312 return ret;
1313
1314
1315 if (using_dma(hs)) {
1316 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1317 if (ret)
1318 return ret;
1319 }
1320
1321 if (using_desc_dma(hs) && !hs_ep->index) {
1322 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1323 if (ret)
1324 return ret;
1325 }
1326
1327 first = list_empty(&hs_ep->queue);
1328 list_add_tail(&hs_req->queue, &hs_ep->queue);
1329
1330
1331
1332
1333
1334
1335
1336 if (using_desc_dma(hs) && hs_ep->isochronous &&
1337 hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1338 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1339 hs_req->req.length);
1340 if (ret)
1341 dev_dbg(hs->dev, "%s: ISO desc chain full\n", __func__);
1342
1343 return 0;
1344 }
1345
1346 if (first) {
1347 if (!hs_ep->isochronous) {
1348 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1349 return 0;
1350 }
1351
1352 while (dwc2_gadget_target_frame_elapsed(hs_ep))
1353 dwc2_gadget_incr_frame_num(hs_ep);
1354
1355 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1356 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1357 }
1358 return 0;
1359}
1360
1361static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1362 gfp_t gfp_flags)
1363{
1364 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1365 struct dwc2_hsotg *hs = hs_ep->parent;
1366 unsigned long flags = 0;
1367 int ret = 0;
1368
1369 spin_lock_irqsave(&hs->lock, flags);
1370 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1371 spin_unlock_irqrestore(&hs->lock, flags);
1372
1373 return ret;
1374}
1375
1376static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1377 struct usb_request *req)
1378{
1379 struct dwc2_hsotg_req *hs_req = our_req(req);
1380
1381 kfree(hs_req);
1382}
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1393 struct usb_request *req)
1394{
1395 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1396 struct dwc2_hsotg *hsotg = hs_ep->parent;
1397
1398 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1399
1400 dwc2_hsotg_ep_free_request(ep, req);
1401}
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1412 u32 windex)
1413{
1414 struct dwc2_hsotg_ep *ep;
1415 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1416 int idx = windex & 0x7F;
1417
1418 if (windex >= 0x100)
1419 return NULL;
1420
1421 if (idx > hsotg->num_of_eps)
1422 return NULL;
1423
1424 ep = index_to_ep(hsotg, idx, dir);
1425
1426 if (idx && ep->dir_in != dir)
1427 return NULL;
1428
1429 return ep;
1430}
1431
1432
1433
1434
1435
1436
1437
1438int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1439{
1440 int dctl = dwc2_readl(hsotg->regs + DCTL);
1441
1442 dctl &= ~DCTL_TSTCTL_MASK;
1443 switch (testmode) {
1444 case TEST_J:
1445 case TEST_K:
1446 case TEST_SE0_NAK:
1447 case TEST_PACKET:
1448 case TEST_FORCE_EN:
1449 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1450 break;
1451 default:
1452 return -EINVAL;
1453 }
1454 dwc2_writel(dctl, hsotg->regs + DCTL);
1455 return 0;
1456}
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1469 struct dwc2_hsotg_ep *ep,
1470 void *buff,
1471 int length)
1472{
1473 struct usb_request *req;
1474 int ret;
1475
1476 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1477
1478 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1479 hsotg->ep0_reply = req;
1480 if (!req) {
1481 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1482 return -ENOMEM;
1483 }
1484
1485 req->buf = hsotg->ep0_buff;
1486 req->length = length;
1487
1488
1489
1490
1491 req->zero = 0;
1492 req->complete = dwc2_hsotg_complete_oursetup;
1493
1494 if (length)
1495 memcpy(req->buf, buff, length);
1496
1497 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1498 if (ret) {
1499 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1500 return ret;
1501 }
1502
1503 return 0;
1504}
1505
1506
1507
1508
1509
1510
1511static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1512 struct usb_ctrlrequest *ctrl)
1513{
1514 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1515 struct dwc2_hsotg_ep *ep;
1516 __le16 reply;
1517 int ret;
1518
1519 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1520
1521 if (!ep0->dir_in) {
1522 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1523 return -EINVAL;
1524 }
1525
1526 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1527 case USB_RECIP_DEVICE:
1528
1529
1530
1531
1532 reply = cpu_to_le16(0);
1533 break;
1534
1535 case USB_RECIP_INTERFACE:
1536
1537 reply = cpu_to_le16(0);
1538 break;
1539
1540 case USB_RECIP_ENDPOINT:
1541 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1542 if (!ep)
1543 return -ENOENT;
1544
1545 reply = cpu_to_le16(ep->halted ? 1 : 0);
1546 break;
1547
1548 default:
1549 return 0;
1550 }
1551
1552 if (le16_to_cpu(ctrl->wLength) != 2)
1553 return -EINVAL;
1554
1555 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1556 if (ret) {
1557 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1558 return ret;
1559 }
1560
1561 return 1;
1562}
1563
1564static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1565
1566
1567
1568
1569
1570
1571
1572static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1573{
1574 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1575 queue);
1576}
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1587{
1588 u32 mask;
1589 struct dwc2_hsotg *hsotg = hs_ep->parent;
1590 int dir_in = hs_ep->dir_in;
1591 struct dwc2_hsotg_req *hs_req;
1592 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1593
1594 if (!list_empty(&hs_ep->queue)) {
1595 hs_req = get_ep_head(hs_ep);
1596 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1597 return;
1598 }
1599 if (!hs_ep->isochronous)
1600 return;
1601
1602 if (dir_in) {
1603 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1604 __func__);
1605 } else {
1606 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1607 __func__);
1608 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1609 mask |= DOEPMSK_OUTTKNEPDISMSK;
1610 dwc2_writel(mask, hsotg->regs + epmsk_reg);
1611 }
1612}
1613
1614
1615
1616
1617
1618
1619static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1620 struct usb_ctrlrequest *ctrl)
1621{
1622 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1623 struct dwc2_hsotg_req *hs_req;
1624 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1625 struct dwc2_hsotg_ep *ep;
1626 int ret;
1627 bool halted;
1628 u32 recip;
1629 u32 wValue;
1630 u32 wIndex;
1631
1632 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1633 __func__, set ? "SET" : "CLEAR");
1634
1635 wValue = le16_to_cpu(ctrl->wValue);
1636 wIndex = le16_to_cpu(ctrl->wIndex);
1637 recip = ctrl->bRequestType & USB_RECIP_MASK;
1638
1639 switch (recip) {
1640 case USB_RECIP_DEVICE:
1641 switch (wValue) {
1642 case USB_DEVICE_TEST_MODE:
1643 if ((wIndex & 0xff) != 0)
1644 return -EINVAL;
1645 if (!set)
1646 return -EINVAL;
1647
1648 hsotg->test_mode = wIndex >> 8;
1649 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1650 if (ret) {
1651 dev_err(hsotg->dev,
1652 "%s: failed to send reply\n", __func__);
1653 return ret;
1654 }
1655 break;
1656 default:
1657 return -ENOENT;
1658 }
1659 break;
1660
1661 case USB_RECIP_ENDPOINT:
1662 ep = ep_from_windex(hsotg, wIndex);
1663 if (!ep) {
1664 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1665 __func__, wIndex);
1666 return -ENOENT;
1667 }
1668
1669 switch (wValue) {
1670 case USB_ENDPOINT_HALT:
1671 halted = ep->halted;
1672
1673 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1674
1675 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1676 if (ret) {
1677 dev_err(hsotg->dev,
1678 "%s: failed to send reply\n", __func__);
1679 return ret;
1680 }
1681
1682
1683
1684
1685
1686
1687 if (!set && halted) {
1688
1689
1690
1691
1692 if (ep->req) {
1693 hs_req = ep->req;
1694 ep->req = NULL;
1695 list_del_init(&hs_req->queue);
1696 if (hs_req->req.complete) {
1697 spin_unlock(&hsotg->lock);
1698 usb_gadget_giveback_request(
1699 &ep->ep, &hs_req->req);
1700 spin_lock(&hsotg->lock);
1701 }
1702 }
1703
1704
1705 if (!ep->req)
1706 dwc2_gadget_start_next_request(ep);
1707 }
1708
1709 break;
1710
1711 default:
1712 return -ENOENT;
1713 }
1714 break;
1715 default:
1716 return -ENOENT;
1717 }
1718 return 1;
1719}
1720
1721static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1722
1723
1724
1725
1726
1727
1728
1729static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1730{
1731 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1732 u32 reg;
1733 u32 ctrl;
1734
1735 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1736 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1737
1738
1739
1740
1741
1742
1743 ctrl = dwc2_readl(hsotg->regs + reg);
1744 ctrl |= DXEPCTL_STALL;
1745 ctrl |= DXEPCTL_CNAK;
1746 dwc2_writel(ctrl, hsotg->regs + reg);
1747
1748 dev_dbg(hsotg->dev,
1749 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1750 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1751
1752
1753
1754
1755
1756 dwc2_hsotg_enqueue_setup(hsotg);
1757}
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1769 struct usb_ctrlrequest *ctrl)
1770{
1771 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1772 int ret = 0;
1773 u32 dcfg;
1774
1775 dev_dbg(hsotg->dev,
1776 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1777 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1778 ctrl->wIndex, ctrl->wLength);
1779
1780 if (ctrl->wLength == 0) {
1781 ep0->dir_in = 1;
1782 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1783 } else if (ctrl->bRequestType & USB_DIR_IN) {
1784 ep0->dir_in = 1;
1785 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1786 } else {
1787 ep0->dir_in = 0;
1788 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1789 }
1790
1791 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1792 switch (ctrl->bRequest) {
1793 case USB_REQ_SET_ADDRESS:
1794 hsotg->connected = 1;
1795 dcfg = dwc2_readl(hsotg->regs + DCFG);
1796 dcfg &= ~DCFG_DEVADDR_MASK;
1797 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1798 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1799 dwc2_writel(dcfg, hsotg->regs + DCFG);
1800
1801 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1802
1803 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1804 return;
1805
1806 case USB_REQ_GET_STATUS:
1807 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1808 break;
1809
1810 case USB_REQ_CLEAR_FEATURE:
1811 case USB_REQ_SET_FEATURE:
1812 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1813 break;
1814 }
1815 }
1816
1817
1818
1819 if (ret == 0 && hsotg->driver) {
1820 spin_unlock(&hsotg->lock);
1821 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1822 spin_lock(&hsotg->lock);
1823 if (ret < 0)
1824 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1825 }
1826
1827
1828
1829
1830
1831
1832 if (ret < 0)
1833 dwc2_hsotg_stall_ep0(hsotg);
1834}
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1845 struct usb_request *req)
1846{
1847 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1848 struct dwc2_hsotg *hsotg = hs_ep->parent;
1849
1850 if (req->status < 0) {
1851 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1852 return;
1853 }
1854
1855 spin_lock(&hsotg->lock);
1856 if (req->actual == 0)
1857 dwc2_hsotg_enqueue_setup(hsotg);
1858 else
1859 dwc2_hsotg_process_control(hsotg, req->buf);
1860 spin_unlock(&hsotg->lock);
1861}
1862
1863
1864
1865
1866
1867
1868
1869
1870static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1871{
1872 struct usb_request *req = hsotg->ctrl_req;
1873 struct dwc2_hsotg_req *hs_req = our_req(req);
1874 int ret;
1875
1876 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1877
1878 req->zero = 0;
1879 req->length = 8;
1880 req->buf = hsotg->ctrl_buff;
1881 req->complete = dwc2_hsotg_complete_setup;
1882
1883 if (!list_empty(&hs_req->queue)) {
1884 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1885 return;
1886 }
1887
1888 hsotg->eps_out[0]->dir_in = 0;
1889 hsotg->eps_out[0]->send_zlp = 0;
1890 hsotg->ep0_state = DWC2_EP0_SETUP;
1891
1892 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1893 if (ret < 0) {
1894 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1895
1896
1897
1898
1899 }
1900}
1901
1902static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1903 struct dwc2_hsotg_ep *hs_ep)
1904{
1905 u32 ctrl;
1906 u8 index = hs_ep->index;
1907 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1908 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1909
1910 if (hs_ep->dir_in)
1911 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1912 index);
1913 else
1914 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1915 index);
1916 if (using_desc_dma(hsotg)) {
1917
1918 dma_addr_t dma = hs_ep->desc_list_dma;
1919
1920 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
1921 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1922 } else {
1923 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1924 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1925 epsiz_reg);
1926 }
1927
1928 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1929 ctrl |= DXEPCTL_CNAK;
1930 ctrl |= DXEPCTL_EPENA;
1931 ctrl |= DXEPCTL_USBACTEP;
1932 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1933}
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1949 struct dwc2_hsotg_ep *hs_ep,
1950 struct dwc2_hsotg_req *hs_req,
1951 int result)
1952{
1953 if (!hs_req) {
1954 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1955 return;
1956 }
1957
1958 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1959 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1960
1961
1962
1963
1964
1965
1966 if (hs_req->req.status == -EINPROGRESS)
1967 hs_req->req.status = result;
1968
1969 if (using_dma(hsotg))
1970 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1971
1972 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1973
1974 hs_ep->req = NULL;
1975 list_del_init(&hs_req->queue);
1976
1977
1978
1979
1980
1981
1982 if (hs_req->req.complete) {
1983 spin_unlock(&hsotg->lock);
1984 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1985 spin_lock(&hsotg->lock);
1986 }
1987
1988
1989 if (using_desc_dma(hsotg) && hs_ep->isochronous)
1990 return;
1991
1992
1993
1994
1995
1996
1997
1998 if (!hs_ep->req && result >= 0)
1999 dwc2_gadget_start_next_request(hs_ep);
2000}
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2013{
2014 struct dwc2_hsotg *hsotg = hs_ep->parent;
2015 struct dwc2_hsotg_req *hs_req;
2016 struct usb_request *ureq;
2017 int index;
2018 dma_addr_t dma_addr;
2019 u32 dma_reg;
2020 u32 depdma;
2021 u32 desc_sts;
2022 u32 mask;
2023
2024 hs_req = get_ep_head(hs_ep);
2025 if (!hs_req) {
2026 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2027 return;
2028 }
2029 ureq = &hs_req->req;
2030
2031 dma_addr = hs_ep->desc_list_dma;
2032
2033
2034
2035
2036
2037
2038 if (!hs_ep->isoc_chain_num)
2039 dma_addr += sizeof(struct dwc2_dma_desc) *
2040 (MAX_DMA_DESC_NUM_GENERIC / 2);
2041
2042 dma_reg = hs_ep->dir_in ? DIEPDMA(hs_ep->index) : DOEPDMA(hs_ep->index);
2043 depdma = dwc2_readl(hsotg->regs + dma_reg);
2044
2045 index = (depdma - dma_addr) / sizeof(struct dwc2_dma_desc) - 1;
2046 desc_sts = hs_ep->desc_list[index].status;
2047
2048 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2049 DEV_DMA_ISOC_RX_NBYTES_MASK;
2050 ureq->actual = ureq->length -
2051 ((desc_sts & mask) >> DEV_DMA_ISOC_NBYTES_SHIFT);
2052
2053
2054 if (!hs_ep->dir_in && ureq->length & 0x3)
2055 ureq->actual += 4 - (ureq->length & 0x3);
2056
2057 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2058}
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
2069{
2070 struct dwc2_hsotg *hsotg = hs_ep->parent;
2071 u32 depctl;
2072 u32 dma_reg;
2073 u32 ctrl;
2074 u32 dma_addr = hs_ep->desc_list_dma;
2075 unsigned char index = hs_ep->index;
2076
2077 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
2078 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2079
2080 ctrl = dwc2_readl(hsotg->regs + depctl);
2081
2082
2083
2084
2085
2086
2087 if (!(ctrl & DXEPCTL_EPENA)) {
2088 if (!hs_ep->next_desc) {
2089 dev_dbg(hsotg->dev, "%s: No more ISOC requests\n",
2090 __func__);
2091 return;
2092 }
2093
2094 dma_addr += sizeof(struct dwc2_dma_desc) *
2095 (MAX_DMA_DESC_NUM_GENERIC / 2) *
2096 hs_ep->isoc_chain_num;
2097 dwc2_writel(dma_addr, hsotg->regs + dma_reg);
2098
2099 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
2100 dwc2_writel(ctrl, hsotg->regs + depctl);
2101
2102
2103 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
2104 hs_ep->next_desc = 0;
2105
2106 dev_dbg(hsotg->dev, "%s: Restarted isochronous endpoint\n",
2107 __func__);
2108 }
2109}
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2122{
2123 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2124 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2125 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
2126 int to_read;
2127 int max_req;
2128 int read_ptr;
2129
2130 if (!hs_req) {
2131 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
2132 int ptr;
2133
2134 dev_dbg(hsotg->dev,
2135 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2136 __func__, size, ep_idx, epctl);
2137
2138
2139 for (ptr = 0; ptr < size; ptr += 4)
2140 (void)dwc2_readl(fifo);
2141
2142 return;
2143 }
2144
2145 to_read = size;
2146 read_ptr = hs_req->req.actual;
2147 max_req = hs_req->req.length - read_ptr;
2148
2149 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2150 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2151
2152 if (to_read > max_req) {
2153
2154
2155
2156
2157
2158
2159 WARN_ON_ONCE(1);
2160 }
2161
2162 hs_ep->total_data += to_read;
2163 hs_req->req.actual += to_read;
2164 to_read = DIV_ROUND_UP(to_read, 4);
2165
2166
2167
2168
2169
2170 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
2171}
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2186{
2187
2188 hsotg->eps_out[0]->dir_in = dir_in;
2189 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2190
2191 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2192}
2193
2194static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2195 u32 epctl_reg)
2196{
2197 u32 ctrl;
2198
2199 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2200 if (ctrl & DXEPCTL_EOFRNUM)
2201 ctrl |= DXEPCTL_SETEVENFR;
2202 else
2203 ctrl |= DXEPCTL_SETODDFR;
2204 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
2205}
2206
2207
2208
2209
2210
2211
2212
2213
2214static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2215{
2216 struct dwc2_hsotg *hsotg = hs_ep->parent;
2217 unsigned int bytes_rem = 0;
2218 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2219 int i;
2220 u32 status;
2221
2222 if (!desc)
2223 return -EINVAL;
2224
2225 for (i = 0; i < hs_ep->desc_count; ++i) {
2226 status = desc->status;
2227 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2228
2229 if (status & DEV_DMA_STS_MASK)
2230 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2231 i, status & DEV_DMA_STS_MASK);
2232 }
2233
2234 return bytes_rem;
2235}
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2247{
2248 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
2249 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2250 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2251 struct usb_request *req = &hs_req->req;
2252 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2253 int result = 0;
2254
2255 if (!hs_req) {
2256 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2257 return;
2258 }
2259
2260 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2261 dev_dbg(hsotg->dev, "zlp packet received\n");
2262 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2263 dwc2_hsotg_enqueue_setup(hsotg);
2264 return;
2265 }
2266
2267 if (using_desc_dma(hsotg))
2268 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2269
2270 if (using_dma(hsotg)) {
2271 unsigned int size_done;
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282 size_done = hs_ep->size_loaded - size_left;
2283 size_done += hs_ep->last_load;
2284
2285 req->actual = size_done;
2286 }
2287
2288
2289 if (req->actual < req->length && size_left == 0) {
2290 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2291 return;
2292 }
2293
2294 if (req->actual < req->length && req->short_not_ok) {
2295 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2296 __func__, req->actual, req->length);
2297
2298
2299
2300
2301
2302 }
2303
2304
2305 if (!using_desc_dma(hsotg) && epnum == 0 &&
2306 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2307
2308 dwc2_hsotg_ep0_zlp(hsotg, true);
2309 return;
2310 }
2311
2312
2313
2314
2315
2316 if (!using_dma(hsotg)) {
2317 if (hs_ep->isochronous && hs_ep->interval == 1)
2318 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2319 else if (hs_ep->isochronous && hs_ep->interval > 1)
2320 dwc2_gadget_incr_frame_num(hs_ep);
2321 }
2322
2323 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2324}
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2343{
2344 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
2345 u32 epnum, status, size;
2346
2347 WARN_ON(using_dma(hsotg));
2348
2349 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2350 status = grxstsr & GRXSTS_PKTSTS_MASK;
2351
2352 size = grxstsr & GRXSTS_BYTECNT_MASK;
2353 size >>= GRXSTS_BYTECNT_SHIFT;
2354
2355 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2356 __func__, grxstsr, size, epnum);
2357
2358 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2359 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2360 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2361 break;
2362
2363 case GRXSTS_PKTSTS_OUTDONE:
2364 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2365 dwc2_hsotg_read_frameno(hsotg));
2366
2367 if (!using_dma(hsotg))
2368 dwc2_hsotg_handle_outdone(hsotg, epnum);
2369 break;
2370
2371 case GRXSTS_PKTSTS_SETUPDONE:
2372 dev_dbg(hsotg->dev,
2373 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2374 dwc2_hsotg_read_frameno(hsotg),
2375 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2376
2377
2378
2379
2380
2381 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2382 dwc2_hsotg_handle_outdone(hsotg, epnum);
2383 break;
2384
2385 case GRXSTS_PKTSTS_OUTRX:
2386 dwc2_hsotg_rx_data(hsotg, epnum, size);
2387 break;
2388
2389 case GRXSTS_PKTSTS_SETUPRX:
2390 dev_dbg(hsotg->dev,
2391 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2392 dwc2_hsotg_read_frameno(hsotg),
2393 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2394
2395 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2396
2397 dwc2_hsotg_rx_data(hsotg, epnum, size);
2398 break;
2399
2400 default:
2401 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2402 __func__, grxstsr);
2403
2404 dwc2_hsotg_dump(hsotg);
2405 break;
2406 }
2407}
2408
2409
2410
2411
2412
2413static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2414{
2415 switch (mps) {
2416 case 64:
2417 return D0EPCTL_MPS_64;
2418 case 32:
2419 return D0EPCTL_MPS_32;
2420 case 16:
2421 return D0EPCTL_MPS_16;
2422 case 8:
2423 return D0EPCTL_MPS_8;
2424 }
2425
2426
2427 WARN_ON(1);
2428 return (u32)-1;
2429}
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2442 unsigned int ep, unsigned int mps,
2443 unsigned int mc, unsigned int dir_in)
2444{
2445 struct dwc2_hsotg_ep *hs_ep;
2446 void __iomem *regs = hsotg->regs;
2447 u32 reg;
2448
2449 hs_ep = index_to_ep(hsotg, ep, dir_in);
2450 if (!hs_ep)
2451 return;
2452
2453 if (ep == 0) {
2454 u32 mps_bytes = mps;
2455
2456
2457 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2458 if (mps > 3)
2459 goto bad_mps;
2460 hs_ep->ep.maxpacket = mps_bytes;
2461 hs_ep->mc = 1;
2462 } else {
2463 if (mps > 1024)
2464 goto bad_mps;
2465 hs_ep->mc = mc;
2466 if (mc > 3)
2467 goto bad_mps;
2468 hs_ep->ep.maxpacket = mps;
2469 }
2470
2471 if (dir_in) {
2472 reg = dwc2_readl(regs + DIEPCTL(ep));
2473 reg &= ~DXEPCTL_MPS_MASK;
2474 reg |= mps;
2475 dwc2_writel(reg, regs + DIEPCTL(ep));
2476 } else {
2477 reg = dwc2_readl(regs + DOEPCTL(ep));
2478 reg &= ~DXEPCTL_MPS_MASK;
2479 reg |= mps;
2480 dwc2_writel(reg, regs + DOEPCTL(ep));
2481 }
2482
2483 return;
2484
2485bad_mps:
2486 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2487}
2488
2489
2490
2491
2492
2493
2494static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2495{
2496 int timeout;
2497 int val;
2498
2499 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2500 hsotg->regs + GRSTCTL);
2501
2502
2503 timeout = 100;
2504
2505 while (1) {
2506 val = dwc2_readl(hsotg->regs + GRSTCTL);
2507
2508 if ((val & (GRSTCTL_TXFFLSH)) == 0)
2509 break;
2510
2511 if (--timeout == 0) {
2512 dev_err(hsotg->dev,
2513 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
2514 __func__, val);
2515 break;
2516 }
2517
2518 udelay(1);
2519 }
2520}
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2531 struct dwc2_hsotg_ep *hs_ep)
2532{
2533 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2534
2535 if (!hs_ep->dir_in || !hs_req) {
2536
2537
2538
2539
2540 if (hs_ep->index != 0)
2541 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2542 hs_ep->dir_in, 0);
2543 return 0;
2544 }
2545
2546 if (hs_req->req.actual < hs_req->req.length) {
2547 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2548 hs_ep->index);
2549 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2550 }
2551
2552 return 0;
2553}
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2564 struct dwc2_hsotg_ep *hs_ep)
2565{
2566 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2567 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
2568 int size_left, size_done;
2569
2570 if (!hs_req) {
2571 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2572 return;
2573 }
2574
2575
2576 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2577 dev_dbg(hsotg->dev, "zlp packet sent\n");
2578
2579
2580
2581
2582
2583 hs_ep->dir_in = 0;
2584
2585 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2586 if (hsotg->test_mode) {
2587 int ret;
2588
2589 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2590 if (ret < 0) {
2591 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2592 hsotg->test_mode);
2593 dwc2_hsotg_stall_ep0(hsotg);
2594 return;
2595 }
2596 }
2597 dwc2_hsotg_enqueue_setup(hsotg);
2598 return;
2599 }
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610 if (using_desc_dma(hsotg)) {
2611 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2612 if (size_left < 0)
2613 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2614 size_left);
2615 } else {
2616 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2617 }
2618
2619 size_done = hs_ep->size_loaded - size_left;
2620 size_done += hs_ep->last_load;
2621
2622 if (hs_req->req.actual != size_done)
2623 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2624 __func__, hs_req->req.actual, size_done);
2625
2626 hs_req->req.actual = size_done;
2627 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2628 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2629
2630 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2631 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2632 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2633 return;
2634 }
2635
2636
2637 if (hs_ep->send_zlp) {
2638 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2639 hs_ep->send_zlp = 0;
2640
2641 return;
2642 }
2643
2644 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2645
2646 dwc2_hsotg_ep0_zlp(hsotg, false);
2647 return;
2648 }
2649
2650 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2651}
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2663 unsigned int idx, int dir_in)
2664{
2665 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2666 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2667 u32 ints;
2668 u32 mask;
2669 u32 diepempmsk;
2670
2671 mask = dwc2_readl(hsotg->regs + epmsk_reg);
2672 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK);
2673 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2674 mask |= DXEPINT_SETUP_RCVD;
2675
2676 ints = dwc2_readl(hsotg->regs + epint_reg);
2677 ints &= mask;
2678 return ints;
2679}
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2695{
2696 struct dwc2_hsotg *hsotg = hs_ep->parent;
2697 struct dwc2_hsotg_req *hs_req;
2698 unsigned char idx = hs_ep->index;
2699 int dir_in = hs_ep->dir_in;
2700 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2701 int dctl = dwc2_readl(hsotg->regs + DCTL);
2702
2703 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2704
2705 if (dir_in) {
2706 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2707
2708 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2709
2710 if (hs_ep->isochronous) {
2711 dwc2_hsotg_complete_in(hsotg, hs_ep);
2712 return;
2713 }
2714
2715 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2716 int dctl = dwc2_readl(hsotg->regs + DCTL);
2717
2718 dctl |= DCTL_CGNPINNAK;
2719 dwc2_writel(dctl, hsotg->regs + DCTL);
2720 }
2721 return;
2722 }
2723
2724 if (dctl & DCTL_GOUTNAKSTS) {
2725 dctl |= DCTL_CGOUTNAK;
2726 dwc2_writel(dctl, hsotg->regs + DCTL);
2727 }
2728
2729 if (!hs_ep->isochronous)
2730 return;
2731
2732 if (list_empty(&hs_ep->queue)) {
2733 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2734 __func__, hs_ep);
2735 return;
2736 }
2737
2738 do {
2739 hs_req = get_ep_head(hs_ep);
2740 if (hs_req)
2741 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2742 -ENODATA);
2743 dwc2_gadget_incr_frame_num(hs_ep);
2744 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2745
2746 dwc2_gadget_start_next_request(hs_ep);
2747}
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2761{
2762 struct dwc2_hsotg *hsotg = ep->parent;
2763 int dir_in = ep->dir_in;
2764 u32 doepmsk;
2765 u32 tmp;
2766
2767 if (dir_in || !ep->isochronous)
2768 return;
2769
2770
2771
2772
2773
2774 tmp = dwc2_hsotg_read_frameno(hsotg);
2775
2776 dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA);
2777
2778 if (using_desc_dma(hsotg)) {
2779 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2780
2781 ep->target_frame = tmp;
2782 dwc2_gadget_start_isoc_ddma(ep);
2783 }
2784 return;
2785 }
2786
2787 if (ep->interval > 1 &&
2788 ep->target_frame == TARGET_FRAME_INITIAL) {
2789 u32 dsts;
2790 u32 ctrl;
2791
2792 dsts = dwc2_readl(hsotg->regs + DSTS);
2793 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2794 dwc2_gadget_incr_frame_num(ep);
2795
2796 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index));
2797 if (ep->target_frame & 0x1)
2798 ctrl |= DXEPCTL_SETODDFR;
2799 else
2800 ctrl |= DXEPCTL_SETEVENFR;
2801
2802 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index));
2803 }
2804
2805 dwc2_gadget_start_next_request(ep);
2806 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
2807 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2808 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK);
2809}
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2826{
2827 struct dwc2_hsotg *hsotg = hs_ep->parent;
2828 int dir_in = hs_ep->dir_in;
2829
2830 if (!dir_in || !hs_ep->isochronous)
2831 return;
2832
2833 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2834 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2835
2836 if (using_desc_dma(hsotg)) {
2837 dwc2_gadget_start_isoc_ddma(hs_ep);
2838 return;
2839 }
2840
2841 if (hs_ep->interval > 1) {
2842 u32 ctrl = dwc2_readl(hsotg->regs +
2843 DIEPCTL(hs_ep->index));
2844 if (hs_ep->target_frame & 0x1)
2845 ctrl |= DXEPCTL_SETODDFR;
2846 else
2847 ctrl |= DXEPCTL_SETEVENFR;
2848
2849 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index));
2850 }
2851
2852 dwc2_hsotg_complete_request(hsotg, hs_ep,
2853 get_ep_head(hs_ep), 0);
2854 }
2855
2856 dwc2_gadget_incr_frame_num(hs_ep);
2857}
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2868 int dir_in)
2869{
2870 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2871 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2872 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2873 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2874 u32 ints;
2875 u32 ctrl;
2876
2877 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2878 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2879
2880
2881 dwc2_writel(ints, hsotg->regs + epint_reg);
2882
2883 if (!hs_ep) {
2884 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2885 __func__, idx, dir_in ? "in" : "out");
2886 return;
2887 }
2888
2889 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2890 __func__, idx, dir_in ? "in" : "out", ints);
2891
2892
2893 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2894 ints &= ~DXEPINT_XFERCOMPL;
2895
2896
2897
2898
2899
2900
2901
2902 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
2903 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
2904 ints &= ~DXEPINT_XFERCOMPL;
2905
2906 if (ints & DXEPINT_XFERCOMPL) {
2907 dev_dbg(hsotg->dev,
2908 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2909 __func__, dwc2_readl(hsotg->regs + epctl_reg),
2910 dwc2_readl(hsotg->regs + epsiz_reg));
2911
2912
2913 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
2914 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
2915
2916 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2917 } else if (dir_in) {
2918
2919
2920
2921
2922
2923 if (hs_ep->isochronous && hs_ep->interval > 1)
2924 dwc2_gadget_incr_frame_num(hs_ep);
2925
2926 dwc2_hsotg_complete_in(hsotg, hs_ep);
2927 if (ints & DXEPINT_NAKINTRPT)
2928 ints &= ~DXEPINT_NAKINTRPT;
2929
2930 if (idx == 0 && !hs_ep->req)
2931 dwc2_hsotg_enqueue_setup(hsotg);
2932 } else if (using_dma(hsotg)) {
2933
2934
2935
2936
2937 if (hs_ep->isochronous && hs_ep->interval > 1)
2938 dwc2_gadget_incr_frame_num(hs_ep);
2939
2940 dwc2_hsotg_handle_outdone(hsotg, idx);
2941 }
2942 }
2943
2944 if (ints & DXEPINT_EPDISBLD)
2945 dwc2_gadget_handle_ep_disabled(hs_ep);
2946
2947 if (ints & DXEPINT_OUTTKNEPDIS)
2948 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
2949
2950 if (ints & DXEPINT_NAKINTRPT)
2951 dwc2_gadget_handle_nak(hs_ep);
2952
2953 if (ints & DXEPINT_AHBERR)
2954 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2955
2956 if (ints & DXEPINT_SETUP) {
2957 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2958
2959 if (using_dma(hsotg) && idx == 0) {
2960
2961
2962
2963
2964
2965
2966
2967 if (dir_in)
2968 WARN_ON_ONCE(1);
2969 else
2970 dwc2_hsotg_handle_outdone(hsotg, 0);
2971 }
2972 }
2973
2974 if (ints & DXEPINT_STSPHSERCVD) {
2975 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
2976
2977
2978 if (using_desc_dma(hsotg))
2979 dwc2_hsotg_ep0_zlp(hsotg, true);
2980 }
2981
2982 if (ints & DXEPINT_BACK2BACKSETUP)
2983 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2984
2985 if (ints & DXEPINT_BNAINTR) {
2986 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
2987
2988
2989
2990
2991
2992
2993
2994 if (hs_ep->isochronous)
2995 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2996 }
2997
2998 if (dir_in && !hs_ep->isochronous) {
2999
3000 if (ints & DXEPINT_INTKNTXFEMP) {
3001 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3002 __func__, idx);
3003 }
3004
3005
3006 if (ints & DXEPINT_INTKNEPMIS) {
3007 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3008 __func__, idx);
3009 }
3010
3011
3012 if (hsotg->dedicated_fifos &&
3013 ints & DXEPINT_TXFEMP) {
3014 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3015 __func__, idx);
3016 if (!using_dma(hsotg))
3017 dwc2_hsotg_trytx(hsotg, hs_ep);
3018 }
3019 }
3020}
3021
3022
3023
3024
3025
3026
3027
3028
3029static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3030{
3031 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
3032 int ep0_mps = 0, ep_mps = 8;
3033
3034
3035
3036
3037
3038
3039
3040 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3041
3042
3043
3044
3045
3046
3047
3048
3049 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3050 case DSTS_ENUMSPD_FS:
3051 case DSTS_ENUMSPD_FS48:
3052 hsotg->gadget.speed = USB_SPEED_FULL;
3053 ep0_mps = EP0_MPS_LIMIT;
3054 ep_mps = 1023;
3055 break;
3056
3057 case DSTS_ENUMSPD_HS:
3058 hsotg->gadget.speed = USB_SPEED_HIGH;
3059 ep0_mps = EP0_MPS_LIMIT;
3060 ep_mps = 1024;
3061 break;
3062
3063 case DSTS_ENUMSPD_LS:
3064 hsotg->gadget.speed = USB_SPEED_LOW;
3065 ep0_mps = 8;
3066 ep_mps = 8;
3067
3068
3069
3070
3071
3072 break;
3073 }
3074 dev_info(hsotg->dev, "new device is %s\n",
3075 usb_speed_string(hsotg->gadget.speed));
3076
3077
3078
3079
3080
3081
3082 if (ep0_mps) {
3083 int i;
3084
3085 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3086 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3087 for (i = 1; i < hsotg->num_of_eps; i++) {
3088 if (hsotg->eps_in[i])
3089 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3090 0, 1);
3091 if (hsotg->eps_out[i])
3092 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3093 0, 0);
3094 }
3095 }
3096
3097
3098
3099 dwc2_hsotg_enqueue_setup(hsotg);
3100
3101 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3102 dwc2_readl(hsotg->regs + DIEPCTL0),
3103 dwc2_readl(hsotg->regs + DOEPCTL0));
3104}
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115static void kill_all_requests(struct dwc2_hsotg *hsotg,
3116 struct dwc2_hsotg_ep *ep,
3117 int result)
3118{
3119 struct dwc2_hsotg_req *req, *treq;
3120 unsigned int size;
3121
3122 ep->req = NULL;
3123
3124 list_for_each_entry_safe(req, treq, &ep->queue, queue)
3125 dwc2_hsotg_complete_request(hsotg, ep, req,
3126 result);
3127
3128 if (!hsotg->dedicated_fifos)
3129 return;
3130 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3131 if (size < ep->fifo_size)
3132 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3133}
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3144{
3145 unsigned int ep;
3146
3147 if (!hsotg->connected)
3148 return;
3149
3150 hsotg->connected = 0;
3151 hsotg->test_mode = 0;
3152
3153 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3154 if (hsotg->eps_in[ep])
3155 kill_all_requests(hsotg, hsotg->eps_in[ep],
3156 -ESHUTDOWN);
3157 if (hsotg->eps_out[ep])
3158 kill_all_requests(hsotg, hsotg->eps_out[ep],
3159 -ESHUTDOWN);
3160 }
3161
3162 call_gadget(hsotg, disconnect);
3163 hsotg->lx_state = DWC2_L3;
3164
3165 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3166}
3167
3168
3169
3170
3171
3172
3173static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3174{
3175 struct dwc2_hsotg_ep *ep;
3176 int epno, ret;
3177
3178
3179 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3180 ep = index_to_ep(hsotg, epno, 1);
3181
3182 if (!ep)
3183 continue;
3184
3185 if (!ep->dir_in)
3186 continue;
3187
3188 if ((periodic && !ep->periodic) ||
3189 (!periodic && ep->periodic))
3190 continue;
3191
3192 ret = dwc2_hsotg_trytx(hsotg, ep);
3193 if (ret < 0)
3194 break;
3195 }
3196}
3197
3198
3199#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3200 GINTSTS_PTXFEMP | \
3201 GINTSTS_RXFLVL)
3202
3203
3204
3205
3206
3207
3208
3209void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3210 bool is_usb_reset)
3211{
3212 u32 intmsk;
3213 u32 val;
3214 u32 usbcfg;
3215 u32 dcfg = 0;
3216
3217
3218 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3219
3220 if (!is_usb_reset)
3221 if (dwc2_core_reset(hsotg, true))
3222 return;
3223
3224
3225
3226
3227
3228
3229
3230 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3231 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3232 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
3233
3234 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
3235 (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
3236 hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
3237
3238 usbcfg |= GUSBCFG_PHYSEL;
3239 } else {
3240
3241 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3242 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3243 (val << GUSBCFG_USBTRDTIM_SHIFT);
3244 }
3245 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3246
3247 dwc2_hsotg_init_fifo(hsotg);
3248
3249 if (!is_usb_reset)
3250 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3251
3252 dcfg |= DCFG_EPMISCNT(1);
3253
3254 switch (hsotg->params.speed) {
3255 case DWC2_SPEED_PARAM_LOW:
3256 dcfg |= DCFG_DEVSPD_LS;
3257 break;
3258 case DWC2_SPEED_PARAM_FULL:
3259 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3260 dcfg |= DCFG_DEVSPD_FS48;
3261 else
3262 dcfg |= DCFG_DEVSPD_FS;
3263 break;
3264 default:
3265 dcfg |= DCFG_DEVSPD_HS;
3266 }
3267
3268 dwc2_writel(dcfg, hsotg->regs + DCFG);
3269
3270
3271 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
3272
3273
3274 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
3275 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3276 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3277 GINTSTS_USBRST | GINTSTS_RESETDET |
3278 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3279 GINTSTS_USBSUSP | GINTSTS_WKUPINT;
3280
3281 if (!using_desc_dma(hsotg))
3282 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3283
3284 if (!hsotg->params.external_id_pin_ctl)
3285 intmsk |= GINTSTS_CONIDSTSCHNG;
3286
3287 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
3288
3289 if (using_dma(hsotg)) {
3290 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3291 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
3292 hsotg->regs + GAHBCFG);
3293
3294
3295 if (using_desc_dma(hsotg))
3296 __orr32(hsotg->regs + DCFG, DCFG_DESCDMA_EN);
3297
3298 } else {
3299 dwc2_writel(((hsotg->dedicated_fifos) ?
3300 (GAHBCFG_NP_TXF_EMP_LVL |
3301 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3302 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
3303 }
3304
3305
3306
3307
3308
3309
3310
3311 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3312 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3313 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3314 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3315 hsotg->regs + DIEPMSK);
3316
3317
3318
3319
3320
3321 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3322 DOEPMSK_STSPHSERCVDMSK) : 0) |
3323 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3324 DOEPMSK_SETUPMSK,
3325 hsotg->regs + DOEPMSK);
3326
3327
3328 if (using_desc_dma(hsotg))
3329 __orr32(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK);
3330
3331 dwc2_writel(0, hsotg->regs + DAINTMSK);
3332
3333 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3334 dwc2_readl(hsotg->regs + DIEPCTL0),
3335 dwc2_readl(hsotg->regs + DOEPCTL0));
3336
3337
3338 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3339
3340
3341
3342
3343
3344
3345 if (!using_dma(hsotg))
3346 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3347
3348
3349 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3350 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3351
3352 if (!is_usb_reset) {
3353 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3354 udelay(10);
3355 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3356 }
3357
3358 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
3359
3360
3361
3362
3363
3364
3365
3366 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3367 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
3368
3369 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3370 DXEPCTL_CNAK | DXEPCTL_EPENA |
3371 DXEPCTL_USBACTEP,
3372 hsotg->regs + DOEPCTL0);
3373
3374
3375 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3376 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
3377
3378 dwc2_hsotg_enqueue_setup(hsotg);
3379
3380 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3381 dwc2_readl(hsotg->regs + DIEPCTL0),
3382 dwc2_readl(hsotg->regs + DOEPCTL0));
3383
3384
3385 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3386 if (!is_usb_reset)
3387 val |= DCTL_SFTDISCON;
3388 __orr32(hsotg->regs + DCTL, val);
3389
3390
3391 mdelay(3);
3392
3393 hsotg->lx_state = DWC2_L0;
3394}
3395
3396static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3397{
3398
3399 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3400}
3401
3402void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3403{
3404
3405 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3406}
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3422{
3423 struct dwc2_hsotg_ep *hs_ep;
3424 u32 epctrl;
3425 u32 idx;
3426
3427 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3428
3429 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3430 hs_ep = hsotg->eps_in[idx];
3431 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx));
3432 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous &&
3433 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3434 epctrl |= DXEPCTL_SNAK;
3435 epctrl |= DXEPCTL_EPDIS;
3436 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx));
3437 }
3438 }
3439
3440
3441 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
3442}
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3458{
3459 u32 gintsts;
3460 u32 gintmsk;
3461 u32 epctrl;
3462 struct dwc2_hsotg_ep *hs_ep;
3463 int idx;
3464
3465 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3466
3467 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3468 hs_ep = hsotg->eps_out[idx];
3469 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3470 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous &&
3471 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3472
3473 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3474 gintmsk |= GINTSTS_GOUTNAKEFF;
3475 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3476
3477 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3478 if (!(gintsts & GINTSTS_GOUTNAKEFF))
3479 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3480 }
3481 }
3482
3483
3484 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
3485}
3486
3487
3488
3489
3490
3491
3492static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3493{
3494 struct dwc2_hsotg *hsotg = pw;
3495 int retry_count = 8;
3496 u32 gintsts;
3497 u32 gintmsk;
3498
3499 if (!dwc2_is_device_mode(hsotg))
3500 return IRQ_NONE;
3501
3502 spin_lock(&hsotg->lock);
3503irq_retry:
3504 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3505 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3506
3507 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3508 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3509
3510 gintsts &= gintmsk;
3511
3512 if (gintsts & GINTSTS_RESETDET) {
3513 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3514
3515 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
3516
3517
3518 if (hsotg->lx_state == DWC2_L2) {
3519 dwc2_exit_hibernation(hsotg, true);
3520 hsotg->lx_state = DWC2_L0;
3521 }
3522 }
3523
3524 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3525 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
3526 u32 connected = hsotg->connected;
3527
3528 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3529 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3530 dwc2_readl(hsotg->regs + GNPTXSTS));
3531
3532 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
3533
3534
3535 dwc2_hsotg_disconnect(hsotg);
3536
3537
3538 __bic32(hsotg->regs + DCFG, DCFG_DEVADDR_MASK);
3539
3540 if (usb_status & GOTGCTL_BSESVLD && connected)
3541 dwc2_hsotg_core_init_disconnected(hsotg, true);
3542 }
3543
3544 if (gintsts & GINTSTS_ENUMDONE) {
3545 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
3546
3547 dwc2_hsotg_irq_enumdone(hsotg);
3548 }
3549
3550 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3551 u32 daint = dwc2_readl(hsotg->regs + DAINT);
3552 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3553 u32 daint_out, daint_in;
3554 int ep;
3555
3556 daint &= daintmsk;
3557 daint_out = daint >> DAINT_OUTEP_SHIFT;
3558 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3559
3560 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3561
3562 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3563 ep++, daint_out >>= 1) {
3564 if (daint_out & 1)
3565 dwc2_hsotg_epint(hsotg, ep, 0);
3566 }
3567
3568 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3569 ep++, daint_in >>= 1) {
3570 if (daint_in & 1)
3571 dwc2_hsotg_epint(hsotg, ep, 1);
3572 }
3573 }
3574
3575
3576
3577 if (gintsts & GINTSTS_NPTXFEMP) {
3578 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3579
3580
3581
3582
3583
3584
3585
3586 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3587 dwc2_hsotg_irq_fifoempty(hsotg, false);
3588 }
3589
3590 if (gintsts & GINTSTS_PTXFEMP) {
3591 dev_dbg(hsotg->dev, "PTxFEmp\n");
3592
3593
3594
3595 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3596 dwc2_hsotg_irq_fifoempty(hsotg, true);
3597 }
3598
3599 if (gintsts & GINTSTS_RXFLVL) {
3600
3601
3602
3603
3604
3605
3606 dwc2_hsotg_handle_rx(hsotg);
3607 }
3608
3609 if (gintsts & GINTSTS_ERLYSUSP) {
3610 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3611 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
3612 }
3613
3614
3615
3616
3617
3618
3619
3620 if (gintsts & GINTSTS_GOUTNAKEFF) {
3621 u8 idx;
3622 u32 epctrl;
3623 u32 gintmsk;
3624 struct dwc2_hsotg_ep *hs_ep;
3625
3626
3627 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3628 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3629 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3630
3631 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3632 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3633 hs_ep = hsotg->eps_out[idx];
3634 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3635
3636 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3637 epctrl |= DXEPCTL_SNAK;
3638 epctrl |= DXEPCTL_EPDIS;
3639 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx));
3640 }
3641 }
3642
3643
3644 }
3645
3646 if (gintsts & GINTSTS_GINNAKEFF) {
3647 dev_info(hsotg->dev, "GINNakEff triggered\n");
3648
3649 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3650
3651 dwc2_hsotg_dump(hsotg);
3652 }
3653
3654 if (gintsts & GINTSTS_INCOMPL_SOIN)
3655 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3656
3657 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3658 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3659
3660
3661
3662
3663
3664
3665 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3666 goto irq_retry;
3667
3668 spin_unlock(&hsotg->lock);
3669
3670 return IRQ_HANDLED;
3671}
3672
3673static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
3674 u32 bit, u32 timeout)
3675{
3676 u32 i;
3677
3678 for (i = 0; i < timeout; i++) {
3679 if (dwc2_readl(hs_otg->regs + reg) & bit)
3680 return 0;
3681 udelay(1);
3682 }
3683
3684 return -ETIMEDOUT;
3685}
3686
3687static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3688 struct dwc2_hsotg_ep *hs_ep)
3689{
3690 u32 epctrl_reg;
3691 u32 epint_reg;
3692
3693 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3694 DOEPCTL(hs_ep->index);
3695 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3696 DOEPINT(hs_ep->index);
3697
3698 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3699 hs_ep->name);
3700
3701 if (hs_ep->dir_in) {
3702 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3703 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
3704
3705 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3706 DXEPINT_INEPNAKEFF, 100))
3707 dev_warn(hsotg->dev,
3708 "%s: timeout DIEPINT.NAKEFF\n",
3709 __func__);
3710 } else {
3711 __orr32(hsotg->regs + DCTL, DCTL_SGNPINNAK);
3712
3713 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3714 GINTSTS_GINNAKEFF, 100))
3715 dev_warn(hsotg->dev,
3716 "%s: timeout GINTSTS.GINNAKEFF\n",
3717 __func__);
3718 }
3719 } else {
3720 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
3721 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3722
3723
3724 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3725 GINTSTS_GOUTNAKEFF, 100))
3726 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3727 __func__);
3728 }
3729
3730
3731 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3732
3733
3734 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3735 dev_warn(hsotg->dev,
3736 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3737
3738
3739 __orr32(hsotg->regs + epint_reg, DXEPINT_EPDISBLD);
3740
3741 if (hs_ep->dir_in) {
3742 unsigned short fifo_index;
3743
3744 if (hsotg->dedicated_fifos || hs_ep->periodic)
3745 fifo_index = hs_ep->fifo_index;
3746 else
3747 fifo_index = 0;
3748
3749
3750 dwc2_flush_tx_fifo(hsotg, fifo_index);
3751
3752
3753 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3754 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3755
3756 } else {
3757
3758 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
3759 }
3760}
3761
3762
3763
3764
3765
3766
3767
3768
3769static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3770 const struct usb_endpoint_descriptor *desc)
3771{
3772 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3773 struct dwc2_hsotg *hsotg = hs_ep->parent;
3774 unsigned long flags;
3775 unsigned int index = hs_ep->index;
3776 u32 epctrl_reg;
3777 u32 epctrl;
3778 u32 mps;
3779 u32 mc;
3780 u32 mask;
3781 unsigned int dir_in;
3782 unsigned int i, val, size;
3783 int ret = 0;
3784
3785 dev_dbg(hsotg->dev,
3786 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3787 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3788 desc->wMaxPacketSize, desc->bInterval);
3789
3790
3791 if (index == 0) {
3792 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3793 return -EINVAL;
3794 }
3795
3796 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3797 if (dir_in != hs_ep->dir_in) {
3798 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3799 return -EINVAL;
3800 }
3801
3802 mps = usb_endpoint_maxp(desc);
3803 mc = usb_endpoint_maxp_mult(desc);
3804
3805
3806
3807 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3808 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3809
3810 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3811 __func__, epctrl, epctrl_reg);
3812
3813
3814 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
3815 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
3816 MAX_DMA_DESC_NUM_GENERIC *
3817 sizeof(struct dwc2_dma_desc),
3818 &hs_ep->desc_list_dma, GFP_ATOMIC);
3819 if (!hs_ep->desc_list) {
3820 ret = -ENOMEM;
3821 goto error2;
3822 }
3823 }
3824
3825 spin_lock_irqsave(&hsotg->lock, flags);
3826
3827 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3828 epctrl |= DXEPCTL_MPS(mps);
3829
3830
3831
3832
3833
3834 epctrl |= DXEPCTL_USBACTEP;
3835
3836
3837 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
3838
3839
3840 hs_ep->isochronous = 0;
3841 hs_ep->periodic = 0;
3842 hs_ep->halted = 0;
3843 hs_ep->interval = desc->bInterval;
3844
3845 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
3846 case USB_ENDPOINT_XFER_ISOC:
3847 epctrl |= DXEPCTL_EPTYPE_ISO;
3848 epctrl |= DXEPCTL_SETEVENFR;
3849 hs_ep->isochronous = 1;
3850 hs_ep->interval = 1 << (desc->bInterval - 1);
3851 hs_ep->target_frame = TARGET_FRAME_INITIAL;
3852 hs_ep->isoc_chain_num = 0;
3853 hs_ep->next_desc = 0;
3854 if (dir_in) {
3855 hs_ep->periodic = 1;
3856 mask = dwc2_readl(hsotg->regs + DIEPMSK);
3857 mask |= DIEPMSK_NAKMSK;
3858 dwc2_writel(mask, hsotg->regs + DIEPMSK);
3859 } else {
3860 mask = dwc2_readl(hsotg->regs + DOEPMSK);
3861 mask |= DOEPMSK_OUTTKNEPDISMSK;
3862 dwc2_writel(mask, hsotg->regs + DOEPMSK);
3863 }
3864 break;
3865
3866 case USB_ENDPOINT_XFER_BULK:
3867 epctrl |= DXEPCTL_EPTYPE_BULK;
3868 break;
3869
3870 case USB_ENDPOINT_XFER_INT:
3871 if (dir_in)
3872 hs_ep->periodic = 1;
3873
3874 if (hsotg->gadget.speed == USB_SPEED_HIGH)
3875 hs_ep->interval = 1 << (desc->bInterval - 1);
3876
3877 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
3878 break;
3879
3880 case USB_ENDPOINT_XFER_CONTROL:
3881 epctrl |= DXEPCTL_EPTYPE_CONTROL;
3882 break;
3883 }
3884
3885
3886
3887
3888
3889 if (dir_in && hsotg->dedicated_fifos) {
3890 u32 fifo_index = 0;
3891 u32 fifo_size = UINT_MAX;
3892
3893 size = hs_ep->ep.maxpacket * hs_ep->mc;
3894 for (i = 1; i < hsotg->num_of_eps; ++i) {
3895 if (hsotg->fifo_map & (1 << i))
3896 continue;
3897 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
3898 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3899 if (val < size)
3900 continue;
3901
3902 if (val < fifo_size) {
3903 fifo_size = val;
3904 fifo_index = i;
3905 }
3906 }
3907 if (!fifo_index) {
3908 dev_err(hsotg->dev,
3909 "%s: No suitable fifo found\n", __func__);
3910 ret = -ENOMEM;
3911 goto error1;
3912 }
3913 hsotg->fifo_map |= 1 << fifo_index;
3914 epctrl |= DXEPCTL_TXFNUM(fifo_index);
3915 hs_ep->fifo_index = fifo_index;
3916 hs_ep->fifo_size = fifo_size;
3917 }
3918
3919
3920 if (index && !hs_ep->isochronous)
3921 epctrl |= DXEPCTL_SETD0PID;
3922
3923 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3924 __func__, epctrl);
3925
3926 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
3927 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3928 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
3929
3930
3931 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
3932
3933error1:
3934 spin_unlock_irqrestore(&hsotg->lock, flags);
3935
3936error2:
3937 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
3938 dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
3939 sizeof(struct dwc2_dma_desc),
3940 hs_ep->desc_list, hs_ep->desc_list_dma);
3941 hs_ep->desc_list = NULL;
3942 }
3943
3944 return ret;
3945}
3946
3947
3948
3949
3950
3951static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
3952{
3953 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3954 struct dwc2_hsotg *hsotg = hs_ep->parent;
3955 int dir_in = hs_ep->dir_in;
3956 int index = hs_ep->index;
3957 unsigned long flags;
3958 u32 epctrl_reg;
3959 u32 ctrl;
3960
3961 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
3962
3963 if (ep == &hsotg->eps_out[0]->ep) {
3964 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
3965 return -EINVAL;
3966 }
3967
3968 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3969 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
3970 return -EINVAL;
3971 }
3972
3973 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3974
3975 spin_lock_irqsave(&hsotg->lock, flags);
3976
3977 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3978
3979 if (ctrl & DXEPCTL_EPENA)
3980 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3981
3982 ctrl &= ~DXEPCTL_EPENA;
3983 ctrl &= ~DXEPCTL_USBACTEP;
3984 ctrl |= DXEPCTL_SNAK;
3985
3986 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
3987 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
3988
3989
3990 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
3991
3992
3993 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
3994
3995 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
3996 hs_ep->fifo_index = 0;
3997 hs_ep->fifo_size = 0;
3998
3999 spin_unlock_irqrestore(&hsotg->lock, flags);
4000 return 0;
4001}
4002
4003
4004
4005
4006
4007
4008static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4009{
4010 struct dwc2_hsotg_req *req, *treq;
4011
4012 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4013 if (req == test)
4014 return true;
4015 }
4016
4017 return false;
4018}
4019
4020
4021
4022
4023
4024
4025static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4026{
4027 struct dwc2_hsotg_req *hs_req = our_req(req);
4028 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4029 struct dwc2_hsotg *hs = hs_ep->parent;
4030 unsigned long flags;
4031
4032 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4033
4034 spin_lock_irqsave(&hs->lock, flags);
4035
4036 if (!on_list(hs_ep, hs_req)) {
4037 spin_unlock_irqrestore(&hs->lock, flags);
4038 return -EINVAL;
4039 }
4040
4041
4042 if (req == &hs_ep->req->req)
4043 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4044
4045 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4046 spin_unlock_irqrestore(&hs->lock, flags);
4047
4048 return 0;
4049}
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4062{
4063 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4064 struct dwc2_hsotg *hs = hs_ep->parent;
4065 int index = hs_ep->index;
4066 u32 epreg;
4067 u32 epctl;
4068 u32 xfertype;
4069
4070 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4071
4072 if (index == 0) {
4073 if (value)
4074 dwc2_hsotg_stall_ep0(hs);
4075 else
4076 dev_warn(hs->dev,
4077 "%s: can't clear halt on ep0\n", __func__);
4078 return 0;
4079 }
4080
4081 if (hs_ep->isochronous) {
4082 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4083 return -EINVAL;
4084 }
4085
4086 if (!now && value && !list_empty(&hs_ep->queue)) {
4087 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4088 ep->name);
4089 return -EAGAIN;
4090 }
4091
4092 if (hs_ep->dir_in) {
4093 epreg = DIEPCTL(index);
4094 epctl = dwc2_readl(hs->regs + epreg);
4095
4096 if (value) {
4097 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4098 if (epctl & DXEPCTL_EPENA)
4099 epctl |= DXEPCTL_EPDIS;
4100 } else {
4101 epctl &= ~DXEPCTL_STALL;
4102 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4103 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4104 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4105 epctl |= DXEPCTL_SETD0PID;
4106 }
4107 dwc2_writel(epctl, hs->regs + epreg);
4108 } else {
4109 epreg = DOEPCTL(index);
4110 epctl = dwc2_readl(hs->regs + epreg);
4111
4112 if (value) {
4113 epctl |= DXEPCTL_STALL;
4114 } else {
4115 epctl &= ~DXEPCTL_STALL;
4116 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4117 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4118 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4119 epctl |= DXEPCTL_SETD0PID;
4120 }
4121 dwc2_writel(epctl, hs->regs + epreg);
4122 }
4123
4124 hs_ep->halted = value;
4125
4126 return 0;
4127}
4128
4129
4130
4131
4132
4133
4134static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4135{
4136 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4137 struct dwc2_hsotg *hs = hs_ep->parent;
4138 unsigned long flags = 0;
4139 int ret = 0;
4140
4141 spin_lock_irqsave(&hs->lock, flags);
4142 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4143 spin_unlock_irqrestore(&hs->lock, flags);
4144
4145 return ret;
4146}
4147
4148static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4149 .enable = dwc2_hsotg_ep_enable,
4150 .disable = dwc2_hsotg_ep_disable,
4151 .alloc_request = dwc2_hsotg_ep_alloc_request,
4152 .free_request = dwc2_hsotg_ep_free_request,
4153 .queue = dwc2_hsotg_ep_queue_lock,
4154 .dequeue = dwc2_hsotg_ep_dequeue,
4155 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4156
4157};
4158
4159
4160
4161
4162
4163static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4164{
4165 u32 trdtim;
4166 u32 usbcfg;
4167
4168
4169 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4170 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4171 hsotg->regs + DIEPMSK);
4172
4173 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4174 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4175 hsotg->regs + DOEPMSK);
4176
4177 dwc2_writel(0, hsotg->regs + DAINTMSK);
4178
4179
4180 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
4181
4182
4183
4184 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4185 dwc2_readl(hsotg->regs + GRXFSIZ),
4186 dwc2_readl(hsotg->regs + GNPTXFSIZ));
4187
4188 dwc2_hsotg_init_fifo(hsotg);
4189
4190
4191 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
4192 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4193 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
4194
4195
4196 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4197 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4198 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4199 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
4200
4201 if (using_dma(hsotg))
4202 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
4203}
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4214 struct usb_gadget_driver *driver)
4215{
4216 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4217 unsigned long flags;
4218 int ret;
4219
4220 if (!hsotg) {
4221 pr_err("%s: called with no device\n", __func__);
4222 return -ENODEV;
4223 }
4224
4225 if (!driver) {
4226 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4227 return -EINVAL;
4228 }
4229
4230 if (driver->max_speed < USB_SPEED_FULL)
4231 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4232
4233 if (!driver->setup) {
4234 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4235 return -EINVAL;
4236 }
4237
4238 WARN_ON(hsotg->driver);
4239
4240 driver->driver.bus = NULL;
4241 hsotg->driver = driver;
4242 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4243 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4244
4245 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4246 ret = dwc2_lowlevel_hw_enable(hsotg);
4247 if (ret)
4248 goto err;
4249 }
4250
4251 if (!IS_ERR_OR_NULL(hsotg->uphy))
4252 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4253
4254 spin_lock_irqsave(&hsotg->lock, flags);
4255 if (dwc2_hw_is_device(hsotg)) {
4256 dwc2_hsotg_init(hsotg);
4257 dwc2_hsotg_core_init_disconnected(hsotg, false);
4258 }
4259
4260 hsotg->enabled = 0;
4261 spin_unlock_irqrestore(&hsotg->lock, flags);
4262
4263 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4264
4265 return 0;
4266
4267err:
4268 hsotg->driver = NULL;
4269 return ret;
4270}
4271
4272
4273
4274
4275
4276
4277
4278
4279static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4280{
4281 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4282 unsigned long flags = 0;
4283 int ep;
4284
4285 if (!hsotg)
4286 return -ENODEV;
4287
4288
4289 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4290 if (hsotg->eps_in[ep])
4291 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4292 if (hsotg->eps_out[ep])
4293 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4294 }
4295
4296 spin_lock_irqsave(&hsotg->lock, flags);
4297
4298 hsotg->driver = NULL;
4299 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4300 hsotg->enabled = 0;
4301
4302 spin_unlock_irqrestore(&hsotg->lock, flags);
4303
4304 if (!IS_ERR_OR_NULL(hsotg->uphy))
4305 otg_set_peripheral(hsotg->uphy->otg, NULL);
4306
4307 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4308 dwc2_lowlevel_hw_disable(hsotg);
4309
4310 return 0;
4311}
4312
4313
4314
4315
4316
4317
4318
4319static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4320{
4321 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4322}
4323
4324
4325
4326
4327
4328
4329
4330
4331static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4332{
4333 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4334 unsigned long flags = 0;
4335
4336 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4337 hsotg->op_state);
4338
4339
4340 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4341 hsotg->enabled = is_on;
4342 return 0;
4343 }
4344
4345 spin_lock_irqsave(&hsotg->lock, flags);
4346 if (is_on) {
4347 hsotg->enabled = 1;
4348 dwc2_hsotg_core_init_disconnected(hsotg, false);
4349 dwc2_hsotg_core_connect(hsotg);
4350 } else {
4351 dwc2_hsotg_core_disconnect(hsotg);
4352 dwc2_hsotg_disconnect(hsotg);
4353 hsotg->enabled = 0;
4354 }
4355
4356 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4357 spin_unlock_irqrestore(&hsotg->lock, flags);
4358
4359 return 0;
4360}
4361
4362static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4363{
4364 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4365 unsigned long flags;
4366
4367 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4368 spin_lock_irqsave(&hsotg->lock, flags);
4369
4370
4371
4372
4373
4374 if (hsotg->lx_state == DWC2_L2)
4375 dwc2_exit_hibernation(hsotg, false);
4376
4377 if (is_active) {
4378 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4379
4380 dwc2_hsotg_core_init_disconnected(hsotg, false);
4381 if (hsotg->enabled)
4382 dwc2_hsotg_core_connect(hsotg);
4383 } else {
4384 dwc2_hsotg_core_disconnect(hsotg);
4385 dwc2_hsotg_disconnect(hsotg);
4386 }
4387
4388 spin_unlock_irqrestore(&hsotg->lock, flags);
4389 return 0;
4390}
4391
4392
4393
4394
4395
4396
4397
4398
4399static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4400{
4401 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4402
4403 if (IS_ERR_OR_NULL(hsotg->uphy))
4404 return -ENOTSUPP;
4405 return usb_phy_set_power(hsotg->uphy, mA);
4406}
4407
4408static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4409 .get_frame = dwc2_hsotg_gadget_getframe,
4410 .udc_start = dwc2_hsotg_udc_start,
4411 .udc_stop = dwc2_hsotg_udc_stop,
4412 .pullup = dwc2_hsotg_pullup,
4413 .vbus_session = dwc2_hsotg_vbus_session,
4414 .vbus_draw = dwc2_hsotg_vbus_draw,
4415};
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4428 struct dwc2_hsotg_ep *hs_ep,
4429 int epnum,
4430 bool dir_in)
4431{
4432 char *dir;
4433
4434 if (epnum == 0)
4435 dir = "";
4436 else if (dir_in)
4437 dir = "in";
4438 else
4439 dir = "out";
4440
4441 hs_ep->dir_in = dir_in;
4442 hs_ep->index = epnum;
4443
4444 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4445
4446 INIT_LIST_HEAD(&hs_ep->queue);
4447 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4448
4449
4450 if (epnum)
4451 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4452
4453 hs_ep->parent = hsotg;
4454 hs_ep->ep.name = hs_ep->name;
4455
4456 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4457 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4458 else
4459 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4460 epnum ? 1024 : EP0_MPS_LIMIT);
4461 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4462
4463 if (epnum == 0) {
4464 hs_ep->ep.caps.type_control = true;
4465 } else {
4466 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4467 hs_ep->ep.caps.type_iso = true;
4468 hs_ep->ep.caps.type_bulk = true;
4469 }
4470 hs_ep->ep.caps.type_int = true;
4471 }
4472
4473 if (dir_in)
4474 hs_ep->ep.caps.dir_in = true;
4475 else
4476 hs_ep->ep.caps.dir_out = true;
4477
4478
4479
4480
4481
4482
4483 if (using_dma(hsotg)) {
4484 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4485
4486 if (dir_in)
4487 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
4488 else
4489 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
4490 }
4491}
4492
4493
4494
4495
4496
4497
4498
4499static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4500{
4501 u32 cfg;
4502 u32 ep_type;
4503 u32 i;
4504
4505
4506
4507 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4508
4509
4510 hsotg->num_of_eps++;
4511
4512 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4513 sizeof(struct dwc2_hsotg_ep),
4514 GFP_KERNEL);
4515 if (!hsotg->eps_in[0])
4516 return -ENOMEM;
4517
4518 hsotg->eps_out[0] = hsotg->eps_in[0];
4519
4520 cfg = hsotg->hw_params.dev_ep_dirs;
4521 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4522 ep_type = cfg & 3;
4523
4524 if (!(ep_type & 2)) {
4525 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4526 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4527 if (!hsotg->eps_in[i])
4528 return -ENOMEM;
4529 }
4530
4531 if (!(ep_type & 1)) {
4532 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4533 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4534 if (!hsotg->eps_out[i])
4535 return -ENOMEM;
4536 }
4537 }
4538
4539 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4540 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4541
4542 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4543 hsotg->num_of_eps,
4544 hsotg->dedicated_fifos ? "dedicated" : "shared",
4545 hsotg->fifo_mem);
4546 return 0;
4547}
4548
4549
4550
4551
4552
4553static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4554{
4555#ifdef DEBUG
4556 struct device *dev = hsotg->dev;
4557 void __iomem *regs = hsotg->regs;
4558 u32 val;
4559 int idx;
4560
4561 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4562 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
4563 dwc2_readl(regs + DIEPMSK));
4564
4565 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4566 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
4567
4568 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4569 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
4570
4571
4572
4573 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4574 val = dwc2_readl(regs + DPTXFSIZN(idx));
4575 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4576 val >> FIFOSIZE_DEPTH_SHIFT,
4577 val & FIFOSIZE_STARTADDR_MASK);
4578 }
4579
4580 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4581 dev_info(dev,
4582 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4583 dwc2_readl(regs + DIEPCTL(idx)),
4584 dwc2_readl(regs + DIEPTSIZ(idx)),
4585 dwc2_readl(regs + DIEPDMA(idx)));
4586
4587 val = dwc2_readl(regs + DOEPCTL(idx));
4588 dev_info(dev,
4589 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4590 idx, dwc2_readl(regs + DOEPCTL(idx)),
4591 dwc2_readl(regs + DOEPTSIZ(idx)),
4592 dwc2_readl(regs + DOEPDMA(idx)));
4593 }
4594
4595 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4596 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
4597#endif
4598}
4599
4600
4601
4602
4603
4604
4605int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
4606{
4607 struct device *dev = hsotg->dev;
4608 int epnum;
4609 int ret;
4610
4611
4612 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4613 hsotg->params.g_np_tx_fifo_size);
4614 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4615
4616 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4617 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4618 hsotg->gadget.name = dev_name(dev);
4619 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4620 hsotg->gadget.is_otg = 1;
4621 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4622 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4623
4624 ret = dwc2_hsotg_hw_cfg(hsotg);
4625 if (ret) {
4626 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4627 return ret;
4628 }
4629
4630 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4631 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4632 if (!hsotg->ctrl_buff)
4633 return -ENOMEM;
4634
4635 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4636 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4637 if (!hsotg->ep0_buff)
4638 return -ENOMEM;
4639
4640 if (using_desc_dma(hsotg)) {
4641 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4642 if (ret < 0)
4643 return ret;
4644 }
4645
4646 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
4647 dev_name(hsotg->dev), hsotg);
4648 if (ret < 0) {
4649 dev_err(dev, "cannot claim IRQ for gadget\n");
4650 return ret;
4651 }
4652
4653
4654
4655 if (hsotg->num_of_eps == 0) {
4656 dev_err(dev, "wrong number of EPs (zero)\n");
4657 return -EINVAL;
4658 }
4659
4660
4661
4662 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4663 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4664
4665
4666
4667 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4668 GFP_KERNEL);
4669 if (!hsotg->ctrl_req) {
4670 dev_err(dev, "failed to allocate ctrl req\n");
4671 return -ENOMEM;
4672 }
4673
4674
4675 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4676 if (hsotg->eps_in[epnum])
4677 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4678 epnum, 1);
4679 if (hsotg->eps_out[epnum])
4680 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4681 epnum, 0);
4682 }
4683
4684 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
4685 if (ret)
4686 return ret;
4687
4688 dwc2_hsotg_dump(hsotg);
4689
4690 return 0;
4691}
4692
4693
4694
4695
4696
4697int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4698{
4699 usb_del_gadget_udc(&hsotg->gadget);
4700
4701 return 0;
4702}
4703
4704int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4705{
4706 unsigned long flags;
4707
4708 if (hsotg->lx_state != DWC2_L0)
4709 return 0;
4710
4711 if (hsotg->driver) {
4712 int ep;
4713
4714 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4715 hsotg->driver->driver.name);
4716
4717 spin_lock_irqsave(&hsotg->lock, flags);
4718 if (hsotg->enabled)
4719 dwc2_hsotg_core_disconnect(hsotg);
4720 dwc2_hsotg_disconnect(hsotg);
4721 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4722 spin_unlock_irqrestore(&hsotg->lock, flags);
4723
4724 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4725 if (hsotg->eps_in[ep])
4726 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4727 if (hsotg->eps_out[ep])
4728 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4729 }
4730 }
4731
4732 return 0;
4733}
4734
4735int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4736{
4737 unsigned long flags;
4738
4739 if (hsotg->lx_state == DWC2_L2)
4740 return 0;
4741
4742 if (hsotg->driver) {
4743 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4744 hsotg->driver->driver.name);
4745
4746 spin_lock_irqsave(&hsotg->lock, flags);
4747 dwc2_hsotg_core_init_disconnected(hsotg, false);
4748 if (hsotg->enabled)
4749 dwc2_hsotg_core_connect(hsotg);
4750 spin_unlock_irqrestore(&hsotg->lock, flags);
4751 }
4752
4753 return 0;
4754}
4755
4756
4757
4758
4759
4760
4761
4762
4763int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4764{
4765 struct dwc2_dregs_backup *dr;
4766 int i;
4767
4768 dev_dbg(hsotg->dev, "%s\n", __func__);
4769
4770
4771 dr = &hsotg->dr_backup;
4772
4773 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
4774 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
4775 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
4776 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
4777 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
4778
4779 for (i = 0; i < hsotg->num_of_eps; i++) {
4780
4781 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
4782
4783
4784 if (dr->diepctl[i] & DXEPCTL_DPID)
4785 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4786 else
4787 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4788
4789 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
4790 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
4791
4792
4793 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
4794
4795
4796 if (dr->doepctl[i] & DXEPCTL_DPID)
4797 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4798 else
4799 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4800
4801 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
4802 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
4803 }
4804 dr->valid = true;
4805 return 0;
4806}
4807
4808
4809
4810
4811
4812
4813
4814
4815int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
4816{
4817 struct dwc2_dregs_backup *dr;
4818 u32 dctl;
4819 int i;
4820
4821 dev_dbg(hsotg->dev, "%s\n", __func__);
4822
4823
4824 dr = &hsotg->dr_backup;
4825 if (!dr->valid) {
4826 dev_err(hsotg->dev, "%s: no device registers to restore\n",
4827 __func__);
4828 return -EINVAL;
4829 }
4830 dr->valid = false;
4831
4832 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
4833 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
4834 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
4835 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
4836 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
4837
4838 for (i = 0; i < hsotg->num_of_eps; i++) {
4839
4840 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
4841 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
4842 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
4843
4844
4845 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
4846 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4847 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
4848 }
4849
4850
4851 dctl = dwc2_readl(hsotg->regs + DCTL);
4852 dctl |= DCTL_PWRONPRGDONE;
4853 dwc2_writel(dctl, hsotg->regs + DCTL);
4854
4855 return 0;
4856}
4857