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55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/dma-mapping.h>
58#include "xhci.h"
59#include "xhci-trace.h"
60#include "xhci-mtk.h"
61
62
63
64
65
66dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
67 union xhci_trb *trb)
68{
69 unsigned long segment_offset;
70
71 if (!seg || !trb || trb < seg->trbs)
72 return 0;
73
74 segment_offset = trb - seg->trbs;
75 if (segment_offset >= TRBS_PER_SEGMENT)
76 return 0;
77 return seg->dma + (segment_offset * sizeof(*trb));
78}
79
80static bool trb_is_noop(union xhci_trb *trb)
81{
82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
83}
84
85static bool trb_is_link(union xhci_trb *trb)
86{
87 return TRB_TYPE_LINK_LE32(trb->link.control);
88}
89
90static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
91{
92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
93}
94
95static bool last_trb_on_ring(struct xhci_ring *ring,
96 struct xhci_segment *seg, union xhci_trb *trb)
97{
98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
99}
100
101static bool link_trb_toggles_cycle(union xhci_trb *trb)
102{
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
104}
105
106static bool last_td_in_urb(struct xhci_td *td)
107{
108 struct urb_priv *urb_priv = td->urb->hcpriv;
109
110 return urb_priv->num_tds_done == urb_priv->num_tds;
111}
112
113static void inc_td_cnt(struct urb *urb)
114{
115 struct urb_priv *urb_priv = urb->hcpriv;
116
117 urb_priv->num_tds_done++;
118}
119
120static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
121{
122 if (trb_is_link(trb)) {
123
124 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
125 } else {
126 trb->generic.field[0] = 0;
127 trb->generic.field[1] = 0;
128 trb->generic.field[2] = 0;
129
130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
132 }
133}
134
135
136
137
138
139static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
143{
144 if (trb_is_link(*trb)) {
145 *seg = (*seg)->next;
146 *trb = ((*seg)->trbs);
147 } else {
148 (*trb)++;
149 }
150}
151
152
153
154
155
156static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
157{
158
159 if (ring->type == TYPE_EVENT) {
160 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
161 ring->dequeue++;
162 goto out;
163 }
164 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
165 ring->cycle_state ^= 1;
166 ring->deq_seg = ring->deq_seg->next;
167 ring->dequeue = ring->deq_seg->trbs;
168 goto out;
169 }
170
171
172 if (!trb_is_link(ring->dequeue)) {
173 ring->dequeue++;
174 ring->num_trbs_free++;
175 }
176 while (trb_is_link(ring->dequeue)) {
177 ring->deq_seg = ring->deq_seg->next;
178 ring->dequeue = ring->deq_seg->trbs;
179 }
180
181out:
182 trace_xhci_inc_deq(ring);
183
184 return;
185}
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
205 bool more_trbs_coming)
206{
207 u32 chain;
208 union xhci_trb *next;
209
210 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
211
212 if (!trb_is_link(ring->enqueue))
213 ring->num_trbs_free--;
214 next = ++(ring->enqueue);
215
216
217 while (trb_is_link(next)) {
218
219
220
221
222
223
224
225
226 if (!chain && !more_trbs_coming)
227 break;
228
229
230
231
232
233 if (!(ring->type == TYPE_ISOC &&
234 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
235 !xhci_link_trb_quirk(xhci)) {
236 next->link.control &= cpu_to_le32(~TRB_CHAIN);
237 next->link.control |= cpu_to_le32(chain);
238 }
239
240 wmb();
241 next->link.control ^= cpu_to_le32(TRB_CYCLE);
242
243
244 if (link_trb_toggles_cycle(next))
245 ring->cycle_state ^= 1;
246
247 ring->enq_seg = ring->enq_seg->next;
248 ring->enqueue = ring->enq_seg->trbs;
249 next = ring->enqueue;
250 }
251
252 trace_xhci_inc_enq(ring);
253}
254
255
256
257
258
259static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
260 unsigned int num_trbs)
261{
262 int num_trbs_in_deq_seg;
263
264 if (ring->num_trbs_free < num_trbs)
265 return 0;
266
267 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
268 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
269 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
270 return 0;
271 }
272
273 return 1;
274}
275
276
277void xhci_ring_cmd_db(struct xhci_hcd *xhci)
278{
279 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
280 return;
281
282 xhci_dbg(xhci, "// Ding dong!\n");
283 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
284
285 readl(&xhci->dba->doorbell[0]);
286}
287
288static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
289{
290 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
291}
292
293static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
294{
295 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
296 cmd_list);
297}
298
299
300
301
302
303
304static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
305 struct xhci_command *cur_cmd)
306{
307 struct xhci_command *i_cmd;
308
309
310 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
311
312 if (i_cmd->status != COMP_COMMAND_ABORTED)
313 continue;
314
315 i_cmd->status = COMP_COMMAND_RING_STOPPED;
316
317 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
318 i_cmd->command_trb);
319
320 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
321
322
323
324
325
326 }
327
328 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
329
330
331 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
332 !(xhci->xhc_state & XHCI_STATE_DYING)) {
333 xhci->current_cmd = cur_cmd;
334 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
335 xhci_ring_cmd_db(xhci);
336 }
337}
338
339
340static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
341{
342 u64 temp_64;
343 int ret;
344
345 xhci_dbg(xhci, "Abort command ring\n");
346
347 reinit_completion(&xhci->cmd_ring_stop_completion);
348
349 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
350 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
351 &xhci->op_regs->cmd_ring);
352
353
354
355
356
357
358
359 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
360 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
361 if (ret < 0) {
362 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
363 xhci_halt(xhci);
364 xhci_hc_died(xhci);
365 return ret;
366 }
367
368
369
370
371
372
373 spin_unlock_irqrestore(&xhci->lock, flags);
374 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
375 msecs_to_jiffies(2000));
376 spin_lock_irqsave(&xhci->lock, flags);
377 if (!ret) {
378 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
379 xhci_cleanup_command_queue(xhci);
380 } else {
381 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
382 }
383 return 0;
384}
385
386void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
387 unsigned int slot_id,
388 unsigned int ep_index,
389 unsigned int stream_id)
390{
391 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
392 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
393 unsigned int ep_state = ep->ep_state;
394
395
396
397
398
399
400
401 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
402 (ep_state & EP_HALTED))
403 return;
404 writel(DB_VALUE(ep_index, stream_id), db_addr);
405
406
407
408}
409
410
411static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
412 unsigned int slot_id,
413 unsigned int ep_index)
414{
415 unsigned int stream_id;
416 struct xhci_virt_ep *ep;
417
418 ep = &xhci->devs[slot_id]->eps[ep_index];
419
420
421 if (!(ep->ep_state & EP_HAS_STREAMS)) {
422 if (ep->ring && !(list_empty(&ep->ring->td_list)))
423 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
424 return;
425 }
426
427 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
428 stream_id++) {
429 struct xhci_stream_info *stream_info = ep->stream_info;
430 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
431 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
432 stream_id);
433 }
434}
435
436
437
438
439
440struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
441 unsigned int slot_id, unsigned int ep_index,
442 unsigned int stream_id)
443{
444 struct xhci_virt_ep *ep;
445
446 ep = &xhci->devs[slot_id]->eps[ep_index];
447
448 if (!(ep->ep_state & EP_HAS_STREAMS))
449 return ep->ring;
450
451 if (stream_id == 0) {
452 xhci_warn(xhci,
453 "WARN: Slot ID %u, ep index %u has streams, "
454 "but URB has no stream ID.\n",
455 slot_id, ep_index);
456 return NULL;
457 }
458
459 if (stream_id < ep->stream_info->num_streams)
460 return ep->stream_info->stream_rings[stream_id];
461
462 xhci_warn(xhci,
463 "WARN: Slot ID %u, ep index %u has "
464 "stream IDs 1 to %u allocated, "
465 "but stream ID %u is requested.\n",
466 slot_id, ep_index,
467 ep->stream_info->num_streams - 1,
468 stream_id);
469 return NULL;
470}
471
472
473
474
475
476
477
478
479static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
480 unsigned int ep_index, unsigned int stream_id)
481{
482 struct xhci_ep_ctx *ep_ctx;
483 struct xhci_stream_ctx *st_ctx;
484 struct xhci_virt_ep *ep;
485
486 ep = &vdev->eps[ep_index];
487
488 if (ep->ep_state & EP_HAS_STREAMS) {
489 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
490 return le64_to_cpu(st_ctx->stream_ring);
491 }
492 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
493 return le64_to_cpu(ep_ctx->deq);
494}
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
515 unsigned int slot_id, unsigned int ep_index,
516 unsigned int stream_id, struct xhci_td *cur_td,
517 struct xhci_dequeue_state *state)
518{
519 struct xhci_virt_device *dev = xhci->devs[slot_id];
520 struct xhci_virt_ep *ep = &dev->eps[ep_index];
521 struct xhci_ring *ep_ring;
522 struct xhci_segment *new_seg;
523 union xhci_trb *new_deq;
524 dma_addr_t addr;
525 u64 hw_dequeue;
526 bool cycle_found = false;
527 bool td_last_trb_found = false;
528
529 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
530 ep_index, stream_id);
531 if (!ep_ring) {
532 xhci_warn(xhci, "WARN can't find new dequeue state "
533 "for invalid stream ID %u.\n",
534 stream_id);
535 return;
536 }
537
538 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
539 "Finding endpoint context");
540
541 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
542 new_seg = ep_ring->deq_seg;
543 new_deq = ep_ring->dequeue;
544 state->new_cycle_state = hw_dequeue & 0x1;
545 state->stream_id = stream_id;
546
547
548
549
550
551
552
553 do {
554 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
555 == (dma_addr_t)(hw_dequeue & ~0xf)) {
556 cycle_found = true;
557 if (td_last_trb_found)
558 break;
559 }
560 if (new_deq == cur_td->last_trb)
561 td_last_trb_found = true;
562
563 if (cycle_found && trb_is_link(new_deq) &&
564 link_trb_toggles_cycle(new_deq))
565 state->new_cycle_state ^= 0x1;
566
567 next_trb(xhci, ep_ring, &new_seg, &new_deq);
568
569
570 if (new_deq == ep->ring->dequeue) {
571 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
572 state->new_deq_seg = NULL;
573 state->new_deq_ptr = NULL;
574 return;
575 }
576
577 } while (!cycle_found || !td_last_trb_found);
578
579 state->new_deq_seg = new_seg;
580 state->new_deq_ptr = new_deq;
581
582
583 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
584 "Cycle state = 0x%x", state->new_cycle_state);
585
586 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
587 "New dequeue segment = %p (virtual)",
588 state->new_deq_seg);
589 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
590 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
591 "New dequeue pointer = 0x%llx (DMA)",
592 (unsigned long long) addr);
593}
594
595
596
597
598
599static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
600 struct xhci_td *td, bool flip_cycle)
601{
602 struct xhci_segment *seg = td->start_seg;
603 union xhci_trb *trb = td->first_trb;
604
605 while (1) {
606 trb_to_noop(trb, TRB_TR_NOOP);
607
608
609 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
610 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
611
612 if (trb == td->last_trb)
613 break;
614
615 next_trb(xhci, ep_ring, &seg, &trb);
616 }
617}
618
619static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
620 struct xhci_virt_ep *ep)
621{
622 ep->ep_state &= ~EP_STOP_CMD_PENDING;
623
624 del_timer(&ep->stop_cmd_timer);
625}
626
627
628
629
630
631static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
632 struct xhci_td *cur_td, int status)
633{
634 struct urb *urb = cur_td->urb;
635 struct urb_priv *urb_priv = urb->hcpriv;
636 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
637
638 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
639 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
640 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
641 if (xhci->quirks & XHCI_AMD_PLL_FIX)
642 usb_amd_quirk_pll_enable();
643 }
644 }
645 xhci_urb_free_priv(urb_priv);
646 usb_hcd_unlink_urb_from_ep(hcd, urb);
647 spin_unlock(&xhci->lock);
648 trace_xhci_urb_giveback(urb);
649 usb_hcd_giveback_urb(hcd, urb, status);
650 spin_lock(&xhci->lock);
651}
652
653static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
654 struct xhci_ring *ring, struct xhci_td *td)
655{
656 struct device *dev = xhci_to_hcd(xhci)->self.controller;
657 struct xhci_segment *seg = td->bounce_seg;
658 struct urb *urb = td->urb;
659
660 if (!ring || !seg || !urb)
661 return;
662
663 if (usb_urb_dir_out(urb)) {
664 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
665 DMA_TO_DEVICE);
666 return;
667 }
668
669
670 sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf,
671 seg->bounce_len, seg->bounce_offs);
672 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
673 DMA_FROM_DEVICE);
674 seg->bounce_len = 0;
675 seg->bounce_offs = 0;
676}
677
678
679
680
681
682
683
684
685
686
687
688static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
689 union xhci_trb *trb, struct xhci_event_cmd *event)
690{
691 unsigned int ep_index;
692 struct xhci_ring *ep_ring;
693 struct xhci_virt_ep *ep;
694 struct xhci_td *cur_td = NULL;
695 struct xhci_td *last_unlinked_td;
696 struct xhci_ep_ctx *ep_ctx;
697 struct xhci_virt_device *vdev;
698 u64 hw_deq;
699 struct xhci_dequeue_state deq_state;
700
701 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
702 if (!xhci->devs[slot_id])
703 xhci_warn(xhci, "Stop endpoint command "
704 "completion for disabled slot %u\n",
705 slot_id);
706 return;
707 }
708
709 memset(&deq_state, 0, sizeof(deq_state));
710 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
711
712 vdev = xhci->devs[slot_id];
713 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
714 trace_xhci_handle_cmd_stop_ep(ep_ctx);
715
716 ep = &xhci->devs[slot_id]->eps[ep_index];
717 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
718 struct xhci_td, cancelled_td_list);
719
720 if (list_empty(&ep->cancelled_td_list)) {
721 xhci_stop_watchdog_timer_in_irq(xhci, ep);
722 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
723 return;
724 }
725
726
727
728
729
730
731 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
732 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
733 "Removing canceled TD starting at 0x%llx (dma).",
734 (unsigned long long)xhci_trb_virt_to_dma(
735 cur_td->start_seg, cur_td->first_trb));
736 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
737 if (!ep_ring) {
738
739
740
741
742
743
744
745
746
747
748
749 xhci_warn(xhci, "WARN Cancelled URB %p "
750 "has invalid stream ID %u.\n",
751 cur_td->urb,
752 cur_td->urb->stream_id);
753 goto remove_finished_td;
754 }
755
756
757
758
759 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
760 cur_td->urb->stream_id);
761 hw_deq &= ~0xf;
762
763 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
764 cur_td->last_trb, hw_deq, false)) {
765 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
766 cur_td->urb->stream_id,
767 cur_td, &deq_state);
768 } else {
769 td_to_noop(xhci, ep_ring, cur_td, false);
770 }
771
772remove_finished_td:
773
774
775
776
777
778 list_del_init(&cur_td->td_list);
779 }
780
781 xhci_stop_watchdog_timer_in_irq(xhci, ep);
782
783
784 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
785 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
786 &deq_state);
787 xhci_ring_cmd_db(xhci);
788 } else {
789
790 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
791 }
792
793
794
795
796
797
798
799 do {
800 cur_td = list_first_entry(&ep->cancelled_td_list,
801 struct xhci_td, cancelled_td_list);
802 list_del_init(&cur_td->cancelled_td_list);
803
804
805
806
807
808 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
809 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
810 inc_td_cnt(cur_td->urb);
811 if (last_td_in_urb(cur_td))
812 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
813
814
815
816
817 if (xhci->xhc_state & XHCI_STATE_DYING)
818 return;
819 } while (cur_td != last_unlinked_td);
820
821
822}
823
824static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
825{
826 struct xhci_td *cur_td;
827 struct xhci_td *tmp;
828
829 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
830 list_del_init(&cur_td->td_list);
831
832 if (!list_empty(&cur_td->cancelled_td_list))
833 list_del_init(&cur_td->cancelled_td_list);
834
835 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
836
837 inc_td_cnt(cur_td->urb);
838 if (last_td_in_urb(cur_td))
839 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
840 }
841}
842
843static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
844 int slot_id, int ep_index)
845{
846 struct xhci_td *cur_td;
847 struct xhci_td *tmp;
848 struct xhci_virt_ep *ep;
849 struct xhci_ring *ring;
850
851 ep = &xhci->devs[slot_id]->eps[ep_index];
852 if ((ep->ep_state & EP_HAS_STREAMS) ||
853 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
854 int stream_id;
855
856 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
857 stream_id++) {
858 ring = ep->stream_info->stream_rings[stream_id];
859 if (!ring)
860 continue;
861
862 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
863 "Killing URBs for slot ID %u, ep index %u, stream %u",
864 slot_id, ep_index, stream_id);
865 xhci_kill_ring_urbs(xhci, ring);
866 }
867 } else {
868 ring = ep->ring;
869 if (!ring)
870 return;
871 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
872 "Killing URBs for slot ID %u, ep index %u",
873 slot_id, ep_index);
874 xhci_kill_ring_urbs(xhci, ring);
875 }
876
877 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
878 cancelled_td_list) {
879 list_del_init(&cur_td->cancelled_td_list);
880 inc_td_cnt(cur_td->urb);
881
882 if (last_td_in_urb(cur_td))
883 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
884 }
885}
886
887
888
889
890
891
892
893
894
895
896void xhci_hc_died(struct xhci_hcd *xhci)
897{
898 int i, j;
899
900 if (xhci->xhc_state & XHCI_STATE_DYING)
901 return;
902
903 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
904 xhci->xhc_state |= XHCI_STATE_DYING;
905
906 xhci_cleanup_command_queue(xhci);
907
908
909 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
910 if (!xhci->devs[i])
911 continue;
912 for (j = 0; j < 31; j++)
913 xhci_kill_endpoint_urbs(xhci, i, j);
914 }
915
916
917 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
918 usb_hc_died(xhci_to_hcd(xhci));
919}
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
939{
940 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
941 struct xhci_hcd *xhci = ep->xhci;
942 unsigned long flags;
943
944 spin_lock_irqsave(&xhci->lock, flags);
945
946
947 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
948 timer_pending(&ep->stop_cmd_timer)) {
949 spin_unlock_irqrestore(&xhci->lock, flags);
950 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
951 return;
952 }
953
954 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
955 ep->ep_state &= ~EP_STOP_CMD_PENDING;
956
957 xhci_halt(xhci);
958
959
960
961
962
963
964 xhci_hc_died(xhci);
965
966 spin_unlock_irqrestore(&xhci->lock, flags);
967 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
968 "xHCI host controller is dead.");
969}
970
971static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
972 struct xhci_virt_device *dev,
973 struct xhci_ring *ep_ring,
974 unsigned int ep_index)
975{
976 union xhci_trb *dequeue_temp;
977 int num_trbs_free_temp;
978 bool revert = false;
979
980 num_trbs_free_temp = ep_ring->num_trbs_free;
981 dequeue_temp = ep_ring->dequeue;
982
983
984
985
986
987
988
989 if (trb_is_link(ep_ring->dequeue)) {
990 ep_ring->deq_seg = ep_ring->deq_seg->next;
991 ep_ring->dequeue = ep_ring->deq_seg->trbs;
992 }
993
994 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
995
996 ep_ring->num_trbs_free++;
997 ep_ring->dequeue++;
998 if (trb_is_link(ep_ring->dequeue)) {
999 if (ep_ring->dequeue ==
1000 dev->eps[ep_index].queued_deq_ptr)
1001 break;
1002 ep_ring->deq_seg = ep_ring->deq_seg->next;
1003 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1004 }
1005 if (ep_ring->dequeue == dequeue_temp) {
1006 revert = true;
1007 break;
1008 }
1009 }
1010
1011 if (revert) {
1012 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1013 ep_ring->num_trbs_free = num_trbs_free_temp;
1014 }
1015}
1016
1017
1018
1019
1020
1021
1022
1023
1024static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1025 union xhci_trb *trb, u32 cmd_comp_code)
1026{
1027 unsigned int ep_index;
1028 unsigned int stream_id;
1029 struct xhci_ring *ep_ring;
1030 struct xhci_virt_device *dev;
1031 struct xhci_virt_ep *ep;
1032 struct xhci_ep_ctx *ep_ctx;
1033 struct xhci_slot_ctx *slot_ctx;
1034
1035 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1036 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1037 dev = xhci->devs[slot_id];
1038 ep = &dev->eps[ep_index];
1039
1040 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1041 if (!ep_ring) {
1042 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1043 stream_id);
1044
1045 goto cleanup;
1046 }
1047
1048 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1049 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1050 trace_xhci_handle_cmd_set_deq(slot_ctx);
1051 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1052
1053 if (cmd_comp_code != COMP_SUCCESS) {
1054 unsigned int ep_state;
1055 unsigned int slot_state;
1056
1057 switch (cmd_comp_code) {
1058 case COMP_TRB_ERROR:
1059 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1060 break;
1061 case COMP_CONTEXT_STATE_ERROR:
1062 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1063 ep_state = GET_EP_CTX_STATE(ep_ctx);
1064 slot_state = le32_to_cpu(slot_ctx->dev_state);
1065 slot_state = GET_SLOT_STATE(slot_state);
1066 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1067 "Slot state = %u, EP state = %u",
1068 slot_state, ep_state);
1069 break;
1070 case COMP_SLOT_NOT_ENABLED_ERROR:
1071 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1072 slot_id);
1073 break;
1074 default:
1075 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1076 cmd_comp_code);
1077 break;
1078 }
1079
1080
1081
1082
1083
1084
1085 } else {
1086 u64 deq;
1087
1088 if (ep->ep_state & EP_HAS_STREAMS) {
1089 struct xhci_stream_ctx *ctx =
1090 &ep->stream_info->stream_ctx_array[stream_id];
1091 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1092 } else {
1093 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1094 }
1095 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1096 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1097 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1098 ep->queued_deq_ptr) == deq) {
1099
1100
1101
1102 update_ring_for_set_deq_completion(xhci, dev,
1103 ep_ring, ep_index);
1104 } else {
1105 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1106 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1107 ep->queued_deq_seg, ep->queued_deq_ptr);
1108 }
1109 }
1110
1111cleanup:
1112 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1113 dev->eps[ep_index].queued_deq_seg = NULL;
1114 dev->eps[ep_index].queued_deq_ptr = NULL;
1115
1116 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1117}
1118
1119static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1120 union xhci_trb *trb, u32 cmd_comp_code)
1121{
1122 struct xhci_virt_device *vdev;
1123 struct xhci_ep_ctx *ep_ctx;
1124 unsigned int ep_index;
1125
1126 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1127 vdev = xhci->devs[slot_id];
1128 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1129 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1130
1131
1132
1133
1134 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1135 "Ignoring reset ep completion code of %u", cmd_comp_code);
1136
1137
1138
1139
1140
1141 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1142 struct xhci_command *command;
1143
1144 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1145 if (!command)
1146 return;
1147
1148 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1149 "Queueing configure endpoint command");
1150 xhci_queue_configure_endpoint(xhci, command,
1151 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1152 false);
1153 xhci_ring_cmd_db(xhci);
1154 } else {
1155
1156 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1157 }
1158}
1159
1160static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1161 struct xhci_command *command, u32 cmd_comp_code)
1162{
1163 if (cmd_comp_code == COMP_SUCCESS)
1164 command->slot_id = slot_id;
1165 else
1166 command->slot_id = 0;
1167}
1168
1169static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1170{
1171 struct xhci_virt_device *virt_dev;
1172 struct xhci_slot_ctx *slot_ctx;
1173
1174 virt_dev = xhci->devs[slot_id];
1175 if (!virt_dev)
1176 return;
1177
1178 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1179 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1180
1181 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1182
1183 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1184 xhci_free_virt_device(xhci, slot_id);
1185}
1186
1187static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1188 struct xhci_event_cmd *event, u32 cmd_comp_code)
1189{
1190 struct xhci_virt_device *virt_dev;
1191 struct xhci_input_control_ctx *ctrl_ctx;
1192 struct xhci_ep_ctx *ep_ctx;
1193 unsigned int ep_index;
1194 unsigned int ep_state;
1195 u32 add_flags, drop_flags;
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205 virt_dev = xhci->devs[slot_id];
1206 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1207 if (!ctrl_ctx) {
1208 xhci_warn(xhci, "Could not get input context, bad type.\n");
1209 return;
1210 }
1211
1212 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1213 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1214
1215 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1216
1217 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1218 trace_xhci_handle_cmd_config_ep(ep_ctx);
1219
1220
1221
1222
1223
1224
1225
1226 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1227 ep_index != (unsigned int) -1 &&
1228 add_flags - SLOT_FLAG == drop_flags) {
1229 ep_state = virt_dev->eps[ep_index].ep_state;
1230 if (!(ep_state & EP_HALTED))
1231 return;
1232 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1233 "Completed config ep cmd - "
1234 "last ep index = %d, state = %d",
1235 ep_index, ep_state);
1236
1237 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1238 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1239 return;
1240 }
1241 return;
1242}
1243
1244static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1245{
1246 struct xhci_virt_device *vdev;
1247 struct xhci_slot_ctx *slot_ctx;
1248
1249 vdev = xhci->devs[slot_id];
1250 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1251 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1252}
1253
1254static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1255 struct xhci_event_cmd *event)
1256{
1257 struct xhci_virt_device *vdev;
1258 struct xhci_slot_ctx *slot_ctx;
1259
1260 vdev = xhci->devs[slot_id];
1261 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1262 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1263
1264 xhci_dbg(xhci, "Completed reset device command.\n");
1265 if (!xhci->devs[slot_id])
1266 xhci_warn(xhci, "Reset device command completion "
1267 "for disabled slot %u\n", slot_id);
1268}
1269
1270static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1271 struct xhci_event_cmd *event)
1272{
1273 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1274 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1275 return;
1276 }
1277 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1278 "NEC firmware version %2x.%02x",
1279 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1280 NEC_FW_MINOR(le32_to_cpu(event->status)));
1281}
1282
1283static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1284{
1285 list_del(&cmd->cmd_list);
1286
1287 if (cmd->completion) {
1288 cmd->status = status;
1289 complete(cmd->completion);
1290 } else {
1291 kfree(cmd);
1292 }
1293}
1294
1295void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1296{
1297 struct xhci_command *cur_cmd, *tmp_cmd;
1298 xhci->current_cmd = NULL;
1299 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1300 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1301}
1302
1303void xhci_handle_command_timeout(struct work_struct *work)
1304{
1305 struct xhci_hcd *xhci;
1306 unsigned long flags;
1307 u64 hw_ring_state;
1308
1309 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1310
1311 spin_lock_irqsave(&xhci->lock, flags);
1312
1313
1314
1315
1316
1317 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1318 spin_unlock_irqrestore(&xhci->lock, flags);
1319 return;
1320 }
1321
1322 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1323
1324
1325 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1326 if (hw_ring_state == ~(u64)0) {
1327 xhci_hc_died(xhci);
1328 goto time_out_completed;
1329 }
1330
1331 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1332 (hw_ring_state & CMD_RING_RUNNING)) {
1333
1334 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1335 xhci_dbg(xhci, "Command timeout\n");
1336 xhci_abort_cmd_ring(xhci, flags);
1337 goto time_out_completed;
1338 }
1339
1340
1341 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1342 xhci_dbg(xhci, "host removed, ring start fail?\n");
1343 xhci_cleanup_command_queue(xhci);
1344
1345 goto time_out_completed;
1346 }
1347
1348
1349 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1350 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1351
1352time_out_completed:
1353 spin_unlock_irqrestore(&xhci->lock, flags);
1354 return;
1355}
1356
1357static void handle_cmd_completion(struct xhci_hcd *xhci,
1358 struct xhci_event_cmd *event)
1359{
1360 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1361 u64 cmd_dma;
1362 dma_addr_t cmd_dequeue_dma;
1363 u32 cmd_comp_code;
1364 union xhci_trb *cmd_trb;
1365 struct xhci_command *cmd;
1366 u32 cmd_type;
1367
1368 cmd_dma = le64_to_cpu(event->cmd_trb);
1369 cmd_trb = xhci->cmd_ring->dequeue;
1370
1371 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1372
1373 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1374 cmd_trb);
1375
1376
1377
1378
1379 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1380 xhci_warn(xhci,
1381 "ERROR mismatched command completion event\n");
1382 return;
1383 }
1384
1385 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1386
1387 cancel_delayed_work(&xhci->cmd_timer);
1388
1389 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1390
1391
1392 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1393 complete_all(&xhci->cmd_ring_stop_completion);
1394 return;
1395 }
1396
1397 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1398 xhci_err(xhci,
1399 "Command completion event does not match command\n");
1400 return;
1401 }
1402
1403
1404
1405
1406
1407
1408
1409 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1410 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1411 if (cmd->status == COMP_COMMAND_ABORTED) {
1412 if (xhci->current_cmd == cmd)
1413 xhci->current_cmd = NULL;
1414 goto event_handled;
1415 }
1416 }
1417
1418 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1419 switch (cmd_type) {
1420 case TRB_ENABLE_SLOT:
1421 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1422 break;
1423 case TRB_DISABLE_SLOT:
1424 xhci_handle_cmd_disable_slot(xhci, slot_id);
1425 break;
1426 case TRB_CONFIG_EP:
1427 if (!cmd->completion)
1428 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1429 cmd_comp_code);
1430 break;
1431 case TRB_EVAL_CONTEXT:
1432 break;
1433 case TRB_ADDR_DEV:
1434 xhci_handle_cmd_addr_dev(xhci, slot_id);
1435 break;
1436 case TRB_STOP_RING:
1437 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1438 le32_to_cpu(cmd_trb->generic.field[3])));
1439 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1440 break;
1441 case TRB_SET_DEQ:
1442 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1443 le32_to_cpu(cmd_trb->generic.field[3])));
1444 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1445 break;
1446 case TRB_CMD_NOOP:
1447
1448 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1449 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1450 break;
1451 case TRB_RESET_EP:
1452 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1453 le32_to_cpu(cmd_trb->generic.field[3])));
1454 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1455 break;
1456 case TRB_RESET_DEV:
1457
1458
1459
1460 slot_id = TRB_TO_SLOT_ID(
1461 le32_to_cpu(cmd_trb->generic.field[3]));
1462 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1463 break;
1464 case TRB_NEC_GET_FW:
1465 xhci_handle_cmd_nec_get_fw(xhci, event);
1466 break;
1467 default:
1468
1469 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1470 break;
1471 }
1472
1473
1474 if (!list_is_singular(&xhci->cmd_list)) {
1475 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1476 struct xhci_command, cmd_list);
1477 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1478 } else if (xhci->current_cmd == cmd) {
1479 xhci->current_cmd = NULL;
1480 }
1481
1482event_handled:
1483 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1484
1485 inc_deq(xhci, xhci->cmd_ring);
1486}
1487
1488static void handle_vendor_event(struct xhci_hcd *xhci,
1489 union xhci_trb *event)
1490{
1491 u32 trb_type;
1492
1493 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1494 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1495 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1496 handle_cmd_completion(xhci, &event->event_cmd);
1497}
1498
1499
1500
1501
1502
1503
1504
1505
1506static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1507 struct xhci_hcd *xhci, u32 port_id)
1508{
1509 unsigned int i;
1510 unsigned int num_similar_speed_ports = 0;
1511
1512
1513
1514
1515
1516 for (i = 0; i < (port_id - 1); i++) {
1517 u8 port_speed = xhci->port_array[i];
1518
1519
1520
1521
1522
1523 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1524 continue;
1525
1526
1527
1528
1529
1530
1531 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
1532 num_similar_speed_ports++;
1533 }
1534 return num_similar_speed_ports;
1535}
1536
1537static void handle_device_notification(struct xhci_hcd *xhci,
1538 union xhci_trb *event)
1539{
1540 u32 slot_id;
1541 struct usb_device *udev;
1542
1543 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1544 if (!xhci->devs[slot_id]) {
1545 xhci_warn(xhci, "Device Notification event for "
1546 "unused slot %u\n", slot_id);
1547 return;
1548 }
1549
1550 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1551 slot_id);
1552 udev = xhci->devs[slot_id]->udev;
1553 if (udev && udev->parent)
1554 usb_wakeup_notification(udev->parent, udev->portnum);
1555}
1556
1557static void handle_port_status(struct xhci_hcd *xhci,
1558 union xhci_trb *event)
1559{
1560 struct usb_hcd *hcd;
1561 u32 port_id;
1562 u32 portsc, cmd_reg;
1563 int max_ports;
1564 int slot_id;
1565 unsigned int faked_port_index;
1566 u8 major_revision;
1567 struct xhci_bus_state *bus_state;
1568 __le32 __iomem **port_array;
1569 bool bogus_port_status = false;
1570
1571
1572 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1573 xhci_warn(xhci,
1574 "WARN: xHC returned failed port status event\n");
1575
1576 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1577 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1578
1579 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1580 if ((port_id <= 0) || (port_id > max_ports)) {
1581 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1582 inc_deq(xhci, xhci->event_ring);
1583 return;
1584 }
1585
1586
1587
1588
1589 major_revision = xhci->port_array[port_id - 1];
1590
1591
1592 hcd = xhci_to_hcd(xhci);
1593 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
1594 hcd = xhci->shared_hcd;
1595
1596 if (major_revision == 0) {
1597 xhci_warn(xhci, "Event for port %u not in "
1598 "Extended Capabilities, ignoring.\n",
1599 port_id);
1600 bogus_port_status = true;
1601 goto cleanup;
1602 }
1603 if (major_revision == DUPLICATE_ENTRY) {
1604 xhci_warn(xhci, "Event for port %u duplicated in"
1605 "Extended Capabilities, ignoring.\n",
1606 port_id);
1607 bogus_port_status = true;
1608 goto cleanup;
1609 }
1610
1611
1612
1613
1614
1615
1616
1617
1618 bus_state = &xhci->bus_state[hcd_index(hcd)];
1619 if (hcd->speed >= HCD_USB3)
1620 port_array = xhci->usb3_ports;
1621 else
1622 port_array = xhci->usb2_ports;
1623
1624 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1625 port_id);
1626 portsc = readl(port_array[faked_port_index]);
1627
1628 trace_xhci_handle_port_status(faked_port_index, portsc);
1629
1630 if (hcd->state == HC_STATE_SUSPENDED) {
1631 xhci_dbg(xhci, "resume root hub\n");
1632 usb_hcd_resume_root_hub(hcd);
1633 }
1634
1635 if (hcd->speed >= HCD_USB3 && (portsc & PORT_PLS_MASK) == XDEV_INACTIVE)
1636 bus_state->port_remote_wakeup &= ~(1 << faked_port_index);
1637
1638 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1639 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1640
1641 cmd_reg = readl(&xhci->op_regs->command);
1642 if (!(cmd_reg & CMD_RUN)) {
1643 xhci_warn(xhci, "xHC is not running.\n");
1644 goto cleanup;
1645 }
1646
1647 if (DEV_SUPERSPEED_ANY(portsc)) {
1648 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1649
1650
1651
1652
1653 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1654 xhci_test_and_clear_bit(xhci, port_array,
1655 faked_port_index, PORT_PLC);
1656 xhci_set_link_state(xhci, port_array, faked_port_index,
1657 XDEV_U0);
1658
1659
1660
1661 bogus_port_status = true;
1662 goto cleanup;
1663 } else if (!test_bit(faked_port_index,
1664 &bus_state->resuming_ports)) {
1665 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1666 bus_state->resume_done[faked_port_index] = jiffies +
1667 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1668 set_bit(faked_port_index, &bus_state->resuming_ports);
1669
1670
1671
1672
1673 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1674 mod_timer(&hcd->rh_timer,
1675 bus_state->resume_done[faked_port_index]);
1676 bogus_port_status = true;
1677 }
1678 }
1679
1680 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_U0 &&
1681 DEV_SUPERSPEED_ANY(portsc)) {
1682 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1683
1684
1685
1686
1687
1688
1689
1690 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1691 faked_port_index + 1);
1692 if (slot_id && xhci->devs[slot_id])
1693 xhci_ring_device(xhci, slot_id);
1694 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1695 bus_state->port_remote_wakeup &=
1696 ~(1 << faked_port_index);
1697 xhci_test_and_clear_bit(xhci, port_array,
1698 faked_port_index, PORT_PLC);
1699 usb_wakeup_notification(hcd->self.root_hub,
1700 faked_port_index + 1);
1701 bogus_port_status = true;
1702 goto cleanup;
1703 }
1704 }
1705
1706
1707
1708
1709
1710
1711 if (!DEV_SUPERSPEED_ANY(portsc) &&
1712 test_and_clear_bit(faked_port_index,
1713 &bus_state->rexit_ports)) {
1714 complete(&bus_state->rexit_done[faked_port_index]);
1715 bogus_port_status = true;
1716 goto cleanup;
1717 }
1718
1719 if (hcd->speed < HCD_USB3)
1720 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1721 PORT_PLC);
1722
1723cleanup:
1724
1725 inc_deq(xhci, xhci->event_ring);
1726
1727
1728
1729
1730
1731 if (bogus_port_status)
1732 return;
1733
1734
1735
1736
1737
1738
1739
1740
1741 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1742 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1743 spin_unlock(&xhci->lock);
1744
1745 usb_hcd_poll_rh_status(hcd);
1746 spin_lock(&xhci->lock);
1747}
1748
1749
1750
1751
1752
1753
1754
1755struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1756 struct xhci_segment *start_seg,
1757 union xhci_trb *start_trb,
1758 union xhci_trb *end_trb,
1759 dma_addr_t suspect_dma,
1760 bool debug)
1761{
1762 dma_addr_t start_dma;
1763 dma_addr_t end_seg_dma;
1764 dma_addr_t end_trb_dma;
1765 struct xhci_segment *cur_seg;
1766
1767 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1768 cur_seg = start_seg;
1769
1770 do {
1771 if (start_dma == 0)
1772 return NULL;
1773
1774 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1775 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1776
1777 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1778
1779 if (debug)
1780 xhci_warn(xhci,
1781 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1782 (unsigned long long)suspect_dma,
1783 (unsigned long long)start_dma,
1784 (unsigned long long)end_trb_dma,
1785 (unsigned long long)cur_seg->dma,
1786 (unsigned long long)end_seg_dma);
1787
1788 if (end_trb_dma > 0) {
1789
1790 if (start_dma <= end_trb_dma) {
1791 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1792 return cur_seg;
1793 } else {
1794
1795
1796
1797 if ((suspect_dma >= start_dma &&
1798 suspect_dma <= end_seg_dma) ||
1799 (suspect_dma >= cur_seg->dma &&
1800 suspect_dma <= end_trb_dma))
1801 return cur_seg;
1802 }
1803 return NULL;
1804 } else {
1805
1806 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1807 return cur_seg;
1808 }
1809 cur_seg = cur_seg->next;
1810 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1811 } while (cur_seg != start_seg);
1812
1813 return NULL;
1814}
1815
1816static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1817 unsigned int slot_id, unsigned int ep_index,
1818 unsigned int stream_id,
1819 struct xhci_td *td, union xhci_trb *ep_trb,
1820 enum xhci_ep_reset_type reset_type)
1821{
1822 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1823 struct xhci_command *command;
1824 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1825 if (!command)
1826 return;
1827
1828 ep->ep_state |= EP_HALTED;
1829
1830 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1831
1832 if (reset_type == EP_HARD_RESET)
1833 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1834
1835 xhci_ring_cmd_db(xhci);
1836}
1837
1838
1839
1840
1841
1842
1843
1844static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1845 struct xhci_ep_ctx *ep_ctx,
1846 unsigned int trb_comp_code)
1847{
1848
1849 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1850 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1851 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1852
1853
1854
1855
1856
1857
1858 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1859 return 1;
1860
1861 return 0;
1862}
1863
1864int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1865{
1866 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1867
1868
1869
1870 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1871 trb_comp_code);
1872 xhci_dbg(xhci, "Treating code as success.\n");
1873 return 1;
1874 }
1875 return 0;
1876}
1877
1878static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1879 struct xhci_ring *ep_ring, int *status)
1880{
1881 struct urb_priv *urb_priv;
1882 struct urb *urb = NULL;
1883
1884
1885 urb = td->urb;
1886 urb_priv = urb->hcpriv;
1887
1888
1889 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1890
1891
1892
1893
1894
1895
1896 if (urb->actual_length > urb->transfer_buffer_length) {
1897 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1898 urb->transfer_buffer_length, urb->actual_length);
1899 urb->actual_length = 0;
1900 *status = 0;
1901 }
1902 list_del_init(&td->td_list);
1903
1904 if (!list_empty(&td->cancelled_td_list))
1905 list_del_init(&td->cancelled_td_list);
1906
1907 inc_td_cnt(urb);
1908
1909 if (last_td_in_urb(td)) {
1910 if ((urb->actual_length != urb->transfer_buffer_length &&
1911 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1912 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1913 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1914 urb, urb->actual_length,
1915 urb->transfer_buffer_length, *status);
1916
1917
1918 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1919 *status = 0;
1920 xhci_giveback_urb_in_irq(xhci, td, *status);
1921 }
1922
1923 return 0;
1924}
1925
1926static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1927 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
1928 struct xhci_virt_ep *ep, int *status)
1929{
1930 struct xhci_virt_device *xdev;
1931 struct xhci_ep_ctx *ep_ctx;
1932 struct xhci_ring *ep_ring;
1933 unsigned int slot_id;
1934 u32 trb_comp_code;
1935 int ep_index;
1936
1937 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1938 xdev = xhci->devs[slot_id];
1939 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1940 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1941 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1942 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1943
1944 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1945 trb_comp_code == COMP_STOPPED ||
1946 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1947
1948
1949
1950
1951 return 0;
1952 }
1953 if (trb_comp_code == COMP_STALL_ERROR ||
1954 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1955 trb_comp_code)) {
1956
1957
1958
1959
1960
1961 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1962 ep_ring->stream_id, td, ep_trb,
1963 EP_HARD_RESET);
1964 } else {
1965
1966 while (ep_ring->dequeue != td->last_trb)
1967 inc_deq(xhci, ep_ring);
1968 inc_deq(xhci, ep_ring);
1969 }
1970
1971 return xhci_td_cleanup(xhci, td, ep_ring, status);
1972}
1973
1974
1975static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
1976 union xhci_trb *stop_trb)
1977{
1978 u32 sum;
1979 union xhci_trb *trb = ring->dequeue;
1980 struct xhci_segment *seg = ring->deq_seg;
1981
1982 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
1983 if (!trb_is_noop(trb) && !trb_is_link(trb))
1984 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
1985 }
1986 return sum;
1987}
1988
1989
1990
1991
1992static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1993 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
1994 struct xhci_virt_ep *ep, int *status)
1995{
1996 struct xhci_virt_device *xdev;
1997 struct xhci_ring *ep_ring;
1998 unsigned int slot_id;
1999 int ep_index;
2000 struct xhci_ep_ctx *ep_ctx;
2001 u32 trb_comp_code;
2002 u32 remaining, requested;
2003 u32 trb_type;
2004
2005 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2006 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2007 xdev = xhci->devs[slot_id];
2008 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2009 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2010 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2011 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2012 requested = td->urb->transfer_buffer_length;
2013 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2014
2015 switch (trb_comp_code) {
2016 case COMP_SUCCESS:
2017 if (trb_type != TRB_STATUS) {
2018 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2019 (trb_type == TRB_DATA) ? "data" : "setup");
2020 *status = -ESHUTDOWN;
2021 break;
2022 }
2023 *status = 0;
2024 break;
2025 case COMP_SHORT_PACKET:
2026 *status = 0;
2027 break;
2028 case COMP_STOPPED_SHORT_PACKET:
2029 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2030 td->urb->actual_length = remaining;
2031 else
2032 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2033 goto finish_td;
2034 case COMP_STOPPED:
2035 switch (trb_type) {
2036 case TRB_SETUP:
2037 td->urb->actual_length = 0;
2038 goto finish_td;
2039 case TRB_DATA:
2040 case TRB_NORMAL:
2041 td->urb->actual_length = requested - remaining;
2042 goto finish_td;
2043 case TRB_STATUS:
2044 td->urb->actual_length = requested;
2045 goto finish_td;
2046 default:
2047 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2048 trb_type);
2049 goto finish_td;
2050 }
2051 case COMP_STOPPED_LENGTH_INVALID:
2052 goto finish_td;
2053 default:
2054 if (!xhci_requires_manual_halt_cleanup(xhci,
2055 ep_ctx, trb_comp_code))
2056 break;
2057 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2058 trb_comp_code, ep_index);
2059
2060 case COMP_STALL_ERROR:
2061
2062 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2063 td->urb->actual_length = requested - remaining;
2064 else if (!td->urb_length_set)
2065 td->urb->actual_length = 0;
2066 goto finish_td;
2067 }
2068
2069
2070 if (trb_type == TRB_SETUP)
2071 goto finish_td;
2072
2073
2074
2075
2076
2077 if (trb_type == TRB_DATA ||
2078 trb_type == TRB_NORMAL) {
2079 td->urb_length_set = true;
2080 td->urb->actual_length = requested - remaining;
2081 xhci_dbg(xhci, "Waiting for status stage event\n");
2082 return 0;
2083 }
2084
2085
2086 if (!td->urb_length_set)
2087 td->urb->actual_length = requested;
2088
2089finish_td:
2090 return finish_td(xhci, td, ep_trb, event, ep, status);
2091}
2092
2093
2094
2095
2096static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2097 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2098 struct xhci_virt_ep *ep, int *status)
2099{
2100 struct xhci_ring *ep_ring;
2101 struct urb_priv *urb_priv;
2102 int idx;
2103 struct usb_iso_packet_descriptor *frame;
2104 u32 trb_comp_code;
2105 bool sum_trbs_for_length = false;
2106 u32 remaining, requested, ep_trb_len;
2107 int short_framestatus;
2108
2109 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2110 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2111 urb_priv = td->urb->hcpriv;
2112 idx = urb_priv->num_tds_done;
2113 frame = &td->urb->iso_frame_desc[idx];
2114 requested = frame->length;
2115 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2116 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2117 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2118 -EREMOTEIO : 0;
2119
2120
2121 switch (trb_comp_code) {
2122 case COMP_SUCCESS:
2123 if (remaining) {
2124 frame->status = short_framestatus;
2125 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2126 sum_trbs_for_length = true;
2127 break;
2128 }
2129 frame->status = 0;
2130 break;
2131 case COMP_SHORT_PACKET:
2132 frame->status = short_framestatus;
2133 sum_trbs_for_length = true;
2134 break;
2135 case COMP_BANDWIDTH_OVERRUN_ERROR:
2136 frame->status = -ECOMM;
2137 break;
2138 case COMP_ISOCH_BUFFER_OVERRUN:
2139 case COMP_BABBLE_DETECTED_ERROR:
2140 frame->status = -EOVERFLOW;
2141 break;
2142 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2143 case COMP_STALL_ERROR:
2144 frame->status = -EPROTO;
2145 break;
2146 case COMP_USB_TRANSACTION_ERROR:
2147 frame->status = -EPROTO;
2148 if (ep_trb != td->last_trb)
2149 return 0;
2150 break;
2151 case COMP_STOPPED:
2152 sum_trbs_for_length = true;
2153 break;
2154 case COMP_STOPPED_SHORT_PACKET:
2155
2156 frame->status = short_framestatus;
2157 requested = remaining;
2158 break;
2159 case COMP_STOPPED_LENGTH_INVALID:
2160 requested = 0;
2161 remaining = 0;
2162 break;
2163 default:
2164 sum_trbs_for_length = true;
2165 frame->status = -1;
2166 break;
2167 }
2168
2169 if (sum_trbs_for_length)
2170 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2171 ep_trb_len - remaining;
2172 else
2173 frame->actual_length = requested;
2174
2175 td->urb->actual_length += frame->actual_length;
2176
2177 return finish_td(xhci, td, ep_trb, event, ep, status);
2178}
2179
2180static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2181 struct xhci_transfer_event *event,
2182 struct xhci_virt_ep *ep, int *status)
2183{
2184 struct xhci_ring *ep_ring;
2185 struct urb_priv *urb_priv;
2186 struct usb_iso_packet_descriptor *frame;
2187 int idx;
2188
2189 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2190 urb_priv = td->urb->hcpriv;
2191 idx = urb_priv->num_tds_done;
2192 frame = &td->urb->iso_frame_desc[idx];
2193
2194
2195 frame->status = -EXDEV;
2196
2197
2198 frame->actual_length = 0;
2199
2200
2201 while (ep_ring->dequeue != td->last_trb)
2202 inc_deq(xhci, ep_ring);
2203 inc_deq(xhci, ep_ring);
2204
2205 return xhci_td_cleanup(xhci, td, ep_ring, status);
2206}
2207
2208
2209
2210
2211static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2212 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2213 struct xhci_virt_ep *ep, int *status)
2214{
2215 struct xhci_ring *ep_ring;
2216 u32 trb_comp_code;
2217 u32 remaining, requested, ep_trb_len;
2218
2219 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2220 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2221 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2222 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2223 requested = td->urb->transfer_buffer_length;
2224
2225 switch (trb_comp_code) {
2226 case COMP_SUCCESS:
2227
2228 if (ep_trb != td->last_trb || remaining) {
2229 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2230 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2231 td->urb->ep->desc.bEndpointAddress,
2232 requested, remaining);
2233 }
2234 *status = 0;
2235 break;
2236 case COMP_SHORT_PACKET:
2237 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2238 td->urb->ep->desc.bEndpointAddress,
2239 requested, remaining);
2240 *status = 0;
2241 break;
2242 case COMP_STOPPED_SHORT_PACKET:
2243 td->urb->actual_length = remaining;
2244 goto finish_td;
2245 case COMP_STOPPED_LENGTH_INVALID:
2246
2247 ep_trb_len = 0;
2248 remaining = 0;
2249 break;
2250 default:
2251
2252 break;
2253 }
2254
2255 if (ep_trb == td->last_trb)
2256 td->urb->actual_length = requested - remaining;
2257 else
2258 td->urb->actual_length =
2259 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2260 ep_trb_len - remaining;
2261finish_td:
2262 if (remaining > requested) {
2263 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2264 remaining);
2265 td->urb->actual_length = 0;
2266 }
2267 return finish_td(xhci, td, ep_trb, event, ep, status);
2268}
2269
2270
2271
2272
2273
2274
2275static int handle_tx_event(struct xhci_hcd *xhci,
2276 struct xhci_transfer_event *event)
2277{
2278 struct xhci_virt_device *xdev;
2279 struct xhci_virt_ep *ep;
2280 struct xhci_ring *ep_ring;
2281 unsigned int slot_id;
2282 int ep_index;
2283 struct xhci_td *td = NULL;
2284 dma_addr_t ep_trb_dma;
2285 struct xhci_segment *ep_seg;
2286 union xhci_trb *ep_trb;
2287 int status = -EINPROGRESS;
2288 struct xhci_ep_ctx *ep_ctx;
2289 struct list_head *tmp;
2290 u32 trb_comp_code;
2291 int td_num = 0;
2292 bool handling_skipped_tds = false;
2293
2294 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2295 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2296 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2297 ep_trb_dma = le64_to_cpu(event->buffer);
2298
2299 xdev = xhci->devs[slot_id];
2300 if (!xdev) {
2301 xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n",
2302 slot_id);
2303 goto err_out;
2304 }
2305
2306 ep = &xdev->eps[ep_index];
2307 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2308 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2309
2310 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2311 xhci_err(xhci,
2312 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2313 slot_id, ep_index);
2314 goto err_out;
2315 }
2316
2317
2318 if (!ep_ring) {
2319 switch (trb_comp_code) {
2320 case COMP_STALL_ERROR:
2321 case COMP_USB_TRANSACTION_ERROR:
2322 case COMP_INVALID_STREAM_TYPE_ERROR:
2323 case COMP_INVALID_STREAM_ID_ERROR:
2324 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2325 NULL, NULL, EP_SOFT_RESET);
2326 goto cleanup;
2327 case COMP_RING_UNDERRUN:
2328 case COMP_RING_OVERRUN:
2329 goto cleanup;
2330 default:
2331 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2332 slot_id, ep_index);
2333 goto err_out;
2334 }
2335 }
2336
2337
2338 if (ep->skip) {
2339 list_for_each(tmp, &ep_ring->td_list)
2340 td_num++;
2341 }
2342
2343
2344 switch (trb_comp_code) {
2345
2346
2347
2348 case COMP_SUCCESS:
2349 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2350 break;
2351 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2352 trb_comp_code = COMP_SHORT_PACKET;
2353 else
2354 xhci_warn_ratelimited(xhci,
2355 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2356 slot_id, ep_index);
2357 case COMP_SHORT_PACKET:
2358 break;
2359
2360 case COMP_STOPPED:
2361 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2362 slot_id, ep_index);
2363 break;
2364 case COMP_STOPPED_LENGTH_INVALID:
2365 xhci_dbg(xhci,
2366 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2367 slot_id, ep_index);
2368 break;
2369 case COMP_STOPPED_SHORT_PACKET:
2370 xhci_dbg(xhci,
2371 "Stopped with short packet transfer detected for slot %u ep %u\n",
2372 slot_id, ep_index);
2373 break;
2374
2375 case COMP_STALL_ERROR:
2376 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2377 ep_index);
2378 ep->ep_state |= EP_HALTED;
2379 status = -EPIPE;
2380 break;
2381 case COMP_SPLIT_TRANSACTION_ERROR:
2382 case COMP_USB_TRANSACTION_ERROR:
2383 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2384 slot_id, ep_index);
2385 status = -EPROTO;
2386 break;
2387 case COMP_BABBLE_DETECTED_ERROR:
2388 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2389 slot_id, ep_index);
2390 status = -EOVERFLOW;
2391 break;
2392
2393 case COMP_TRB_ERROR:
2394 xhci_warn(xhci,
2395 "WARN: TRB error for slot %u ep %u on endpoint\n",
2396 slot_id, ep_index);
2397 status = -EILSEQ;
2398 break;
2399
2400 case COMP_DATA_BUFFER_ERROR:
2401 xhci_warn(xhci,
2402 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2403 slot_id, ep_index);
2404 status = -ENOSR;
2405 break;
2406 case COMP_BANDWIDTH_OVERRUN_ERROR:
2407 xhci_warn(xhci,
2408 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2409 slot_id, ep_index);
2410 break;
2411 case COMP_ISOCH_BUFFER_OVERRUN:
2412 xhci_warn(xhci,
2413 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2414 slot_id, ep_index);
2415 break;
2416 case COMP_RING_UNDERRUN:
2417
2418
2419
2420
2421
2422 xhci_dbg(xhci, "underrun event on endpoint\n");
2423 if (!list_empty(&ep_ring->td_list))
2424 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2425 "still with TDs queued?\n",
2426 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2427 ep_index);
2428 goto cleanup;
2429 case COMP_RING_OVERRUN:
2430 xhci_dbg(xhci, "overrun event on endpoint\n");
2431 if (!list_empty(&ep_ring->td_list))
2432 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2433 "still with TDs queued?\n",
2434 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2435 ep_index);
2436 goto cleanup;
2437 case COMP_MISSED_SERVICE_ERROR:
2438
2439
2440
2441
2442
2443
2444 ep->skip = true;
2445 xhci_dbg(xhci,
2446 "Miss service interval error for slot %u ep %u, set skip flag\n",
2447 slot_id, ep_index);
2448 goto cleanup;
2449 case COMP_NO_PING_RESPONSE_ERROR:
2450 ep->skip = true;
2451 xhci_dbg(xhci,
2452 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2453 slot_id, ep_index);
2454 goto cleanup;
2455
2456 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2457
2458 xhci_warn(xhci,
2459 "WARN: detect an incompatible device for slot %u ep %u",
2460 slot_id, ep_index);
2461 status = -EPROTO;
2462 break;
2463 default:
2464 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2465 status = 0;
2466 break;
2467 }
2468 xhci_warn(xhci,
2469 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2470 trb_comp_code, slot_id, ep_index);
2471 goto cleanup;
2472 }
2473
2474 do {
2475
2476
2477
2478 if (list_empty(&ep_ring->td_list)) {
2479
2480
2481
2482
2483
2484
2485
2486
2487 if (!(trb_comp_code == COMP_STOPPED ||
2488 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2489 ep_ring->last_td_was_short)) {
2490 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2491 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2492 ep_index);
2493 }
2494 if (ep->skip) {
2495 ep->skip = false;
2496 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2497 slot_id, ep_index);
2498 }
2499 goto cleanup;
2500 }
2501
2502
2503 if (ep->skip && td_num == 0) {
2504 ep->skip = false;
2505 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2506 slot_id, ep_index);
2507 goto cleanup;
2508 }
2509
2510 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2511 td_list);
2512 if (ep->skip)
2513 td_num--;
2514
2515
2516 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2517 td->last_trb, ep_trb_dma, false);
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2528 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2529 goto cleanup;
2530 }
2531
2532 if (!ep_seg) {
2533 if (!ep->skip ||
2534 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2535
2536
2537
2538
2539 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2540 ep_ring->last_td_was_short) {
2541 ep_ring->last_td_was_short = false;
2542 goto cleanup;
2543 }
2544
2545 xhci_err(xhci,
2546 "ERROR Transfer event TRB DMA ptr not "
2547 "part of current TD ep_index %d "
2548 "comp_code %u\n", ep_index,
2549 trb_comp_code);
2550 trb_in_td(xhci, ep_ring->deq_seg,
2551 ep_ring->dequeue, td->last_trb,
2552 ep_trb_dma, true);
2553 return -ESHUTDOWN;
2554 }
2555
2556 skip_isoc_td(xhci, td, event, ep, &status);
2557 goto cleanup;
2558 }
2559 if (trb_comp_code == COMP_SHORT_PACKET)
2560 ep_ring->last_td_was_short = true;
2561 else
2562 ep_ring->last_td_was_short = false;
2563
2564 if (ep->skip) {
2565 xhci_dbg(xhci,
2566 "Found td. Clear skip flag for slot %u ep %u.\n",
2567 slot_id, ep_index);
2568 ep->skip = false;
2569 }
2570
2571 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2572 sizeof(*ep_trb)];
2573
2574 trace_xhci_handle_transfer(ep_ring,
2575 (struct xhci_generic_trb *) ep_trb);
2576
2577
2578
2579
2580
2581
2582
2583
2584 if (trb_is_noop(ep_trb)) {
2585 if (trb_comp_code == COMP_STALL_ERROR ||
2586 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2587 trb_comp_code))
2588 xhci_cleanup_halted_endpoint(xhci, slot_id,
2589 ep_index,
2590 ep_ring->stream_id,
2591 td, ep_trb,
2592 EP_HARD_RESET);
2593 goto cleanup;
2594 }
2595
2596
2597 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2598 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2599 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2600 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2601 else
2602 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2603 &status);
2604cleanup:
2605 handling_skipped_tds = ep->skip &&
2606 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2607 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2608
2609
2610
2611
2612
2613 if (!handling_skipped_tds)
2614 inc_deq(xhci, xhci->event_ring);
2615
2616
2617
2618
2619
2620
2621
2622 } while (handling_skipped_tds);
2623
2624 return 0;
2625
2626err_out:
2627 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2628 (unsigned long long) xhci_trb_virt_to_dma(
2629 xhci->event_ring->deq_seg,
2630 xhci->event_ring->dequeue),
2631 lower_32_bits(le64_to_cpu(event->buffer)),
2632 upper_32_bits(le64_to_cpu(event->buffer)),
2633 le32_to_cpu(event->transfer_len),
2634 le32_to_cpu(event->flags));
2635 return -ENODEV;
2636}
2637
2638
2639
2640
2641
2642
2643
2644static int xhci_handle_event(struct xhci_hcd *xhci)
2645{
2646 union xhci_trb *event;
2647 int update_ptrs = 1;
2648 int ret;
2649
2650
2651 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2652 xhci_err(xhci, "ERROR event ring not ready\n");
2653 return -ENOMEM;
2654 }
2655
2656 event = xhci->event_ring->dequeue;
2657
2658 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2659 xhci->event_ring->cycle_state)
2660 return 0;
2661
2662 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2663
2664
2665
2666
2667
2668 rmb();
2669
2670 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2671 case TRB_TYPE(TRB_COMPLETION):
2672 handle_cmd_completion(xhci, &event->event_cmd);
2673 break;
2674 case TRB_TYPE(TRB_PORT_STATUS):
2675 handle_port_status(xhci, event);
2676 update_ptrs = 0;
2677 break;
2678 case TRB_TYPE(TRB_TRANSFER):
2679 ret = handle_tx_event(xhci, &event->trans_event);
2680 if (ret >= 0)
2681 update_ptrs = 0;
2682 break;
2683 case TRB_TYPE(TRB_DEV_NOTE):
2684 handle_device_notification(xhci, event);
2685 break;
2686 default:
2687 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2688 TRB_TYPE(48))
2689 handle_vendor_event(xhci, event);
2690 else
2691 xhci_warn(xhci, "ERROR unknown event type %d\n",
2692 TRB_FIELD_TO_TYPE(
2693 le32_to_cpu(event->event_cmd.flags)));
2694 }
2695
2696
2697
2698 if (xhci->xhc_state & XHCI_STATE_DYING) {
2699 xhci_dbg(xhci, "xHCI host dying, returning from "
2700 "event handler.\n");
2701 return 0;
2702 }
2703
2704 if (update_ptrs)
2705
2706 inc_deq(xhci, xhci->event_ring);
2707
2708
2709
2710
2711 return 1;
2712}
2713
2714
2715
2716
2717
2718
2719irqreturn_t xhci_irq(struct usb_hcd *hcd)
2720{
2721 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2722 union xhci_trb *event_ring_deq;
2723 irqreturn_t ret = IRQ_NONE;
2724 unsigned long flags;
2725 dma_addr_t deq;
2726 u64 temp_64;
2727 u32 status;
2728
2729 spin_lock_irqsave(&xhci->lock, flags);
2730
2731 status = readl(&xhci->op_regs->status);
2732 if (status == ~(u32)0) {
2733 xhci_hc_died(xhci);
2734 ret = IRQ_HANDLED;
2735 goto out;
2736 }
2737
2738 if (!(status & STS_EINT))
2739 goto out;
2740
2741 if (status & STS_FATAL) {
2742 xhci_warn(xhci, "WARNING: Host System Error\n");
2743 xhci_halt(xhci);
2744 ret = IRQ_HANDLED;
2745 goto out;
2746 }
2747
2748
2749
2750
2751
2752
2753 status |= STS_EINT;
2754 writel(status, &xhci->op_regs->status);
2755
2756 if (!hcd->msi_enabled) {
2757 u32 irq_pending;
2758 irq_pending = readl(&xhci->ir_set->irq_pending);
2759 irq_pending |= IMAN_IP;
2760 writel(irq_pending, &xhci->ir_set->irq_pending);
2761 }
2762
2763 if (xhci->xhc_state & XHCI_STATE_DYING ||
2764 xhci->xhc_state & XHCI_STATE_HALTED) {
2765 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2766 "Shouldn't IRQs be disabled?\n");
2767
2768
2769
2770 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2771 xhci_write_64(xhci, temp_64 | ERST_EHB,
2772 &xhci->ir_set->erst_dequeue);
2773 ret = IRQ_HANDLED;
2774 goto out;
2775 }
2776
2777 event_ring_deq = xhci->event_ring->dequeue;
2778
2779
2780
2781 while (xhci_handle_event(xhci) > 0) {}
2782
2783 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2784
2785 if (event_ring_deq != xhci->event_ring->dequeue) {
2786 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2787 xhci->event_ring->dequeue);
2788 if (deq == 0)
2789 xhci_warn(xhci, "WARN something wrong with SW event "
2790 "ring dequeue ptr.\n");
2791
2792 temp_64 &= ERST_PTR_MASK;
2793 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2794 }
2795
2796
2797 temp_64 |= ERST_EHB;
2798 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2799 ret = IRQ_HANDLED;
2800
2801out:
2802 spin_unlock_irqrestore(&xhci->lock, flags);
2803
2804 return ret;
2805}
2806
2807irqreturn_t xhci_msi_irq(int irq, void *hcd)
2808{
2809 return xhci_irq(hcd);
2810}
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2822 bool more_trbs_coming,
2823 u32 field1, u32 field2, u32 field3, u32 field4)
2824{
2825 struct xhci_generic_trb *trb;
2826
2827 trb = &ring->enqueue->generic;
2828 trb->field[0] = cpu_to_le32(field1);
2829 trb->field[1] = cpu_to_le32(field2);
2830 trb->field[2] = cpu_to_le32(field3);
2831 trb->field[3] = cpu_to_le32(field4);
2832
2833 trace_xhci_queue_trb(ring, trb);
2834
2835 inc_enq(xhci, ring, more_trbs_coming);
2836}
2837
2838
2839
2840
2841
2842static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2843 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2844{
2845 unsigned int num_trbs_needed;
2846
2847
2848 switch (ep_state) {
2849 case EP_STATE_DISABLED:
2850
2851
2852
2853
2854 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2855 return -ENOENT;
2856 case EP_STATE_ERROR:
2857 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2858
2859
2860 return -EINVAL;
2861 case EP_STATE_HALTED:
2862 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2863 case EP_STATE_STOPPED:
2864 case EP_STATE_RUNNING:
2865 break;
2866 default:
2867 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2868
2869
2870
2871
2872 return -EINVAL;
2873 }
2874
2875 while (1) {
2876 if (room_on_ring(xhci, ep_ring, num_trbs))
2877 break;
2878
2879 if (ep_ring == xhci->cmd_ring) {
2880 xhci_err(xhci, "Do not support expand command ring\n");
2881 return -ENOMEM;
2882 }
2883
2884 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2885 "ERROR no room on ep ring, try ring expansion");
2886 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2887 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2888 mem_flags)) {
2889 xhci_err(xhci, "Ring expansion failed\n");
2890 return -ENOMEM;
2891 }
2892 }
2893
2894 while (trb_is_link(ep_ring->enqueue)) {
2895
2896
2897
2898 if (!xhci_link_trb_quirk(xhci) &&
2899 !(ep_ring->type == TYPE_ISOC &&
2900 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2901 ep_ring->enqueue->link.control &=
2902 cpu_to_le32(~TRB_CHAIN);
2903 else
2904 ep_ring->enqueue->link.control |=
2905 cpu_to_le32(TRB_CHAIN);
2906
2907 wmb();
2908 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2909
2910
2911 if (link_trb_toggles_cycle(ep_ring->enqueue))
2912 ep_ring->cycle_state ^= 1;
2913
2914 ep_ring->enq_seg = ep_ring->enq_seg->next;
2915 ep_ring->enqueue = ep_ring->enq_seg->trbs;
2916 }
2917 return 0;
2918}
2919
2920static int prepare_transfer(struct xhci_hcd *xhci,
2921 struct xhci_virt_device *xdev,
2922 unsigned int ep_index,
2923 unsigned int stream_id,
2924 unsigned int num_trbs,
2925 struct urb *urb,
2926 unsigned int td_index,
2927 gfp_t mem_flags)
2928{
2929 int ret;
2930 struct urb_priv *urb_priv;
2931 struct xhci_td *td;
2932 struct xhci_ring *ep_ring;
2933 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2934
2935 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2936 if (!ep_ring) {
2937 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2938 stream_id);
2939 return -EINVAL;
2940 }
2941
2942 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
2943 num_trbs, mem_flags);
2944 if (ret)
2945 return ret;
2946
2947 urb_priv = urb->hcpriv;
2948 td = &urb_priv->td[td_index];
2949
2950 INIT_LIST_HEAD(&td->td_list);
2951 INIT_LIST_HEAD(&td->cancelled_td_list);
2952
2953 if (td_index == 0) {
2954 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2955 if (unlikely(ret))
2956 return ret;
2957 }
2958
2959 td->urb = urb;
2960
2961 list_add_tail(&td->td_list, &ep_ring->td_list);
2962 td->start_seg = ep_ring->enq_seg;
2963 td->first_trb = ep_ring->enqueue;
2964
2965 return 0;
2966}
2967
2968static unsigned int count_trbs(u64 addr, u64 len)
2969{
2970 unsigned int num_trbs;
2971
2972 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
2973 TRB_MAX_BUFF_SIZE);
2974 if (num_trbs == 0)
2975 num_trbs++;
2976
2977 return num_trbs;
2978}
2979
2980static inline unsigned int count_trbs_needed(struct urb *urb)
2981{
2982 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
2983}
2984
2985static unsigned int count_sg_trbs_needed(struct urb *urb)
2986{
2987 struct scatterlist *sg;
2988 unsigned int i, len, full_len, num_trbs = 0;
2989
2990 full_len = urb->transfer_buffer_length;
2991
2992 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
2993 len = sg_dma_len(sg);
2994 num_trbs += count_trbs(sg_dma_address(sg), len);
2995 len = min_t(unsigned int, len, full_len);
2996 full_len -= len;
2997 if (full_len == 0)
2998 break;
2999 }
3000
3001 return num_trbs;
3002}
3003
3004static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3005{
3006 u64 addr, len;
3007
3008 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3009 len = urb->iso_frame_desc[i].length;
3010
3011 return count_trbs(addr, len);
3012}
3013
3014static void check_trb_math(struct urb *urb, int running_total)
3015{
3016 if (unlikely(running_total != urb->transfer_buffer_length))
3017 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3018 "queued %#x (%d), asked for %#x (%d)\n",
3019 __func__,
3020 urb->ep->desc.bEndpointAddress,
3021 running_total, running_total,
3022 urb->transfer_buffer_length,
3023 urb->transfer_buffer_length);
3024}
3025
3026static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3027 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3028 struct xhci_generic_trb *start_trb)
3029{
3030
3031
3032
3033
3034 wmb();
3035 if (start_cycle)
3036 start_trb->field[3] |= cpu_to_le32(start_cycle);
3037 else
3038 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3039 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3040}
3041
3042static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3043 struct xhci_ep_ctx *ep_ctx)
3044{
3045 int xhci_interval;
3046 int ep_interval;
3047
3048 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3049 ep_interval = urb->interval;
3050
3051
3052 if (urb->dev->speed == USB_SPEED_LOW ||
3053 urb->dev->speed == USB_SPEED_FULL)
3054 ep_interval *= 8;
3055
3056
3057
3058
3059 if (xhci_interval != ep_interval) {
3060 dev_dbg_ratelimited(&urb->dev->dev,
3061 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3062 ep_interval, ep_interval == 1 ? "" : "s",
3063 xhci_interval, xhci_interval == 1 ? "" : "s");
3064 urb->interval = xhci_interval;
3065
3066 if (urb->dev->speed == USB_SPEED_LOW ||
3067 urb->dev->speed == USB_SPEED_FULL)
3068 urb->interval /= 8;
3069 }
3070}
3071
3072
3073
3074
3075
3076
3077
3078int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3079 struct urb *urb, int slot_id, unsigned int ep_index)
3080{
3081 struct xhci_ep_ctx *ep_ctx;
3082
3083 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3084 check_interval(xhci, urb, ep_ctx);
3085
3086 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3087}
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3110 int trb_buff_len, unsigned int td_total_len,
3111 struct urb *urb, bool more_trbs_coming)
3112{
3113 u32 maxp, total_packet_count;
3114
3115
3116 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3117 return ((td_total_len - transferred) >> 10);
3118
3119
3120 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3121 trb_buff_len == td_total_len)
3122 return 0;
3123
3124
3125 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3126 trb_buff_len = 0;
3127
3128 maxp = usb_endpoint_maxp(&urb->ep->desc);
3129 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3130
3131
3132 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3133}
3134
3135
3136static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3137 u32 *trb_buff_len, struct xhci_segment *seg)
3138{
3139 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3140 unsigned int unalign;
3141 unsigned int max_pkt;
3142 u32 new_buff_len;
3143
3144 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3145 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3146
3147
3148 if (unalign == 0)
3149 return 0;
3150
3151 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3152 unalign, *trb_buff_len);
3153
3154
3155 if (*trb_buff_len > unalign) {
3156 *trb_buff_len -= unalign;
3157 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3158 return 0;
3159 }
3160
3161
3162
3163
3164
3165
3166 new_buff_len = max_pkt - (enqd_len % max_pkt);
3167
3168 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3169 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3170
3171
3172 if (usb_urb_dir_out(urb)) {
3173 sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs,
3174 seg->bounce_buf, new_buff_len, enqd_len);
3175 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3176 max_pkt, DMA_TO_DEVICE);
3177 } else {
3178 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3179 max_pkt, DMA_FROM_DEVICE);
3180 }
3181
3182 if (dma_mapping_error(dev, seg->bounce_dma)) {
3183
3184 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3185 return 0;
3186 }
3187 *trb_buff_len = new_buff_len;
3188 seg->bounce_len = new_buff_len;
3189 seg->bounce_offs = enqd_len;
3190
3191 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3192
3193 return 1;
3194}
3195
3196
3197int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3198 struct urb *urb, int slot_id, unsigned int ep_index)
3199{
3200 struct xhci_ring *ring;
3201 struct urb_priv *urb_priv;
3202 struct xhci_td *td;
3203 struct xhci_generic_trb *start_trb;
3204 struct scatterlist *sg = NULL;
3205 bool more_trbs_coming = true;
3206 bool need_zero_pkt = false;
3207 bool first_trb = true;
3208 unsigned int num_trbs;
3209 unsigned int start_cycle, num_sgs = 0;
3210 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3211 int sent_len, ret;
3212 u32 field, length_field, remainder;
3213 u64 addr, send_addr;
3214
3215 ring = xhci_urb_to_transfer_ring(xhci, urb);
3216 if (!ring)
3217 return -EINVAL;
3218
3219 full_len = urb->transfer_buffer_length;
3220
3221 if (urb->num_sgs) {
3222 num_sgs = urb->num_mapped_sgs;
3223 sg = urb->sg;
3224 addr = (u64) sg_dma_address(sg);
3225 block_len = sg_dma_len(sg);
3226 num_trbs = count_sg_trbs_needed(urb);
3227 } else {
3228 num_trbs = count_trbs_needed(urb);
3229 addr = (u64) urb->transfer_dma;
3230 block_len = full_len;
3231 }
3232 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3233 ep_index, urb->stream_id,
3234 num_trbs, urb, 0, mem_flags);
3235 if (unlikely(ret < 0))
3236 return ret;
3237
3238 urb_priv = urb->hcpriv;
3239
3240
3241 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3242 need_zero_pkt = true;
3243
3244 td = &urb_priv->td[0];
3245
3246
3247
3248
3249
3250
3251 start_trb = &ring->enqueue->generic;
3252 start_cycle = ring->cycle_state;
3253 send_addr = addr;
3254
3255
3256 for (enqd_len = 0; first_trb || enqd_len < full_len;
3257 enqd_len += trb_buff_len) {
3258 field = TRB_TYPE(TRB_NORMAL);
3259
3260
3261 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3262 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3263
3264 if (enqd_len + trb_buff_len > full_len)
3265 trb_buff_len = full_len - enqd_len;
3266
3267
3268 if (first_trb) {
3269 first_trb = false;
3270 if (start_cycle == 0)
3271 field |= TRB_CYCLE;
3272 } else
3273 field |= ring->cycle_state;
3274
3275
3276
3277
3278 if (enqd_len + trb_buff_len < full_len) {
3279 field |= TRB_CHAIN;
3280 if (trb_is_link(ring->enqueue + 1)) {
3281 if (xhci_align_td(xhci, urb, enqd_len,
3282 &trb_buff_len,
3283 ring->enq_seg)) {
3284 send_addr = ring->enq_seg->bounce_dma;
3285
3286 td->bounce_seg = ring->enq_seg;
3287 }
3288 }
3289 }
3290 if (enqd_len + trb_buff_len >= full_len) {
3291 field &= ~TRB_CHAIN;
3292 field |= TRB_IOC;
3293 more_trbs_coming = false;
3294 td->last_trb = ring->enqueue;
3295 }
3296
3297
3298 if (usb_urb_dir_in(urb))
3299 field |= TRB_ISP;
3300
3301
3302 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3303 full_len, urb, more_trbs_coming);
3304
3305 length_field = TRB_LEN(trb_buff_len) |
3306 TRB_TD_SIZE(remainder) |
3307 TRB_INTR_TARGET(0);
3308
3309 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3310 lower_32_bits(send_addr),
3311 upper_32_bits(send_addr),
3312 length_field,
3313 field);
3314
3315 addr += trb_buff_len;
3316 sent_len = trb_buff_len;
3317
3318 while (sg && sent_len >= block_len) {
3319
3320 --num_sgs;
3321 sent_len -= block_len;
3322 if (num_sgs != 0) {
3323 sg = sg_next(sg);
3324 block_len = sg_dma_len(sg);
3325 addr = (u64) sg_dma_address(sg);
3326 addr += sent_len;
3327 }
3328 }
3329 block_len -= sent_len;
3330 send_addr = addr;
3331 }
3332
3333 if (need_zero_pkt) {
3334 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3335 ep_index, urb->stream_id,
3336 1, urb, 1, mem_flags);
3337 urb_priv->td[1].last_trb = ring->enqueue;
3338 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3339 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3340 }
3341
3342 check_trb_math(urb, enqd_len);
3343 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3344 start_cycle, start_trb);
3345 return 0;
3346}
3347
3348
3349int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3350 struct urb *urb, int slot_id, unsigned int ep_index)
3351{
3352 struct xhci_ring *ep_ring;
3353 int num_trbs;
3354 int ret;
3355 struct usb_ctrlrequest *setup;
3356 struct xhci_generic_trb *start_trb;
3357 int start_cycle;
3358 u32 field;
3359 struct urb_priv *urb_priv;
3360 struct xhci_td *td;
3361
3362 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3363 if (!ep_ring)
3364 return -EINVAL;
3365
3366
3367
3368
3369
3370 if (!urb->setup_packet)
3371 return -EINVAL;
3372
3373
3374 num_trbs = 2;
3375
3376
3377
3378
3379
3380 if (urb->transfer_buffer_length > 0)
3381 num_trbs++;
3382 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3383 ep_index, urb->stream_id,
3384 num_trbs, urb, 0, mem_flags);
3385 if (ret < 0)
3386 return ret;
3387
3388 urb_priv = urb->hcpriv;
3389 td = &urb_priv->td[0];
3390
3391
3392
3393
3394
3395
3396 start_trb = &ep_ring->enqueue->generic;
3397 start_cycle = ep_ring->cycle_state;
3398
3399
3400
3401 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3402 field = 0;
3403 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3404 if (start_cycle == 0)
3405 field |= 0x1;
3406
3407
3408 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3409 if (urb->transfer_buffer_length > 0) {
3410 if (setup->bRequestType & USB_DIR_IN)
3411 field |= TRB_TX_TYPE(TRB_DATA_IN);
3412 else
3413 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3414 }
3415 }
3416
3417 queue_trb(xhci, ep_ring, true,
3418 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3419 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3420 TRB_LEN(8) | TRB_INTR_TARGET(0),
3421
3422 field);
3423
3424
3425
3426 if (usb_urb_dir_in(urb))
3427 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3428 else
3429 field = TRB_TYPE(TRB_DATA);
3430
3431 if (urb->transfer_buffer_length > 0) {
3432 u32 length_field, remainder;
3433
3434 remainder = xhci_td_remainder(xhci, 0,
3435 urb->transfer_buffer_length,
3436 urb->transfer_buffer_length,
3437 urb, 1);
3438 length_field = TRB_LEN(urb->transfer_buffer_length) |
3439 TRB_TD_SIZE(remainder) |
3440 TRB_INTR_TARGET(0);
3441 if (setup->bRequestType & USB_DIR_IN)
3442 field |= TRB_DIR_IN;
3443 queue_trb(xhci, ep_ring, true,
3444 lower_32_bits(urb->transfer_dma),
3445 upper_32_bits(urb->transfer_dma),
3446 length_field,
3447 field | ep_ring->cycle_state);
3448 }
3449
3450
3451 td->last_trb = ep_ring->enqueue;
3452
3453
3454
3455 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3456 field = 0;
3457 else
3458 field = TRB_DIR_IN;
3459 queue_trb(xhci, ep_ring, false,
3460 0,
3461 0,
3462 TRB_INTR_TARGET(0),
3463
3464 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3465
3466 giveback_first_trb(xhci, slot_id, ep_index, 0,
3467 start_cycle, start_trb);
3468 return 0;
3469}
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3480 struct urb *urb, unsigned int total_packet_count)
3481{
3482 unsigned int max_burst;
3483
3484 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3485 return 0;
3486
3487 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3488 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3489}
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3500 struct urb *urb, unsigned int total_packet_count)
3501{
3502 unsigned int max_burst;
3503 unsigned int residue;
3504
3505 if (xhci->hci_version < 0x100)
3506 return 0;
3507
3508 if (urb->dev->speed >= USB_SPEED_SUPER) {
3509
3510 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3511 residue = total_packet_count % (max_burst + 1);
3512
3513
3514
3515 if (residue == 0)
3516 return max_burst;
3517 return residue - 1;
3518 }
3519 if (total_packet_count == 0)
3520 return 0;
3521 return total_packet_count - 1;
3522}
3523
3524
3525
3526
3527
3528
3529
3530
3531static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3532 struct urb *urb, int index)
3533{
3534 int start_frame, ist, ret = 0;
3535 int start_frame_id, end_frame_id, current_frame_id;
3536
3537 if (urb->dev->speed == USB_SPEED_LOW ||
3538 urb->dev->speed == USB_SPEED_FULL)
3539 start_frame = urb->start_frame + index * urb->interval;
3540 else
3541 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3552 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3553 ist <<= 3;
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568 current_frame_id = readl(&xhci->run_regs->microframe_index);
3569 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3570 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3571
3572 start_frame &= 0x7ff;
3573 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3574 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3575
3576 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3577 __func__, index, readl(&xhci->run_regs->microframe_index),
3578 start_frame_id, end_frame_id, start_frame);
3579
3580 if (start_frame_id < end_frame_id) {
3581 if (start_frame > end_frame_id ||
3582 start_frame < start_frame_id)
3583 ret = -EINVAL;
3584 } else if (start_frame_id > end_frame_id) {
3585 if ((start_frame > end_frame_id &&
3586 start_frame < start_frame_id))
3587 ret = -EINVAL;
3588 } else {
3589 ret = -EINVAL;
3590 }
3591
3592 if (index == 0) {
3593 if (ret == -EINVAL || start_frame == start_frame_id) {
3594 start_frame = start_frame_id + 1;
3595 if (urb->dev->speed == USB_SPEED_LOW ||
3596 urb->dev->speed == USB_SPEED_FULL)
3597 urb->start_frame = start_frame;
3598 else
3599 urb->start_frame = start_frame << 3;
3600 ret = 0;
3601 }
3602 }
3603
3604 if (ret) {
3605 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3606 start_frame, current_frame_id, index,
3607 start_frame_id, end_frame_id);
3608 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3609 return ret;
3610 }
3611
3612 return start_frame;
3613}
3614
3615
3616static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3617 struct urb *urb, int slot_id, unsigned int ep_index)
3618{
3619 struct xhci_ring *ep_ring;
3620 struct urb_priv *urb_priv;
3621 struct xhci_td *td;
3622 int num_tds, trbs_per_td;
3623 struct xhci_generic_trb *start_trb;
3624 bool first_trb;
3625 int start_cycle;
3626 u32 field, length_field;
3627 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3628 u64 start_addr, addr;
3629 int i, j;
3630 bool more_trbs_coming;
3631 struct xhci_virt_ep *xep;
3632 int frame_id;
3633
3634 xep = &xhci->devs[slot_id]->eps[ep_index];
3635 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3636
3637 num_tds = urb->number_of_packets;
3638 if (num_tds < 1) {
3639 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3640 return -EINVAL;
3641 }
3642 start_addr = (u64) urb->transfer_dma;
3643 start_trb = &ep_ring->enqueue->generic;
3644 start_cycle = ep_ring->cycle_state;
3645
3646 urb_priv = urb->hcpriv;
3647
3648 for (i = 0; i < num_tds; i++) {
3649 unsigned int total_pkt_count, max_pkt;
3650 unsigned int burst_count, last_burst_pkt_count;
3651 u32 sia_frame_id;
3652
3653 first_trb = true;
3654 running_total = 0;
3655 addr = start_addr + urb->iso_frame_desc[i].offset;
3656 td_len = urb->iso_frame_desc[i].length;
3657 td_remain_len = td_len;
3658 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3659 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3660
3661
3662 if (total_pkt_count == 0)
3663 total_pkt_count++;
3664 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3665 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3666 urb, total_pkt_count);
3667
3668 trbs_per_td = count_isoc_trbs_needed(urb, i);
3669
3670 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3671 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3672 if (ret < 0) {
3673 if (i == 0)
3674 return ret;
3675 goto cleanup;
3676 }
3677 td = &urb_priv->td[i];
3678
3679
3680 sia_frame_id = TRB_SIA;
3681 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3682 HCC_CFC(xhci->hcc_params)) {
3683 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3684 if (frame_id >= 0)
3685 sia_frame_id = TRB_FRAME_ID(frame_id);
3686 }
3687
3688
3689
3690
3691
3692 field = TRB_TYPE(TRB_ISOC) |
3693 TRB_TLBPC(last_burst_pkt_count) |
3694 sia_frame_id |
3695 (i ? ep_ring->cycle_state : !start_cycle);
3696
3697
3698 if (!xep->use_extended_tbc)
3699 field |= TRB_TBC(burst_count);
3700
3701
3702 for (j = 0; j < trbs_per_td; j++) {
3703 u32 remainder = 0;
3704
3705
3706 if (!first_trb)
3707 field = TRB_TYPE(TRB_NORMAL) |
3708 ep_ring->cycle_state;
3709
3710
3711 if (usb_urb_dir_in(urb))
3712 field |= TRB_ISP;
3713
3714
3715 if (j < trbs_per_td - 1) {
3716 more_trbs_coming = true;
3717 field |= TRB_CHAIN;
3718 } else {
3719 more_trbs_coming = false;
3720 td->last_trb = ep_ring->enqueue;
3721 field |= TRB_IOC;
3722
3723 if (xhci->hci_version >= 0x100 &&
3724 !(xhci->quirks & XHCI_AVOID_BEI) &&
3725 i < num_tds - 1)
3726 field |= TRB_BEI;
3727 }
3728
3729 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3730 if (trb_buff_len > td_remain_len)
3731 trb_buff_len = td_remain_len;
3732
3733
3734 remainder = xhci_td_remainder(xhci, running_total,
3735 trb_buff_len, td_len,
3736 urb, more_trbs_coming);
3737
3738 length_field = TRB_LEN(trb_buff_len) |
3739 TRB_INTR_TARGET(0);
3740
3741
3742 if (first_trb && xep->use_extended_tbc)
3743 length_field |= TRB_TD_SIZE_TBC(burst_count);
3744 else
3745 length_field |= TRB_TD_SIZE(remainder);
3746 first_trb = false;
3747
3748 queue_trb(xhci, ep_ring, more_trbs_coming,
3749 lower_32_bits(addr),
3750 upper_32_bits(addr),
3751 length_field,
3752 field);
3753 running_total += trb_buff_len;
3754
3755 addr += trb_buff_len;
3756 td_remain_len -= trb_buff_len;
3757 }
3758
3759
3760 if (running_total != td_len) {
3761 xhci_err(xhci, "ISOC TD length unmatch\n");
3762 ret = -EINVAL;
3763 goto cleanup;
3764 }
3765 }
3766
3767
3768 if (HCC_CFC(xhci->hcc_params))
3769 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3770
3771 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3772 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3773 usb_amd_quirk_pll_disable();
3774 }
3775 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3776
3777 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3778 start_cycle, start_trb);
3779 return 0;
3780cleanup:
3781
3782
3783 for (i--; i >= 0; i--)
3784 list_del_init(&urb_priv->td[i].td_list);
3785
3786
3787
3788
3789
3790
3791 urb_priv->td[0].last_trb = ep_ring->enqueue;
3792
3793 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3794
3795
3796 ep_ring->enqueue = urb_priv->td[0].first_trb;
3797 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3798 ep_ring->cycle_state = start_cycle;
3799 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3800 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3801 return ret;
3802}
3803
3804
3805
3806
3807
3808
3809
3810
3811int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3812 struct urb *urb, int slot_id, unsigned int ep_index)
3813{
3814 struct xhci_virt_device *xdev;
3815 struct xhci_ring *ep_ring;
3816 struct xhci_ep_ctx *ep_ctx;
3817 int start_frame;
3818 int num_tds, num_trbs, i;
3819 int ret;
3820 struct xhci_virt_ep *xep;
3821 int ist;
3822
3823 xdev = xhci->devs[slot_id];
3824 xep = &xhci->devs[slot_id]->eps[ep_index];
3825 ep_ring = xdev->eps[ep_index].ring;
3826 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3827
3828 num_trbs = 0;
3829 num_tds = urb->number_of_packets;
3830 for (i = 0; i < num_tds; i++)
3831 num_trbs += count_isoc_trbs_needed(urb, i);
3832
3833
3834
3835
3836 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3837 num_trbs, mem_flags);
3838 if (ret)
3839 return ret;
3840
3841
3842
3843
3844
3845 check_interval(xhci, urb, ep_ctx);
3846
3847
3848 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3849 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3850 urb->start_frame = xep->next_frame_id;
3851 goto skip_start_over;
3852 }
3853 }
3854
3855 start_frame = readl(&xhci->run_regs->microframe_index);
3856 start_frame &= 0x3fff;
3857
3858
3859
3860
3861 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3862 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3863 ist <<= 3;
3864 start_frame += ist + XHCI_CFC_DELAY;
3865 start_frame = roundup(start_frame, 8);
3866
3867
3868
3869
3870
3871 if (urb->dev->speed == USB_SPEED_LOW ||
3872 urb->dev->speed == USB_SPEED_FULL) {
3873 start_frame = roundup(start_frame, urb->interval << 3);
3874 urb->start_frame = start_frame >> 3;
3875 } else {
3876 start_frame = roundup(start_frame, urb->interval);
3877 urb->start_frame = start_frame;
3878 }
3879
3880skip_start_over:
3881 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3882
3883 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3884}
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3897 u32 field1, u32 field2,
3898 u32 field3, u32 field4, bool command_must_succeed)
3899{
3900 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3901 int ret;
3902
3903 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3904 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3905 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3906 return -ESHUTDOWN;
3907 }
3908
3909 if (!command_must_succeed)
3910 reserved_trbs++;
3911
3912 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3913 reserved_trbs, GFP_ATOMIC);
3914 if (ret < 0) {
3915 xhci_err(xhci, "ERR: No room for command on command ring\n");
3916 if (command_must_succeed)
3917 xhci_err(xhci, "ERR: Reserved TRB counting for "
3918 "unfailable commands failed.\n");
3919 return ret;
3920 }
3921
3922 cmd->command_trb = xhci->cmd_ring->enqueue;
3923
3924
3925 if (list_empty(&xhci->cmd_list)) {
3926 xhci->current_cmd = cmd;
3927 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3928 }
3929
3930 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3931
3932 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3933 field4 | xhci->cmd_ring->cycle_state);
3934 return 0;
3935}
3936
3937
3938int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3939 u32 trb_type, u32 slot_id)
3940{
3941 return queue_command(xhci, cmd, 0, 0, 0,
3942 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3943}
3944
3945
3946int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3947 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3948{
3949 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3950 upper_32_bits(in_ctx_ptr), 0,
3951 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3952 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3953}
3954
3955int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3956 u32 field1, u32 field2, u32 field3, u32 field4)
3957{
3958 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3959}
3960
3961
3962int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3963 u32 slot_id)
3964{
3965 return queue_command(xhci, cmd, 0, 0, 0,
3966 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3967 false);
3968}
3969
3970
3971int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3972 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3973 u32 slot_id, bool command_must_succeed)
3974{
3975 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3976 upper_32_bits(in_ctx_ptr), 0,
3977 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3978 command_must_succeed);
3979}
3980
3981
3982int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3983 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3984{
3985 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3986 upper_32_bits(in_ctx_ptr), 0,
3987 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3988 command_must_succeed);
3989}
3990
3991
3992
3993
3994
3995int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3996 int slot_id, unsigned int ep_index, int suspend)
3997{
3998 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3999 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4000 u32 type = TRB_TYPE(TRB_STOP_RING);
4001 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4002
4003 return queue_command(xhci, cmd, 0, 0, 0,
4004 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4005}
4006
4007
4008void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4009 unsigned int slot_id, unsigned int ep_index,
4010 struct xhci_dequeue_state *deq_state)
4011{
4012 dma_addr_t addr;
4013 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4014 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4015 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4016 u32 trb_sct = 0;
4017 u32 type = TRB_TYPE(TRB_SET_DEQ);
4018 struct xhci_virt_ep *ep;
4019 struct xhci_command *cmd;
4020 int ret;
4021
4022 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4023 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4024 deq_state->new_deq_seg,
4025 (unsigned long long)deq_state->new_deq_seg->dma,
4026 deq_state->new_deq_ptr,
4027 (unsigned long long)xhci_trb_virt_to_dma(
4028 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4029 deq_state->new_cycle_state);
4030
4031 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4032 deq_state->new_deq_ptr);
4033 if (addr == 0) {
4034 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4035 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4036 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4037 return;
4038 }
4039 ep = &xhci->devs[slot_id]->eps[ep_index];
4040 if ((ep->ep_state & SET_DEQ_PENDING)) {
4041 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4042 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4043 return;
4044 }
4045
4046
4047 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
4048 if (!cmd)
4049 return;
4050
4051 ep->queued_deq_seg = deq_state->new_deq_seg;
4052 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4053 if (deq_state->stream_id)
4054 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4055 ret = queue_command(xhci, cmd,
4056 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4057 upper_32_bits(addr), trb_stream_id,
4058 trb_slot_id | trb_ep_index | type, false);
4059 if (ret < 0) {
4060 xhci_free_command(xhci, cmd);
4061 return;
4062 }
4063
4064
4065
4066
4067
4068
4069 ep->ep_state |= SET_DEQ_PENDING;
4070}
4071
4072int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4073 int slot_id, unsigned int ep_index,
4074 enum xhci_ep_reset_type reset_type)
4075{
4076 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4077 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4078 u32 type = TRB_TYPE(TRB_RESET_EP);
4079
4080 if (reset_type == EP_SOFT_RESET)
4081 type |= TRB_TSP;
4082
4083 return queue_command(xhci, cmd, 0, 0, 0,
4084 trb_slot_id | trb_ep_index | type, false);
4085}
4086