LXR linux/drivers/usb/musb/am35x.c

   1// SPDX-License-Identifier: GPL-2.0
   2
   3/*
   4 * Texas Instruments AM35x "glue layer"
   5 *
   6 * Copyright (c) 2010, by Texas Instruments
   7 *
   8 * Based on the DA8xx "glue layer" code.
   9 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
  10 *
  11 * This file is part of the Inventra Controller Driver for Linux.
  12 */
  13
  14#include <linux/module.h>
  15#include <linux/clk.h>
  16#include <linux/err.h>
  17#include <linux/io.h>
  18#include <linux/platform_device.h>
  19#include <linux/dma-mapping.h>
  20#include <linux/usb/usb_phy_generic.h>
  21#include <linux/platform_data/usb-omap.h>
  22
  23#include "musb_core.h"
  24
  25/*
  26 * AM35x specific definitions
  27 */
  28/* USB 2.0 OTG module registers */
  29#define USB_REVISION_REG        0x00
  30#define USB_CTRL_REG            0x04
  31#define USB_STAT_REG            0x08
  32#define USB_EMULATION_REG       0x0c
  33/* 0x10 Reserved */
  34#define USB_AUTOREQ_REG         0x14
  35#define USB_SRP_FIX_TIME_REG    0x18
  36#define USB_TEARDOWN_REG        0x1c
  37#define EP_INTR_SRC_REG         0x20
  38#define EP_INTR_SRC_SET_REG     0x24
  39#define EP_INTR_SRC_CLEAR_REG   0x28
  40#define EP_INTR_MASK_REG        0x2c
  41#define EP_INTR_MASK_SET_REG    0x30
  42#define EP_INTR_MASK_CLEAR_REG  0x34
  43#define EP_INTR_SRC_MASKED_REG  0x38
  44#define CORE_INTR_SRC_REG       0x40
  45#define CORE_INTR_SRC_SET_REG   0x44
  46#define CORE_INTR_SRC_CLEAR_REG 0x48
  47#define CORE_INTR_MASK_REG      0x4c
  48#define CORE_INTR_MASK_SET_REG  0x50
  49#define CORE_INTR_MASK_CLEAR_REG 0x54
  50#define CORE_INTR_SRC_MASKED_REG 0x58
  51/* 0x5c Reserved */
  52#define USB_END_OF_INTR_REG     0x60
  53
  54/* Control register bits */
  55#define AM35X_SOFT_RESET_MASK   1
  56
  57/* USB interrupt register bits */
  58#define AM35X_INTR_USB_SHIFT    16
  59#define AM35X_INTR_USB_MASK     (0x1ff << AM35X_INTR_USB_SHIFT)
  60#define AM35X_INTR_DRVVBUS      0x100
  61#define AM35X_INTR_RX_SHIFT     16
  62#define AM35X_INTR_TX_SHIFT     0
  63#define AM35X_TX_EP_MASK        0xffff          /* EP0 + 15 Tx EPs */
  64#define AM35X_RX_EP_MASK        0xfffe          /* 15 Rx EPs */
  65#define AM35X_TX_INTR_MASK      (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
  66#define AM35X_RX_INTR_MASK      (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
  67
  68#define USB_MENTOR_CORE_OFFSET  0x400
  69
  70struct am35x_glue {
  71        struct device           *dev;
  72        struct platform_device  *musb;
  73        struct platform_device  *phy;
  74        struct clk              *phy_clk;
  75        struct clk              *clk;
  76};
  77
  78/*
  79 * am35x_musb_enable - enable interrupts
  80 */
  81static void am35x_musb_enable(struct musb *musb)
  82{
  83        void __iomem *reg_base = musb->ctrl_base;
  84        u32 epmask;
  85
  86        /* Workaround: setup IRQs through both register sets. */
  87        epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
  88               ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
  89
  90        musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
  91        musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
  92
  93        /* Force the DRVVBUS IRQ so we can start polling for ID change. */
  94        musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
  95                        AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
  96}
  97
  98/*
  99 * am35x_musb_disable - disable HDRC and flush interrupts
 100 */
 101static void am35x_musb_disable(struct musb *musb)
 102{
 103        void __iomem *reg_base = musb->ctrl_base;
 104
 105        musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
 106        musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
 107                         AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
 108        musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
 109}
 110
 111#define portstate(stmt)         stmt
 112
 113static void am35x_musb_set_vbus(struct musb *musb, int is_on)
 114{
 115        WARN_ON(is_on && is_peripheral_active(musb));
 116}
 117
 118#define POLL_SECONDS    2
 119
 120static void otg_timer(struct timer_list *t)
 121{
 122        struct musb             *musb = from_timer(musb, t, dev_timer);
 123        void __iomem            *mregs = musb->mregs;
 124        u8                      devctl;
 125        unsigned long           flags;
 126
 127        /*
 128         * We poll because AM35x's won't expose several OTG-critical
 129         * status change events (from the transceiver) otherwise.
 130         */
 131        devctl = musb_readb(mregs, MUSB_DEVCTL);
 132        dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
 133                usb_otg_state_string(musb->xceiv->otg->state));
 134
 135        spin_lock_irqsave(&musb->lock, flags);
 136        switch (musb->xceiv->otg->state) {
 137        case OTG_STATE_A_WAIT_BCON:
 138                devctl &= ~MUSB_DEVCTL_SESSION;
 139                musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 140
 141                devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 142                if (devctl & MUSB_DEVCTL_BDEVICE) {
 143                        musb->xceiv->otg->state = OTG_STATE_B_IDLE;
 144                        MUSB_DEV_MODE(musb);
 145                } else {
 146                        musb->xceiv->otg->state = OTG_STATE_A_IDLE;
 147                        MUSB_HST_MODE(musb);
 148                }
 149                break;
 150        case OTG_STATE_A_WAIT_VFALL:
 151                musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
 152                musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
 153                            MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
 154                break;
 155        case OTG_STATE_B_IDLE:
 156                devctl = musb_readb(mregs, MUSB_DEVCTL);
 157                if (devctl & MUSB_DEVCTL_BDEVICE)
 158                        mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
 159                else
 160                        musb->xceiv->otg->state = OTG_STATE_A_IDLE;
 161                break;
 162        default:
 163                break;
 164        }
 165        spin_unlock_irqrestore(&musb->lock, flags);
 166}
 167
 168static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
 169{
 170        static unsigned long last_timer;
 171
 172        if (timeout == 0)
 173                timeout = jiffies + msecs_to_jiffies(3);
 174
 175        /* Never idle if active, or when VBUS timeout is not set as host */
 176        if (musb->is_active || (musb->a_wait_bcon == 0 &&
 177                                musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
 178                dev_dbg(musb->controller, "%s active, deleting timer\n",
 179                        usb_otg_state_string(musb->xceiv->otg->state));
 180                del_timer(&musb->dev_timer);
 181                last_timer = jiffies;
 182                return;
 183        }
 184
 185        if (time_after(last_timer, timeout) && timer_pending(&musb->dev_timer)) {
 186                dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
 187                return;
 188        }
 189        last_timer = timeout;
 190
 191        dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
 192                usb_otg_state_string(musb->xceiv->otg->state),
 193                jiffies_to_msecs(timeout - jiffies));
 194        mod_timer(&musb->dev_timer, timeout);
 195}
 196
 197static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
 198{
 199        struct musb  *musb = hci;
 200        void __iomem *reg_base = musb->ctrl_base;
 201        struct device *dev = musb->controller;
 202        struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 203        struct omap_musb_board_data *data = plat->board_data;
 204        struct usb_otg *otg = musb->xceiv->otg;
 205        unsigned long flags;
 206        irqreturn_t ret = IRQ_NONE;
 207        u32 epintr, usbintr;
 208
 209        spin_lock_irqsave(&musb->lock, flags);
 210
 211        /* Get endpoint interrupts */
 212        epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
 213
 214        if (epintr) {
 215                musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
 216
 217                musb->int_rx =
 218                        (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
 219                musb->int_tx =
 220                        (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
 221        }
 222
 223        /* Get usb core interrupts */
 224        usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
 225        if (!usbintr && !epintr)
 226                goto eoi;
 227
 228        if (usbintr) {
 229                musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
 230
 231                musb->int_usb =
 232                        (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
 233        }
 234        /*
 235         * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
 236         * AM35x's missing ID change IRQ.  We need an ID change IRQ to
 237         * switch appropriately between halves of the OTG state machine.
 238         * Managing DEVCTL.SESSION per Mentor docs requires that we know its
 239         * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
 240         * Also, DRVVBUS pulses for SRP (but not at 5V) ...
 241         */
 242        if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
 243                int drvvbus = musb_readl(reg_base, USB_STAT_REG);
 244                void __iomem *mregs = musb->mregs;
 245                u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
 246                int err;
 247
 248                err = musb->int_usb & MUSB_INTR_VBUSERROR;
 249                if (err) {
 250                        /*
 251                         * The Mentor core doesn't debounce VBUS as needed
 252                         * to cope with device connect current spikes. This
 253                         * means it's not uncommon for bus-powered devices
 254                         * to get VBUS errors during enumeration.
 255                         *
 256                         * This is a workaround, but newer RTL from Mentor
 257                         * seems to allow a better one: "re"-starting sessions
 258                         * without waiting for VBUS to stop registering in
 259                         * devctl.
 260                         */
 261                        musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 262                        musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
 263                        mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
 264                        WARNING("VBUS error workaround (delay coming)\n");
 265                } else if (drvvbus) {
 266                        MUSB_HST_MODE(musb);
 267                        otg->default_a = 1;
 268                        musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
 269                        portstate(musb->port1_status |= USB_PORT_STAT_POWER);
 270                        del_timer(&musb->dev_timer);
 271                } else {
 272                        musb->is_active = 0;
 273                        MUSB_DEV_MODE(musb);
 274                        otg->default_a = 0;
 275                        musb->xceiv->otg->state = OTG_STATE_B_IDLE;
 276                        portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
 277                }
 278
 279                /* NOTE: this must complete power-on within 100 ms. */
 280                dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
 281                                drvvbus ? "on" : "off",
 282                                usb_otg_state_string(musb->xceiv->otg->state),
 283                                err ? " ERROR" : "",
 284                                devctl);
 285                ret = IRQ_HANDLED;
 286        }
 287
 288        /* Drop spurious RX and TX if device is disconnected */
 289        if (musb->int_usb & MUSB_INTR_DISCONNECT) {
 290                musb->int_tx = 0;
 291                musb->int_rx = 0;
 292        }
 293
 294        if (musb->int_tx || musb->int_rx || musb->int_usb)
 295                ret |= musb_interrupt(musb);
 296
 297eoi:
 298        /* EOI needs to be written for the IRQ to be re-asserted. */
 299        if (ret == IRQ_HANDLED || epintr || usbintr) {
 300                /* clear level interrupt */
 301                if (data->clear_irq)
 302                        data->clear_irq();
 303                /* write EOI */
 304                musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
 305        }
 306
 307        /* Poll for ID change */
 308        if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
 309                mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
 310
 311        spin_unlock_irqrestore(&musb->lock, flags);
 312
 313        return ret;
 314}
 315
 316static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
 317{
 318        struct device *dev = musb->controller;
 319        struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 320        struct omap_musb_board_data *data = plat->board_data;
 321        int     retval = 0;
 322
 323        if (data->set_mode)
 324                data->set_mode(musb_mode);
 325        else
 326                retval = -EIO;
 327
 328        return retval;
 329}
 330
 331static int am35x_musb_init(struct musb *musb)
 332{
 333        struct device *dev = musb->controller;
 334        struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 335        struct omap_musb_board_data *data = plat->board_data;
 336        void __iomem *reg_base = musb->ctrl_base;
 337        u32 rev;
 338
 339        musb->mregs += USB_MENTOR_CORE_OFFSET;
 340
 341        /* Returns zero if e.g. not clocked */
 342        rev = musb_readl(reg_base, USB_REVISION_REG);
 343        if (!rev)
 344                return -ENODEV;
 345
 346        musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
 347        if (IS_ERR_OR_NULL(musb->xceiv))
 348                return -EPROBE_DEFER;
 349
 350        timer_setup(&musb->dev_timer, otg_timer, 0);
 351
 352        /* Reset the musb */
 353        if (data->reset)
 354                data->reset();
 355
 356        /* Reset the controller */
 357        musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
 358
 359        /* Start the on-chip PHY and its PLL. */
 360        if (data->set_phy_power)
 361                data->set_phy_power(1);
 362
 363        msleep(5);
 364
 365        musb->isr = am35x_musb_interrupt;
 366
 367        /* clear level interrupt */
 368        if (data->clear_irq)
 369                data->clear_irq();
 370
 371        return 0;
 372}
 373
 374static int am35x_musb_exit(struct musb *musb)
 375{
 376        struct device *dev = musb->controller;
 377        struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 378        struct omap_musb_board_data *data = plat->board_data;
 379
 380        del_timer_sync(&musb->dev_timer);
 381
 382        /* Shutdown the on-chip PHY and its PLL. */
 383        if (data->set_phy_power)
 384                data->set_phy_power(0);
 385
 386        usb_put_phy(musb->xceiv);
 387
 388        return 0;
 389}
 390
 391/* AM35x supports only 32bit read operation */
 392static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 393{
 394        void __iomem *fifo = hw_ep->fifo;
 395        u32             val;
 396        int             i;
 397
 398        /* Read for 32bit-aligned destination address */
 399        if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
 400                readsl(fifo, dst, len >> 2);
 401                dst += len & ~0x03;
 402                len &= 0x03;
 403        }
 404        /*
 405         * Now read the remaining 1 to 3 byte or complete length if
 406         * unaligned address.
 407         */
 408        if (len > 4) {
 409                for (i = 0; i < (len >> 2); i++) {
 410                        *(u32 *) dst = musb_readl(fifo, 0);
 411                        dst += 4;
 412                }
 413                len &= 0x03;
 414        }
 415        if (len > 0) {
 416                val = musb_readl(fifo, 0);
 417                memcpy(dst, &val, len);
 418        }
 419}
 420
 421static const struct musb_platform_ops am35x_ops = {
 422        .quirks         = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
 423        .init           = am35x_musb_init,
 424        .exit           = am35x_musb_exit,
 425
 426        .read_fifo      = am35x_read_fifo,
 427#ifdef CONFIG_USB_INVENTRA_DMA
 428        .dma_init       = musbhs_dma_controller_create,
 429        .dma_exit       = musbhs_dma_controller_destroy,
 430#endif
 431        .enable         = am35x_musb_enable,
 432        .disable        = am35x_musb_disable,
 433
 434        .set_mode       = am35x_musb_set_mode,
 435        .try_idle       = am35x_musb_try_idle,
 436
 437        .set_vbus       = am35x_musb_set_vbus,
 438};
 439
 440static const struct platform_device_info am35x_dev_info = {
 441        .name           = "musb-hdrc",
 442        .id             = PLATFORM_DEVID_AUTO,
 443        .dma_mask       = DMA_BIT_MASK(32),
 444};
 445
 446static int am35x_probe(struct platform_device *pdev)
 447{
 448        struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
 449        struct platform_device          *musb;
 450        struct am35x_glue               *glue;
 451        struct platform_device_info     pinfo;
 452        struct clk                      *phy_clk;
 453        struct clk                      *clk;
 454
 455        int                             ret = -ENOMEM;
 456
 457        glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 458        if (!glue)
 459                goto err0;
 460
 461        phy_clk = clk_get(&pdev->dev, "fck");
 462        if (IS_ERR(phy_clk)) {
 463                dev_err(&pdev->dev, "failed to get PHY clock\n");
 464                ret = PTR_ERR(phy_clk);
 465                goto err3;
 466        }
 467
 468        clk = clk_get(&pdev->dev, "ick");
 469        if (IS_ERR(clk)) {
 470                dev_err(&pdev->dev, "failed to get clock\n");
 471                ret = PTR_ERR(clk);
 472                goto err4;
 473        }
 474
 475        ret = clk_enable(phy_clk);
 476        if (ret) {
 477                dev_err(&pdev->dev, "failed to enable PHY clock\n");
 478                goto err5;
 479        }
 480
 481        ret = clk_enable(clk);
 482        if (ret) {
 483                dev_err(&pdev->dev, "failed to enable clock\n");
 484                goto err6;
 485        }
 486
 487        glue->dev                       = &pdev->dev;
 488        glue->phy_clk                   = phy_clk;
 489        glue->clk                       = clk;
 490
 491        pdata->platform_ops             = &am35x_ops;
 492
 493        glue->phy = usb_phy_generic_register();
 494        if (IS_ERR(glue->phy)) {
 495                ret = PTR_ERR(glue->phy);
 496                goto err7;
 497        }
 498        platform_set_drvdata(pdev, glue);
 499
 500        pinfo = am35x_dev_info;
 501        pinfo.parent = &pdev->dev;
 502        pinfo.res = pdev->resource;
 503        pinfo.num_res = pdev->num_resources;
 504        pinfo.data = pdata;
 505        pinfo.size_data = sizeof(*pdata);
 506
 507        glue->musb = musb = platform_device_register_full(&pinfo);
 508        if (IS_ERR(musb)) {
 509                ret = PTR_ERR(musb);
 510                dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
 511                goto err8;
 512        }
 513
 514        return 0;
 515
 516err8:
 517        usb_phy_generic_unregister(glue->phy);
 518
 519err7:
 520        clk_disable(clk);
 521
 522err6:
 523        clk_disable(phy_clk);
 524
 525err5:
 526        clk_put(clk);
 527
 528err4:
 529        clk_put(phy_clk);
 530
 531err3:
 532        kfree(glue);
 533
 534err0:
 535        return ret;
 536}
 537
 538static int am35x_remove(struct platform_device *pdev)
 539{
 540        struct am35x_glue       *glue = platform_get_drvdata(pdev);
 541
 542        platform_device_unregister(glue->musb);
 543        usb_phy_generic_unregister(glue->phy);
 544        clk_disable(glue->clk);
 545        clk_disable(glue->phy_clk);
 546        clk_put(glue->clk);
 547        clk_put(glue->phy_clk);
 548        kfree(glue);
 549
 550        return 0;
 551}
 552
 553#ifdef CONFIG_PM_SLEEP
 554static int am35x_suspend(struct device *dev)
 555{
 556        struct am35x_glue       *glue = dev_get_drvdata(dev);
 557        struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 558        struct omap_musb_board_data *data = plat->board_data;
 559
 560        /* Shutdown the on-chip PHY and its PLL. */
 561        if (data->set_phy_power)
 562                data->set_phy_power(0);
 563
 564        clk_disable(glue->phy_clk);
 565        clk_disable(glue->clk);
 566
 567        return 0;
 568}
 569
 570static int am35x_resume(struct device *dev)
 571{
 572        struct am35x_glue       *glue = dev_get_drvdata(dev);
 573        struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 574        struct omap_musb_board_data *data = plat->board_data;
 575        int                     ret;
 576
 577        /* Start the on-chip PHY and its PLL. */
 578        if (data->set_phy_power)
 579                data->set_phy_power(1);
 580
 581        ret = clk_enable(glue->phy_clk);
 582        if (ret) {
 583                dev_err(dev, "failed to enable PHY clock\n");
 584                return ret;
 585        }
 586
 587        ret = clk_enable(glue->clk);
 588        if (ret) {
 589                dev_err(dev, "failed to enable clock\n");
 590                return ret;
 591        }
 592
 593        return 0;
 594}
 595#endif
 596
 597static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
 598
 599static struct platform_driver am35x_driver = {
 600        .probe          = am35x_probe,
 601        .remove         = am35x_remove,
 602        .driver         = {
 603                .name   = "musb-am35x",
 604                .pm     = &am35x_pm_ops,
 605        },
 606};
 607
 608MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
 609MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
 610MODULE_LICENSE("GPL v2");
 611module_platform_driver(am35x_driver);
 612