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9#include <linux/dma-mapping.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/interrupt.h>
13#include <linux/ioport.h>
14#include <linux/serial_core.h>
15#include <linux/serial_s3c.h>
16#include <clocksource/samsung_pwm.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/io.h>
20#include <linux/platform_data/dma-s3c24xx.h>
21#include <linux/dmaengine.h>
22
23#include <mach/hardware.h>
24#include <mach/regs-clock.h>
25#include <asm/irq.h>
26#include <asm/cacheflush.h>
27#include <asm/system_info.h>
28#include <asm/system_misc.h>
29
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32
33#include <mach/regs-gpio.h>
34#include <mach/dma.h>
35
36#include <plat/cpu.h>
37#include <plat/devs.h>
38#include <plat/cpu-freq.h>
39#include <plat/pwm-core.h>
40
41#include "common.h"
42
43
44
45static const char name_s3c2410[] = "S3C2410";
46static const char name_s3c2412[] = "S3C2412";
47static const char name_s3c2416[] = "S3C2416/S3C2450";
48static const char name_s3c2440[] = "S3C2440";
49static const char name_s3c2442[] = "S3C2442";
50static const char name_s3c2442b[] = "S3C2442B";
51static const char name_s3c2443[] = "S3C2443";
52static const char name_s3c2410a[] = "S3C2410A";
53static const char name_s3c2440a[] = "S3C2440A";
54
55static struct cpu_table cpu_ids[] __initdata = {
56 {
57 .idcode = 0x32410000,
58 .idmask = 0xffffffff,
59 .map_io = s3c2410_map_io,
60 .init_uarts = s3c2410_init_uarts,
61 .init = s3c2410_init,
62 .name = name_s3c2410
63 },
64 {
65 .idcode = 0x32410002,
66 .idmask = 0xffffffff,
67 .map_io = s3c2410_map_io,
68 .init_uarts = s3c2410_init_uarts,
69 .init = s3c2410a_init,
70 .name = name_s3c2410a
71 },
72 {
73 .idcode = 0x32440000,
74 .idmask = 0xffffffff,
75 .map_io = s3c2440_map_io,
76 .init_uarts = s3c244x_init_uarts,
77 .init = s3c2440_init,
78 .name = name_s3c2440
79 },
80 {
81 .idcode = 0x32440001,
82 .idmask = 0xffffffff,
83 .map_io = s3c2440_map_io,
84 .init_uarts = s3c244x_init_uarts,
85 .init = s3c2440_init,
86 .name = name_s3c2440a
87 },
88 {
89 .idcode = 0x32440aaa,
90 .idmask = 0xffffffff,
91 .map_io = s3c2442_map_io,
92 .init_uarts = s3c244x_init_uarts,
93 .init = s3c2442_init,
94 .name = name_s3c2442
95 },
96 {
97 .idcode = 0x32440aab,
98 .idmask = 0xffffffff,
99 .map_io = s3c2442_map_io,
100 .init_uarts = s3c244x_init_uarts,
101 .init = s3c2442_init,
102 .name = name_s3c2442b
103 },
104 {
105 .idcode = 0x32412001,
106 .idmask = 0xffffffff,
107 .map_io = s3c2412_map_io,
108 .init_uarts = s3c2412_init_uarts,
109 .init = s3c2412_init,
110 .name = name_s3c2412,
111 },
112 {
113 .idcode = 0x32412003,
114 .idmask = 0xffffffff,
115 .map_io = s3c2412_map_io,
116 .init_uarts = s3c2412_init_uarts,
117 .init = s3c2412_init,
118 .name = name_s3c2412,
119 },
120 {
121 .idcode = 0x32450003,
122 .idmask = 0xffffffff,
123 .map_io = s3c2416_map_io,
124 .init_uarts = s3c2416_init_uarts,
125 .init = s3c2416_init,
126 .name = name_s3c2416,
127 },
128 {
129 .idcode = 0x32443001,
130 .idmask = 0xffffffff,
131 .map_io = s3c2443_map_io,
132 .init_uarts = s3c2443_init_uarts,
133 .init = s3c2443_init,
134 .name = name_s3c2443,
135 },
136};
137
138
139
140static struct map_desc s3c_iodesc[] __initdata = {
141 IODESC_ENT(GPIO),
142 IODESC_ENT(IRQ),
143 IODESC_ENT(MEMCTRL),
144 IODESC_ENT(UART)
145};
146
147
148
149static unsigned long s3c24xx_read_idcode_v5(void)
150{
151#if defined(CONFIG_CPU_S3C2416)
152
153
154 u32 gs = __raw_readl(S3C24XX_GSTATUS1);
155
156
157 if ((gs >> 16) == 0x3245)
158 return gs;
159#endif
160
161#if defined(CONFIG_CPU_S3C2412)
162 return __raw_readl(S3C2412_GSTATUS1);
163#else
164 return 1UL;
165#endif
166}
167
168static unsigned long s3c24xx_read_idcode_v4(void)
169{
170 return __raw_readl(S3C2410_GSTATUS1);
171}
172
173static void s3c24xx_default_idle(void)
174{
175 unsigned long tmp = 0;
176 int i;
177
178
179
180
181
182
183
184 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
185 S3C2410_CLKCON);
186
187
188 for (i = 0; i < 50; i++)
189 tmp += __raw_readl(S3C2410_CLKCON);
190
191
192
193 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
194 S3C2410_CLKCON);
195}
196
197static struct samsung_pwm_variant s3c24xx_pwm_variant = {
198 .bits = 16,
199 .div_base = 1,
200 .has_tint_cstat = false,
201 .tclk_mask = (1 << 4),
202};
203
204void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
205{
206 arm_pm_idle = s3c24xx_default_idle;
207
208
209 iotable_init(mach_desc, size);
210 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
211
212 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
213 samsung_cpu_id = s3c24xx_read_idcode_v5();
214 } else {
215 samsung_cpu_id = s3c24xx_read_idcode_v4();
216 }
217
218 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
219
220 samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
221}
222
223void __init samsung_set_timer_source(unsigned int event, unsigned int source)
224{
225 s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
226 s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
227}
228
229void __init samsung_timer_init(void)
230{
231 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
232 IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
233 };
234
235 samsung_pwm_clocksource_init(S3C_VA_TIMER,
236 timer_irqs, &s3c24xx_pwm_variant);
237}
238
239
240
241#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
242#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
243#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
244#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
245
246static struct resource s3c2410_uart0_resource[] = {
247 [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
248 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
249 IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
250 NULL, IORESOURCE_IRQ)
251};
252
253static struct resource s3c2410_uart1_resource[] = {
254 [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
255 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
256 IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
257 NULL, IORESOURCE_IRQ)
258};
259
260static struct resource s3c2410_uart2_resource[] = {
261 [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
262 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
263 IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
264 NULL, IORESOURCE_IRQ)
265};
266
267static struct resource s3c2410_uart3_resource[] = {
268 [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
269 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
270 IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
271 NULL, IORESOURCE_IRQ)
272};
273
274struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
275 [0] = {
276 .resources = s3c2410_uart0_resource,
277 .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
278 },
279 [1] = {
280 .resources = s3c2410_uart1_resource,
281 .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
282 },
283 [2] = {
284 .resources = s3c2410_uart2_resource,
285 .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
286 },
287 [3] = {
288 .resources = s3c2410_uart3_resource,
289 .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
290 },
291};
292
293#define s3c24xx_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
294
295#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
296 defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
297static struct resource s3c2410_dma_resource[] = {
298 [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
299 [1] = DEFINE_RES_IRQ(IRQ_DMA0),
300 [2] = DEFINE_RES_IRQ(IRQ_DMA1),
301 [3] = DEFINE_RES_IRQ(IRQ_DMA2),
302 [4] = DEFINE_RES_IRQ(IRQ_DMA3),
303};
304#endif
305
306#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
307static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
308 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
309 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
310 [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
311 S3C24XX_DMA_CHANREQ(2, 2) |
312 S3C24XX_DMA_CHANREQ(1, 3),
313 },
314 [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
315 [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
316 [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
317 [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
318 [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
319 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
320 S3C24XX_DMA_CHANREQ(3, 2) |
321 S3C24XX_DMA_CHANREQ(3, 3),
322 },
323 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
324 S3C24XX_DMA_CHANREQ(1, 2),
325 },
326 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
327 [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
328 [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
329 [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
330 [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
331};
332
333static const struct dma_slave_map s3c2410_dma_slave_map[] = {
334 { "s3c2410-sdi", "rx-tx", (void *)DMACH_SDI },
335 { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0_RX },
336 { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0_TX },
337 { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1_RX },
338 { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1_TX },
339
340
341
342
343 { "s3c2410-uart.0", "rx", (void *)DMACH_UART0 },
344 { "s3c2410-uart.0", "tx", (void *)DMACH_UART0 },
345 { "s3c2410-uart.1", "rx", (void *)DMACH_UART1 },
346 { "s3c2410-uart.1", "tx", (void *)DMACH_UART1 },
347 { "s3c2410-uart.2", "rx", (void *)DMACH_UART2 },
348 { "s3c2410-uart.2", "tx", (void *)DMACH_UART2 },
349 { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
350 { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
351 { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
352 { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
353 { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
354 { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
355 { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
356 { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
357 { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
358 { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
359};
360
361static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
362 .num_phy_channels = 4,
363 .channels = s3c2410_dma_channels,
364 .num_channels = DMACH_MAX,
365 .slave_map = s3c2410_dma_slave_map,
366 .slavecnt = ARRAY_SIZE(s3c2410_dma_slave_map),
367};
368
369struct platform_device s3c2410_device_dma = {
370 .name = "s3c2410-dma",
371 .id = 0,
372 .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
373 .resource = s3c2410_dma_resource,
374 .dev = {
375 .dma_mask = &s3c24xx_device_dma_mask,
376 .coherent_dma_mask = DMA_BIT_MASK(32),
377 .platform_data = &s3c2410_dma_platdata,
378 },
379};
380#endif
381
382#ifdef CONFIG_CPU_S3C2412
383static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
384 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
385 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
386 [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
387 [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
388 [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
389 [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
390 [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
391 [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
392 [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
393 [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
394 [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
395 [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
396 [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
397 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
398 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
399 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
400 [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
401 [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
402 [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
403 [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
404};
405
406static const struct dma_slave_map s3c2412_dma_slave_map[] = {
407 { "s3c2412-sdi", "rx-tx", (void *)DMACH_SDI },
408 { "s3c2412-spi.0", "rx", (void *)DMACH_SPI0_RX },
409 { "s3c2412-spi.0", "tx", (void *)DMACH_SPI0_TX },
410 { "s3c2412-spi.1", "rx", (void *)DMACH_SPI1_RX },
411 { "s3c2412-spi.1", "tx", (void *)DMACH_SPI1_TX },
412 { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
413 { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
414 { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
415 { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
416 { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
417 { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
418 { "s3c2412-iis", "rx", (void *)DMACH_I2S_IN },
419 { "s3c2412-iis", "tx", (void *)DMACH_I2S_OUT },
420 { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
421 { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
422 { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
423 { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
424 { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
425 { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
426 { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
427 { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
428};
429
430static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
431 .num_phy_channels = 4,
432 .channels = s3c2412_dma_channels,
433 .num_channels = DMACH_MAX,
434 .slave_map = s3c2412_dma_slave_map,
435 .slavecnt = ARRAY_SIZE(s3c2412_dma_slave_map),
436};
437
438struct platform_device s3c2412_device_dma = {
439 .name = "s3c2412-dma",
440 .id = 0,
441 .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
442 .resource = s3c2410_dma_resource,
443 .dev = {
444 .dma_mask = &s3c24xx_device_dma_mask,
445 .coherent_dma_mask = DMA_BIT_MASK(32),
446 .platform_data = &s3c2412_dma_platdata,
447 },
448};
449#endif
450
451#if defined(CONFIG_CPU_S3C2440)
452static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
453 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
454 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
455 [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
456 S3C24XX_DMA_CHANREQ(6, 1) |
457 S3C24XX_DMA_CHANREQ(2, 2) |
458 S3C24XX_DMA_CHANREQ(1, 3),
459 },
460 [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
461 [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
462 [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
463 [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
464 [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
465 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
466 S3C24XX_DMA_CHANREQ(3, 2) |
467 S3C24XX_DMA_CHANREQ(3, 3),
468 },
469 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
470 S3C24XX_DMA_CHANREQ(1, 2),
471 },
472 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
473 S3C24XX_DMA_CHANREQ(0, 2),
474 },
475 [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
476 S3C24XX_DMA_CHANREQ(5, 2),
477 },
478 [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
479 S3C24XX_DMA_CHANREQ(6, 3),
480 },
481 [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
482 S3C24XX_DMA_CHANREQ(5, 3),
483 },
484 [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
485 [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
486 [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
487 [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
488};
489
490static const struct dma_slave_map s3c2440_dma_slave_map[] = {
491
492
493 { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
494 { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0 },
495 { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0 },
496 { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1 },
497 { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1 },
498 { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
499 { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
500 { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
501 { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
502 { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
503 { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
504 { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
505 { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
506
507 { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
508 { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
509 { "samsung-ac97", "rx", (void *)DMACH_PCM_IN },
510 { "samsung-ac97", "tx", (void *)DMACH_PCM_OUT },
511 { "samsung-ac97", "rx", (void *)DMACH_MIC_IN },
512 { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
513 { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
514 { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
515 { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
516 { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
517 { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
518 { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
519 { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
520};
521
522static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
523 .num_phy_channels = 4,
524 .channels = s3c2440_dma_channels,
525 .num_channels = DMACH_MAX,
526 .slave_map = s3c2440_dma_slave_map,
527 .slavecnt = ARRAY_SIZE(s3c2440_dma_slave_map),
528};
529
530struct platform_device s3c2440_device_dma = {
531 .name = "s3c2410-dma",
532 .id = 0,
533 .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
534 .resource = s3c2410_dma_resource,
535 .dev = {
536 .dma_mask = &s3c24xx_device_dma_mask,
537 .coherent_dma_mask = DMA_BIT_MASK(32),
538 .platform_data = &s3c2440_dma_platdata,
539 },
540};
541#endif
542
543#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
544static struct resource s3c2443_dma_resource[] = {
545 [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
546 [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
547 [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
548 [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
549 [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
550 [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
551 [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
552};
553
554static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
555 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
556 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
557 [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
558 [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
559 [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
560 [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
561 [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
562 [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
563 [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
564 [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
565 [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
566 [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
567 [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
568 [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
569 [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
570 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
571 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
572 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
573 [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
574 [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
575 [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
576};
577
578static const struct dma_slave_map s3c2443_dma_slave_map[] = {
579 { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
580 { "s3c2443-spi.0", "rx", (void *)DMACH_SPI0_RX },
581 { "s3c2443-spi.0", "tx", (void *)DMACH_SPI0_TX },
582 { "s3c2443-spi.1", "rx", (void *)DMACH_SPI1_RX },
583 { "s3c2443-spi.1", "tx", (void *)DMACH_SPI1_TX },
584 { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
585 { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
586 { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
587 { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
588 { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
589 { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
590 { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
591 { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
592 { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
593 { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
594};
595
596static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
597 .num_phy_channels = 6,
598 .channels = s3c2443_dma_channels,
599 .num_channels = DMACH_MAX,
600 .slave_map = s3c2443_dma_slave_map,
601 .slavecnt = ARRAY_SIZE(s3c2443_dma_slave_map),
602};
603
604struct platform_device s3c2443_device_dma = {
605 .name = "s3c2443-dma",
606 .id = 0,
607 .num_resources = ARRAY_SIZE(s3c2443_dma_resource),
608 .resource = s3c2443_dma_resource,
609 .dev = {
610 .dma_mask = &s3c24xx_device_dma_mask,
611 .coherent_dma_mask = DMA_BIT_MASK(32),
612 .platform_data = &s3c2443_dma_platdata,
613 },
614};
615#endif
616
617#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
618void __init s3c2410_init_clocks(int xtal)
619{
620 s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
621}
622#endif
623
624#ifdef CONFIG_CPU_S3C2412
625void __init s3c2412_init_clocks(int xtal)
626{
627 s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
628}
629#endif
630
631#ifdef CONFIG_CPU_S3C2416
632void __init s3c2416_init_clocks(int xtal)
633{
634 s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
635}
636#endif
637
638#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
639void __init s3c2440_init_clocks(int xtal)
640{
641 s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
642}
643#endif
644
645#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
646void __init s3c2442_init_clocks(int xtal)
647{
648 s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
649}
650#endif
651
652#ifdef CONFIG_CPU_S3C2443
653void __init s3c2443_init_clocks(int xtal)
654{
655 s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
656}
657#endif
658
659#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
660 defined(CONFIG_CPU_S3C2442)
661static struct resource s3c2410_dclk_resource[] = {
662 [0] = DEFINE_RES_MEM(0x56000084, 0x4),
663};
664
665struct platform_device s3c2410_device_dclk = {
666 .name = "s3c2410-dclk",
667 .id = 0,
668 .num_resources = ARRAY_SIZE(s3c2410_dclk_resource),
669 .resource = s3c2410_dclk_resource,
670};
671#endif
672
