1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright 2008 Openmoko, Inc. 4 * Copyright 2008 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * http://armlinux.simtec.co.uk/ 7 * 8 * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c 9 */ 10 11#ifndef __MACH_S3C64XX_PM_CORE_H 12#define __MACH_S3C64XX_PM_CORE_H __FILE__ 13 14#include <linux/serial_s3c.h> 15#include <linux/delay.h> 16 17#include <mach/regs-gpio.h> 18#include <mach/regs-clock.h> 19#include <mach/map.h> 20 21static inline void s3c_pm_debug_init_uart(void) 22{ 23 u32 tmp = __raw_readl(S3C_PCLK_GATE); 24 25 /* As a note, since the S3C64XX UARTs generally have multiple 26 * clock sources, we simply enable PCLK at the moment and hope 27 * that the resume settings for the UART are suitable for the 28 * use with PCLK. 29 */ 30 31 tmp |= S3C_CLKCON_PCLK_UART0; 32 tmp |= S3C_CLKCON_PCLK_UART1; 33 tmp |= S3C_CLKCON_PCLK_UART2; 34 tmp |= S3C_CLKCON_PCLK_UART3; 35 36 __raw_writel(tmp, S3C_PCLK_GATE); 37 udelay(10); 38} 39 40static inline void s3c_pm_arch_prepare_irqs(void) 41{ 42 /* VIC should have already been taken care of */ 43 44 /* clear any pending EINT0 interrupts */ 45 __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); 46} 47 48static inline void s3c_pm_arch_stop_clocks(void) 49{ 50} 51 52static inline void s3c_pm_arch_show_resume_irqs(void) 53{ 54} 55 56/* make these defines, we currently do not have any need to change 57 * the IRQ wake controls depending on the CPU we are running on */ 58#ifdef CONFIG_PM_SLEEP 59#define s3c_irqwake_eintallow ((1 << 28) - 1) 60#define s3c_irqwake_intallow (~0) 61#else 62#define s3c_irqwake_eintallow 0 63#define s3c_irqwake_intallow 0 64#endif 65 66static inline void s3c_pm_arch_update_uart(void __iomem *regs, 67 struct pm_uart_save *save) 68{ 69 u32 ucon = __raw_readl(regs + S3C2410_UCON); 70 u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; 71 u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; 72 u32 new_ucon; 73 u32 delta; 74 75 /* S3C64XX UART blocks only support level interrupts, so ensure that 76 * when we restore unused UART blocks we force the level interrupt 77 * settigs. */ 78 save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; 79 80 /* We have a constraint on changing the clock type of the UART 81 * between UCLKx and PCLK, so ensure that when we restore UCON 82 * that the CLK field is correctly modified if the bootloader 83 * has changed anything. 84 */ 85 if (ucon_clk != save_clk) { 86 new_ucon = save->ucon; 87 delta = ucon_clk ^ save_clk; 88 89 /* change from UCLKx => wrong PCLK, 90 * either UCLK can be tested for by a bit-test 91 * with UCLK0 */ 92 if (ucon_clk & S3C6400_UCON_UCLK0 && 93 !(save_clk & S3C6400_UCON_UCLK0) && 94 delta & S3C6400_UCON_PCLK2) { 95 new_ucon &= ~S3C6400_UCON_UCLK0; 96 } else if (delta == S3C6400_UCON_PCLK2) { 97 /* as an precaution, don't change from 98 * PCLK2 => PCLK or vice-versa */ 99 new_ucon ^= S3C6400_UCON_PCLK2; 100 } 101 102 S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", 103 ucon, new_ucon, save->ucon); 104 save->ucon = new_ucon; 105 } 106} 107 108static inline void s3c_pm_restored_gpios(void) 109{ 110 /* ensure sleep mode has been cleared from the system */ 111 112 __raw_writel(0, S3C64XX_SLPEN); 113} 114 115static inline void samsung_pm_saved_gpios(void) 116{ 117 /* turn on the sleep mode and keep it there, as it seems that during 118 * suspend the xCON registers get re-set and thus you can end up with 119 * problems between going to sleep and resuming. 120 */ 121 122 __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); 123} 124#endif /* __MACH_S3C64XX_PM_CORE_H */ 125