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26#include <linux/linkage.h>
27#include <linux/init.h>
28#include <asm/assembler.h>
29#include <asm/asm-offsets.h>
30#include <asm/hwcap.h>
31#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h>
33#include <asm/ptrace.h>
34
35#include "proc-macros.S"
36
37
38
39
40
41
42
43
44
45#define MAX_AREA_SIZE 32768
46
47
48
49
50#define CACHE_DLINESIZE 32
51
52
53
54
55#define CACHE_DSEGMENTS 16
56
57
58
59
60#define CACHE_DENTRIES 64
61
62
63
64
65
66
67#define CACHE_DLIMIT 32768
68
69 .text
70
71
72
73ENTRY(cpu_arm1020_proc_init)
74 ret lr
75
76
77
78
79ENTRY(cpu_arm1020_proc_fin)
80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0,
82 bic r0, r0,
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
84 ret lr
85
86
87
88
89
90
91
92
93
94
95 .align 5
96 .pushsection .idmap.text, "ax"
97ENTRY(cpu_arm1020_reset)
98 mov ip,
99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
100 mcr p15, 0, ip, c7, c10, 4 @ drain WB
101#ifdef CONFIG_MMU
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103#endif
104 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
105 bic ip, ip,
106 bic ip, ip,
107 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
108 ret r0
109ENDPROC(cpu_arm1020_reset)
110 .popsection
111
112
113
114
115 .align 5
116ENTRY(cpu_arm1020_do_idle)
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 ret lr
119
120
121
122 .align 5
123
124
125
126
127
128
129ENTRY(arm1020_flush_icache_all)
130#ifndef CONFIG_CPU_ICACHE_DISABLE
131 mov r0,
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
133#endif
134 ret lr
135ENDPROC(arm1020_flush_icache_all)
136
137
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139
140
141
142
143ENTRY(arm1020_flush_user_cache_all)
144
145
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147
148
149
150ENTRY(arm1020_flush_kern_cache_all)
151 mov r2,
152 mov ip,
153__flush_whole_cache:
154#ifndef CONFIG_CPU_DCACHE_DISABLE
155 mcr p15, 0, ip, c7, c10, 4 @ drain WB
156 mov r1,
1571: orr r3, r1,
1582: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
159 mcr p15, 0, ip, c7, c10, 4 @ drain WB
160 subs r3, r3,
161 bcs 2b @ entries 63 to 0
162 subs r1, r1,
163 bcs 1b @ segments 15 to 0
164#endif
165 tst r2,
166#ifndef CONFIG_CPU_ICACHE_DISABLE
167 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
168#endif
169 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
170 ret lr
171
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179
180
181
182ENTRY(arm1020_flush_user_cache_range)
183 mov ip,
184 sub r3, r1, r0 @ calculate total size
185 cmp r3,
186 bhs __flush_whole_cache
187
188#ifndef CONFIG_CPU_DCACHE_DISABLE
189 mcr p15, 0, ip, c7, c10, 4
1901: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
191 mcr p15, 0, ip, c7, c10, 4 @ drain WB
192 add r0, r0,
193 cmp r0, r1
194 blo 1b
195#endif
196 tst r2,
197#ifndef CONFIG_CPU_ICACHE_DISABLE
198 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
199#endif
200 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
201 ret lr
202
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211
212
213ENTRY(arm1020_coherent_kern_range)
214
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224
225
226ENTRY(arm1020_coherent_user_range)
227 mov ip,
228 bic r0, r0,
229 mcr p15, 0, ip, c7, c10, 4
2301:
231#ifndef CONFIG_CPU_DCACHE_DISABLE
232 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
233 mcr p15, 0, ip, c7, c10, 4 @ drain WB
234#endif
235#ifndef CONFIG_CPU_ICACHE_DISABLE
236 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
237#endif
238 add r0, r0,
239 cmp r0, r1
240 blo 1b
241 mcr p15, 0, ip, c7, c10, 4 @ drain WB
242 mov r0,
243 ret lr
244
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251
252
253
254ENTRY(arm1020_flush_kern_dcache_area)
255 mov ip,
256#ifndef CONFIG_CPU_DCACHE_DISABLE
257 add r1, r0, r1
2581: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
259 mcr p15, 0, ip, c7, c10, 4 @ drain WB
260 add r0, r0,
261 cmp r0, r1
262 blo 1b
263#endif
264 mcr p15, 0, ip, c7, c10, 4 @ drain WB
265 ret lr
266
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278
279
280arm1020_dma_inv_range:
281 mov ip,
282#ifndef CONFIG_CPU_DCACHE_DISABLE
283 tst r0,
284 bic r0, r0,
285 mcrne p15, 0, ip, c7, c10, 4
286 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
287 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
288 tst r1,
289 mcrne p15, 0, ip, c7, c10, 4
290 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
291 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
2921: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
293 add r0, r0,
294 cmp r0, r1
295 blo 1b
296#endif
297 mcr p15, 0, ip, c7, c10, 4 @ drain WB
298 ret lr
299
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309
310arm1020_dma_clean_range:
311 mov ip,
312#ifndef CONFIG_CPU_DCACHE_DISABLE
313 bic r0, r0,
3141: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
315 mcr p15, 0, ip, c7, c10, 4 @ drain WB
316 add r0, r0,
317 cmp r0, r1
318 blo 1b
319#endif
320 mcr p15, 0, ip, c7, c10, 4 @ drain WB
321 ret lr
322
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329
330
331ENTRY(arm1020_dma_flush_range)
332 mov ip,
333#ifndef CONFIG_CPU_DCACHE_DISABLE
334 bic r0, r0,
335 mcr p15, 0, ip, c7, c10, 4
3361: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
337 mcr p15, 0, ip, c7, c10, 4 @ drain WB
338 add r0, r0,
339 cmp r0, r1
340 blo 1b
341#endif
342 mcr p15, 0, ip, c7, c10, 4 @ drain WB
343 ret lr
344
345
346
347
348
349
350
351ENTRY(arm1020_dma_map_area)
352 add r1, r1, r0
353 cmp r2,
354 beq arm1020_dma_clean_range
355 bcs arm1020_dma_inv_range
356 b arm1020_dma_flush_range
357ENDPROC(arm1020_dma_map_area)
358
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364
365ENTRY(arm1020_dma_unmap_area)
366 ret lr
367ENDPROC(arm1020_dma_unmap_area)
368
369 .globl arm1020_flush_kern_cache_louis
370 .equ arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all
371
372 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
373 define_cache_functions arm1020
374
375 .align 5
376ENTRY(cpu_arm1020_dcache_clean_area)
377#ifndef CONFIG_CPU_DCACHE_DISABLE
378 mov ip,
3791: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
380 mcr p15, 0, ip, c7, c10, 4 @ drain WB
381 add r0, r0,
382 subs r1, r1,
383 bhi 1b
384#endif
385 ret lr
386
387
388
389
390
391
392
393
394
395
396 .align 5
397ENTRY(cpu_arm1020_switch_mm)
398#ifdef CONFIG_MMU
399#ifndef CONFIG_CPU_DCACHE_DISABLE
400 mcr p15, 0, r3, c7, c10, 4
401 mov r1,
4021: mov r3,
4032: mov ip, r3, LSL
404 orr ip, ip, r1, LSL
405 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
406 mov ip,
407 mcr p15, 0, ip, c7, c10, 4
408 subs r3, r3,
409 cmp r3,
410 bge 2b @ entries 3F to 0
411 subs r1, r1,
412 cmp r1,
413 bge 1b @ segments 15 to 0
414
415#endif
416 mov r1,
417#ifndef CONFIG_CPU_ICACHE_DISABLE
418 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
419#endif
420 mcr p15, 0, r1, c7, c10, 4 @ drain WB
421 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
422 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
423#endif
424 ret lr
425
426
427
428
429
430
431 .align 5
432ENTRY(cpu_arm1020_set_pte_ext)
433#ifdef CONFIG_MMU
434 armv3_set_pte_ext
435 mov r0, r0
436#ifndef CONFIG_CPU_DCACHE_DISABLE
437 mcr p15, 0, r0, c7, c10, 4
438 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
439#endif
440 mcr p15, 0, r0, c7, c10, 4 @ drain WB
441#endif
442 ret lr
443
444 .type __arm1020_setup,
445__arm1020_setup:
446 mov r0,
447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
448 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
449#ifdef CONFIG_MMU
450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
451#endif
452
453 adr r5, arm1020_crval
454 ldmia r5, {r5, r6}
455 mrc p15, 0, r0, c1, c0 @ get control register v4
456 bic r0, r0, r5
457 orr r0, r0, r6
458#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
459 orr r0, r0,
460#endif
461 ret lr
462 .size __arm1020_setup, . - __arm1020_setup
463
464
465
466
467
468
469 .type arm1020_crval,
470arm1020_crval:
471 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
472
473 __INITDATA
474 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
475 define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
476
477
478 .section ".rodata"
479
480 string cpu_arch_name, "armv5t"
481 string cpu_elf_name, "v5"
482
483 .type cpu_arm1020_name,
484cpu_arm1020_name:
485 .ascii "ARM1020"
486#ifndef CONFIG_CPU_ICACHE_DISABLE
487 .ascii "i"
488#endif
489#ifndef CONFIG_CPU_DCACHE_DISABLE
490 .ascii "d"
491#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
492 .ascii "(wt)"
493#else
494 .ascii "(wb)"
495#endif
496#endif
497#ifndef CONFIG_CPU_BPREDICT_DISABLE
498 .ascii "B"
499#endif
500#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
501 .ascii "RR"
502#endif
503 .ascii "\0"
504 .size cpu_arm1020_name, . - cpu_arm1020_name
505
506 .align
507
508 .section ".proc.info.init",
509
510 .type __arm1020_proc_info,
511__arm1020_proc_info:
512 .long 0x4104a200 @ ARM 1020T (Architecture v5T)
513 .long 0xff0ffff0
514 .long PMD_TYPE_SECT | \
515 PMD_SECT_AP_WRITE | \
516 PMD_SECT_AP_READ
517 .long PMD_TYPE_SECT | \
518 PMD_SECT_AP_WRITE | \
519 PMD_SECT_AP_READ
520 initfn __arm1020_setup, __arm1020_proc_info
521 .long cpu_arch_name
522 .long cpu_elf_name
523 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
524 .long cpu_arm1020_name
525 .long arm1020_processor_functions
526 .long v4wbi_tlb_fns
527 .long v4wb_user_fns
528 .long arm1020_cache_fns
529 .size __arm1020_proc_info, . - __arm1020_proc_info
530