LXR linux/arch/arm64/include/asm/hw

   1/*
   2 * Copyright (C) 2012 ARM Ltd.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15 */
  16#ifndef __ASM_HW_BREAKPOINT_H
  17#define __ASM_HW_BREAKPOINT_H
  18
  19#include <asm/cputype.h>
  20#include <asm/cpufeature.h>
  21#include <asm/sysreg.h>
  22#include <asm/virt.h>
  23
  24#ifdef __KERNEL__
  25
  26struct arch_hw_breakpoint_ctrl {
  27        u32 __reserved  : 19,
  28        len             : 8,
  29        type            : 2,
  30        privilege       : 2,
  31        enabled         : 1;
  32};
  33
  34struct arch_hw_breakpoint {
  35        u64 address;
  36        u64 trigger;
  37        struct arch_hw_breakpoint_ctrl ctrl;
  38};
  39
  40/* Privilege Levels */
  41#define AARCH64_BREAKPOINT_EL1  1
  42#define AARCH64_BREAKPOINT_EL0  2
  43
  44#define DBG_HMC_HYP             (1 << 13)
  45
  46static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
  47{
  48        u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |
  49                ctrl.enabled;
  50
  51        if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1)
  52                val |= DBG_HMC_HYP;
  53
  54        return val;
  55}
  56
  57static inline void decode_ctrl_reg(u32 reg,
  58                                   struct arch_hw_breakpoint_ctrl *ctrl)
  59{
  60        ctrl->enabled   = reg & 0x1;
  61        reg >>= 1;
  62        ctrl->privilege = reg & 0x3;
  63        reg >>= 2;
  64        ctrl->type      = reg & 0x3;
  65        reg >>= 2;
  66        ctrl->len       = reg & 0xff;
  67}
  68
  69/* Breakpoint */
  70#define ARM_BREAKPOINT_EXECUTE  0
  71
  72/* Watchpoints */
  73#define ARM_BREAKPOINT_LOAD     1
  74#define ARM_BREAKPOINT_STORE    2
  75#define AARCH64_ESR_ACCESS_MASK (1 << 6)
  76
  77/* Lengths */
  78#define ARM_BREAKPOINT_LEN_1    0x1
  79#define ARM_BREAKPOINT_LEN_2    0x3
  80#define ARM_BREAKPOINT_LEN_3    0x7
  81#define ARM_BREAKPOINT_LEN_4    0xf
  82#define ARM_BREAKPOINT_LEN_5    0x1f
  83#define ARM_BREAKPOINT_LEN_6    0x3f
  84#define ARM_BREAKPOINT_LEN_7    0x7f
  85#define ARM_BREAKPOINT_LEN_8    0xff
  86
  87/* Kernel stepping */
  88#define ARM_KERNEL_STEP_NONE    0
  89#define ARM_KERNEL_STEP_ACTIVE  1
  90#define ARM_KERNEL_STEP_SUSPEND 2
  91
  92/*
  93 * Limits.
  94 * Changing these will require modifications to the register accessors.
  95 */
  96#define ARM_MAX_BRP             16
  97#define ARM_MAX_WRP             16
  98
  99/* Virtual debug register bases. */
 100#define AARCH64_DBG_REG_BVR     0
 101#define AARCH64_DBG_REG_BCR     (AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
 102#define AARCH64_DBG_REG_WVR     (AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
 103#define AARCH64_DBG_REG_WCR     (AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
 104
 105/* Debug register names. */
 106#define AARCH64_DBG_REG_NAME_BVR        bvr
 107#define AARCH64_DBG_REG_NAME_BCR        bcr
 108#define AARCH64_DBG_REG_NAME_WVR        wvr
 109#define AARCH64_DBG_REG_NAME_WCR        wcr
 110
 111/* Accessor macros for the debug registers. */
 112#define AARCH64_DBG_READ(N, REG, VAL) do {\
 113        VAL = read_sysreg(dbg##REG##N##_el1);\
 114} while (0)
 115
 116#define AARCH64_DBG_WRITE(N, REG, VAL) do {\
 117        write_sysreg(VAL, dbg##REG##N##_el1);\
 118} while (0)
 119
 120struct task_struct;
 121struct notifier_block;
 122struct perf_event;
 123struct pmu;
 124
 125extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
 126                                  int *gen_len, int *gen_type, int *offset);
 127extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
 128extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
 129extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
 130                                           unsigned long val, void *data);
 131
 132extern int arch_install_hw_breakpoint(struct perf_event *bp);
 133extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
 134extern void hw_breakpoint_pmu_read(struct perf_event *bp);
 135extern int hw_breakpoint_slots(int type);
 136
 137#ifdef CONFIG_HAVE_HW_BREAKPOINT
 138extern void hw_breakpoint_thread_switch(struct task_struct *next);
 139extern void ptrace_hw_copy_thread(struct task_struct *task);
 140#else
 141static inline void hw_breakpoint_thread_switch(struct task_struct *next)
 142{
 143}
 144static inline void ptrace_hw_copy_thread(struct task_struct *task)
 145{
 146}
 147#endif
 148
 149/* Determine number of BRP registers available. */
 150static inline int get_num_brps(void)
 151{
 152        u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
 153        return 1 +
 154                cpuid_feature_extract_unsigned_field(dfr0,
 155                                                ID_AA64DFR0_BRPS_SHIFT);
 156}
 157
 158/* Determine number of WRP registers available. */
 159static inline int get_num_wrps(void)
 160{
 161        u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
 162        return 1 +
 163                cpuid_feature_extract_unsigned_field(dfr0,
 164                                                ID_AA64DFR0_WRPS_SHIFT);
 165}
 166
 167#endif  /* __KERNEL__ */
 168#endif  /* __ASM_BREAKPOINT_H */
 169