LXR linux/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef __iop_sap_in_defs_h
   3#define __iop_sap_in_defs_h
   4
   5/*
   6 * This file is autogenerated from
   7 *   file:           iop_sap_in.r
   8 * 
   9 *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r
  10 * Any changes here will be lost.
  11 *
  12 * -*- buffer-read-only: t -*-
  13 */
  14/* Main access macros */
  15#ifndef REG_RD
  16#define REG_RD( scope, inst, reg ) \
  17  REG_READ( reg_##scope##_##reg, \
  18            (inst) + REG_RD_ADDR_##scope##_##reg )
  19#endif
  20
  21#ifndef REG_WR
  22#define REG_WR( scope, inst, reg, val ) \
  23  REG_WRITE( reg_##scope##_##reg, \
  24             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  25#endif
  26
  27#ifndef REG_RD_VECT
  28#define REG_RD_VECT( scope, inst, reg, index ) \
  29  REG_READ( reg_##scope##_##reg, \
  30            (inst) + REG_RD_ADDR_##scope##_##reg + \
  31            (index) * STRIDE_##scope##_##reg )
  32#endif
  33
  34#ifndef REG_WR_VECT
  35#define REG_WR_VECT( scope, inst, reg, index, val ) \
  36  REG_WRITE( reg_##scope##_##reg, \
  37             (inst) + REG_WR_ADDR_##scope##_##reg + \
  38             (index) * STRIDE_##scope##_##reg, (val) )
  39#endif
  40
  41#ifndef REG_RD_INT
  42#define REG_RD_INT( scope, inst, reg ) \
  43  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  44#endif
  45
  46#ifndef REG_WR_INT
  47#define REG_WR_INT( scope, inst, reg, val ) \
  48  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  49#endif
  50
  51#ifndef REG_RD_INT_VECT
  52#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  53  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  54            (index) * STRIDE_##scope##_##reg )
  55#endif
  56
  57#ifndef REG_WR_INT_VECT
  58#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  59  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  60             (index) * STRIDE_##scope##_##reg, (val) )
  61#endif
  62
  63#ifndef REG_TYPE_CONV
  64#define REG_TYPE_CONV( type, orgtype, val ) \
  65  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  66#endif
  67
  68#ifndef reg_page_size
  69#define reg_page_size 8192
  70#endif
  71
  72#ifndef REG_ADDR
  73#define REG_ADDR( scope, inst, reg ) \
  74  ( (inst) + REG_RD_ADDR_##scope##_##reg )
  75#endif
  76
  77#ifndef REG_ADDR_VECT
  78#define REG_ADDR_VECT( scope, inst, reg, index ) \
  79  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  80    (index) * STRIDE_##scope##_##reg )
  81#endif
  82
  83/* C-code for register scope iop_sap_in */
  84
  85#define STRIDE_iop_sap_in_rw_bus_byte 4
  86/* Register rw_bus_byte, scope iop_sap_in, type rw */
  87typedef struct {
  88  unsigned int sync_sel     : 2;
  89  unsigned int sync_ext_src : 3;
  90  unsigned int sync_edge    : 2;
  91  unsigned int delay        : 2;
  92  unsigned int dummy1       : 23;
  93} reg_iop_sap_in_rw_bus_byte;
  94#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0
  95#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0
  96
  97#define STRIDE_iop_sap_in_rw_gio 4
  98/* Register rw_gio, scope iop_sap_in, type rw */
  99typedef struct {
 100  unsigned int sync_sel     : 2;
 101  unsigned int sync_ext_src : 3;
 102  unsigned int sync_edge    : 2;
 103  unsigned int delay        : 2;
 104  unsigned int logic        : 2;
 105  unsigned int dummy1       : 21;
 106} reg_iop_sap_in_rw_gio;
 107#define REG_RD_ADDR_iop_sap_in_rw_gio 16
 108#define REG_WR_ADDR_iop_sap_in_rw_gio 16
 109
 110
 111/* Constants */
 112enum {
 113  regk_iop_sap_in_and                      = 0x00000002,
 114  regk_iop_sap_in_ext_clk200               = 0x00000003,
 115  regk_iop_sap_in_gio0                     = 0x00000000,
 116  regk_iop_sap_in_gio12                    = 0x00000003,
 117  regk_iop_sap_in_gio16                    = 0x00000004,
 118  regk_iop_sap_in_gio20                    = 0x00000005,
 119  regk_iop_sap_in_gio24                    = 0x00000006,
 120  regk_iop_sap_in_gio28                    = 0x00000007,
 121  regk_iop_sap_in_gio4                     = 0x00000001,
 122  regk_iop_sap_in_gio8                     = 0x00000002,
 123  regk_iop_sap_in_inv                      = 0x00000001,
 124  regk_iop_sap_in_neg                      = 0x00000002,
 125  regk_iop_sap_in_no                       = 0x00000000,
 126  regk_iop_sap_in_no_del_ext_clk200        = 0x00000002,
 127  regk_iop_sap_in_none                     = 0x00000000,
 128  regk_iop_sap_in_one                      = 0x00000001,
 129  regk_iop_sap_in_or                       = 0x00000003,
 130  regk_iop_sap_in_pos                      = 0x00000001,
 131  regk_iop_sap_in_pos_neg                  = 0x00000003,
 132  regk_iop_sap_in_rw_bus_byte_default      = 0x00000000,
 133  regk_iop_sap_in_rw_bus_byte_size         = 0x00000004,
 134  regk_iop_sap_in_rw_gio_default           = 0x00000000,
 135  regk_iop_sap_in_rw_gio_size              = 0x00000020,
 136  regk_iop_sap_in_timer_grp0_tmr3          = 0x00000000,
 137  regk_iop_sap_in_timer_grp1_tmr3          = 0x00000001,
 138  regk_iop_sap_in_tmr_clk200               = 0x00000001,
 139  regk_iop_sap_in_two                      = 0x00000002,
 140  regk_iop_sap_in_two_clk200               = 0x00000000
 141};
 142#endif /* __iop_sap_in_defs_h */
 143