linux/arch/m68k/include/asm/m54xxsim.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 *      m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
   4 */
   5
   6#ifndef m54xxsim_h
   7#define m54xxsim_h
   8
   9#define CPU_NAME                "COLDFIRE(m54xx)"
  10#define CPU_INSTR_PER_JIFFY     2
  11#define MCF_BUSCLK              (MCF_CLK / 2)
  12#define MACHINE                 MACH_M54XX
  13#define FPUTYPE                 FPU_COLDFIRE
  14#define IOMEMBASE               MCF_MBAR
  15#define IOMEMSIZE               0x01000000
  16
  17#include <asm/m54xxacr.h>
  18
  19#define MCFINT_VECBASE          64
  20
  21/*
  22 *      Interrupt Controller Registers
  23 */
  24#define MCFICM_INTC0            (MCF_MBAR + 0x700)      /* Base for Interrupt Ctrl 0 */
  25
  26#define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
  27#define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
  28#define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
  29#define MCFINTC_IMRL            0x0c            /* Interrupt mask 1-31 */
  30#define MCFINTC_INTFRCH         0x10            /* Interrupt force 32-63 */
  31#define MCFINTC_INTFRCL         0x14            /* Interrupt force 1-31 */
  32#define MCFINTC_IRLR            0x18            /* */
  33#define MCFINTC_IACKL           0x19            /* */
  34#define MCFINTC_ICR0            0x40            /* Base ICR register */
  35
  36/*
  37 *      UART module.
  38 */
  39#define MCFUART_BASE0           (MCF_MBAR + 0x8600)     /* Base address UART0 */
  40#define MCFUART_BASE1           (MCF_MBAR + 0x8700)     /* Base address UART1 */
  41#define MCFUART_BASE2           (MCF_MBAR + 0x8800)     /* Base address UART2 */
  42#define MCFUART_BASE3           (MCF_MBAR + 0x8900)     /* Base address UART3 */
  43
  44/*
  45 *      Define system peripheral IRQ usage.
  46 */
  47#define MCF_IRQ_TIMER           (MCFINT_VECBASE + 54)   /* Slice Timer 0 */
  48#define MCF_IRQ_PROFILER        (MCFINT_VECBASE + 53)   /* Slice Timer 1 */
  49#define MCF_IRQ_I2C0            (MCFINT_VECBASE + 40)
  50#define MCF_IRQ_UART0           (MCFINT_VECBASE + 35)
  51#define MCF_IRQ_UART1           (MCFINT_VECBASE + 34)
  52#define MCF_IRQ_UART2           (MCFINT_VECBASE + 33)
  53#define MCF_IRQ_UART3           (MCFINT_VECBASE + 32)
  54
  55/*
  56 *      Slice Timer support.
  57 */
  58#define MCFSLT_TIMER0           (MCF_MBAR + 0x900)      /* Base addr TIMER0 */
  59#define MCFSLT_TIMER1           (MCF_MBAR + 0x910)      /* Base addr TIMER1 */
  60
  61/*
  62 *      Generic GPIO support
  63 */
  64#define MCFGPIO_PODR            (MCF_MBAR + 0xA00)
  65#define MCFGPIO_PDDR            (MCF_MBAR + 0xA10)
  66#define MCFGPIO_PPDR            (MCF_MBAR + 0xA20)
  67#define MCFGPIO_SETR            (MCF_MBAR + 0xA20)
  68#define MCFGPIO_CLRR            (MCF_MBAR + 0xA30)
  69
  70#define MCFGPIO_PIN_MAX         136     /* 128 gpio + 8 eport */
  71#define MCFGPIO_IRQ_MAX         8
  72#define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
  73
  74/*
  75 *      EDGE Port support.
  76 */
  77#define MCFEPORT_EPPAR          (MCF_MBAR + 0xf00)      /* Pin assignment */
  78#define MCFEPORT_EPDDR          (MCF_MBAR + 0xf04)      /* Data direction */
  79#define MCFEPORT_EPIER          (MCF_MBAR + 0xf05)      /* Interrupt enable */
  80#define MCFEPORT_EPDR           (MCF_MBAR + 0xf08)      /* Port data (w) */
  81#define MCFEPORT_EPPDR          (MCF_MBAR + 0xf09)      /* Port data (r) */
  82#define MCFEPORT_EPFR           (MCF_MBAR + 0xf0c)      /* Flags */
  83
  84/*
  85 *      Pin Assignment register definitions
  86 */
  87#define MCFGPIO_PAR_FBCTL       (MCF_MBAR + 0xA40)
  88#define MCFGPIO_PAR_FBCS        (MCF_MBAR + 0xA42)
  89#define MCFGPIO_PAR_DMA         (MCF_MBAR + 0xA43)
  90#define MCFGPIO_PAR_FECI2CIRQ   (MCF_MBAR + 0xA44)
  91#define MCFGPIO_PAR_PCIBG       (MCF_MBAR + 0xA48)      /* PCI bus grant */
  92#define MCFGPIO_PAR_PCIBR       (MCF_MBAR + 0xA4A)      /* PCI */
  93#define MCFGPIO_PAR_PSC0        (MCF_MBAR + 0xA4F)
  94#define MCFGPIO_PAR_PSC1        (MCF_MBAR + 0xA4E)
  95#define MCFGPIO_PAR_PSC2        (MCF_MBAR + 0xA4D)
  96#define MCFGPIO_PAR_PSC3        (MCF_MBAR + 0xA4C)
  97#define MCFGPIO_PAR_DSPI        (MCF_MBAR + 0xA50)
  98#define MCFGPIO_PAR_TIMER       (MCF_MBAR + 0xA52)
  99
 100#define MCF_PAR_SDA             (0x0008)
 101#define MCF_PAR_SCL             (0x0004)
 102#define MCF_PAR_PSC_TXD         (0x04)
 103#define MCF_PAR_PSC_RXD         (0x08)
 104#define MCF_PAR_PSC_CTS_GPIO    (0x00)
 105#define MCF_PAR_PSC_CTS_BCLK    (0x80)
 106#define MCF_PAR_PSC_CTS_CTS     (0xC0)
 107#define MCF_PAR_PSC_RTS_GPIO    (0x00)
 108#define MCF_PAR_PSC_RTS_FSYNC   (0x20)
 109#define MCF_PAR_PSC_RTS_RTS     (0x30)
 110#define MCF_PAR_PSC_CANRX       (0x40)
 111
 112#define MCF_PAR_FECI2CIRQ       (MCF_MBAR + 0x00000a44) /* FEC/I2C/IRQ */
 113#define MCF_PAR_FECI2CIRQ_SDA   (1 << 3)
 114#define MCF_PAR_FECI2CIRQ_SCL   (1 << 2)
 115
 116/*
 117 * I2C module.
 118 */
 119#define MCFI2C_BASE0            (MCF_MBAR + 0x8f00)
 120#define MCFI2C_SIZE0            0x40
 121
 122#endif  /* m54xxsim_h */
 123