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14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19
20#include <asm/ptrace.h>
21#include <asm/traps.h>
22
23#include <asm/q40_master.h>
24#include <asm/q40ints.h>
25
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32
33
34
35
36static void q40_irq_handler(unsigned int, struct pt_regs *fp);
37static void q40_irq_enable(struct irq_data *data);
38static void q40_irq_disable(struct irq_data *data);
39
40unsigned short q40_ablecount[35];
41unsigned short q40_state[35];
42
43static unsigned int q40_irq_startup(struct irq_data *data)
44{
45 unsigned int irq = data->irq;
46
47
48 switch (irq) {
49 case 1: case 2: case 8: case 9:
50 case 11: case 12: case 13:
51 pr_warn("%s: ISA IRQ %d not implemented by HW\n", __func__,
52 irq);
53
54 }
55 return 0;
56}
57
58static void q40_irq_shutdown(struct irq_data *data)
59{
60}
61
62static struct irq_chip q40_irq_chip = {
63 .name = "q40",
64 .irq_startup = q40_irq_startup,
65 .irq_shutdown = q40_irq_shutdown,
66 .irq_enable = q40_irq_enable,
67 .irq_disable = q40_irq_disable,
68};
69
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80
81static int disabled;
82
83void __init q40_init_IRQ(void)
84{
85 m68k_setup_irq_controller(&q40_irq_chip, handle_simple_irq, 1,
86 Q40_IRQ_MAX);
87
88
89 m68k_setup_auto_interrupt(q40_irq_handler);
90
91 m68k_irq_startup_irq(IRQ_AUTO_2);
92 m68k_irq_startup_irq(IRQ_AUTO_4);
93
94
95 master_outb(1, EXT_ENABLE_REG);
96
97
98 master_outb(0, KEY_IRQ_ENABLE_REG);
99}
100
101
102
103
104
105
106int ql_ticks;
107static int sound_ticks;
108
109#define SVOL 45
110
111void q40_mksound(unsigned int hz, unsigned int ticks)
112{
113
114
115 if (hz == 0) {
116 if (sound_ticks)
117 sound_ticks = 1;
118
119 *DAC_LEFT = 128;
120 *DAC_RIGHT = 128;
121
122 return;
123 }
124
125 if (sound_ticks == 0)
126 sound_ticks = 1000;
127 sound_ticks = ticks << 1;
128}
129
130static irq_handler_t q40_timer_routine;
131
132static irqreturn_t q40_timer_int (int irq, void * dev)
133{
134 ql_ticks = ql_ticks ? 0 : 1;
135 if (sound_ticks) {
136 unsigned char sval=(sound_ticks & 1) ? 128-SVOL : 128+SVOL;
137 sound_ticks--;
138 *DAC_LEFT=sval;
139 *DAC_RIGHT=sval;
140 }
141
142 if (!ql_ticks)
143 q40_timer_routine(irq, dev);
144 return IRQ_HANDLED;
145}
146
147void q40_sched_init (irq_handler_t timer_routine)
148{
149 int timer_irq;
150
151 q40_timer_routine = timer_routine;
152 timer_irq = Q40_IRQ_FRAME;
153
154 if (request_irq(timer_irq, q40_timer_int, 0,
155 "timer", q40_timer_int))
156 panic("Couldn't register timer int");
157
158 master_outb(-1, FRAME_CLEAR_REG);
159 master_outb( 1, FRAME_RATE_REG);
160}
161
162
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166
167
168
169struct IRQ_TABLE{ unsigned mask; int irq ;};
170#if 0
171static struct IRQ_TABLE iirqs[]={
172 {Q40_IRQ_FRAME_MASK,Q40_IRQ_FRAME},
173 {Q40_IRQ_KEYB_MASK,Q40_IRQ_KEYBOARD},
174 {0,0}};
175#endif
176static struct IRQ_TABLE eirqs[] = {
177 { .mask = Q40_IRQ3_MASK, .irq = 3 },
178 { .mask = Q40_IRQ4_MASK, .irq = 4 },
179 { .mask = Q40_IRQ14_MASK, .irq = 14 },
180 { .mask = Q40_IRQ15_MASK, .irq = 15 },
181 { .mask = Q40_IRQ6_MASK, .irq = 6 },
182 { .mask = Q40_IRQ7_MASK, .irq = 7 },
183 { .mask = Q40_IRQ5_MASK, .irq = 5 },
184 { .mask = Q40_IRQ10_MASK, .irq = 10 },
185 {0,0}
186};
187
188
189static int ccleirq=60;
190
191
192
193
194#define IRQ_INPROGRESS 1
195
196
197
198#define DEBUG_Q40INT
199
200
201static int mext_disabled=0;
202static int aliased_irq=0;
203
204
205
206static void q40_irq_handler(unsigned int irq, struct pt_regs *fp)
207{
208 unsigned mir, mer;
209 int i;
210
211
212 mir = master_inb(IIRQ_REG);
213#ifdef CONFIG_BLK_DEV_FD
214 if ((mir & Q40_IRQ_EXT_MASK) &&
215 (master_inb(EIRQ_REG) & Q40_IRQ6_MASK)) {
216 floppy_hardint();
217 return;
218 }
219#endif
220 switch (irq) {
221 case 4:
222 case 6:
223 do_IRQ(Q40_IRQ_SAMPLE, fp);
224 return;
225 }
226 if (mir & Q40_IRQ_FRAME_MASK) {
227 do_IRQ(Q40_IRQ_FRAME, fp);
228 master_outb(-1, FRAME_CLEAR_REG);
229 }
230 if ((mir & Q40_IRQ_SER_MASK) || (mir & Q40_IRQ_EXT_MASK)) {
231 mer = master_inb(EIRQ_REG);
232 for (i = 0; eirqs[i].mask; i++) {
233 if (mer & eirqs[i].mask) {
234 irq = eirqs[i].irq;
235
236
237
238
239
240
241 if (irq > 4 && irq <= 15 && mext_disabled) {
242
243 goto iirq;
244 }
245 if (q40_state[irq] & IRQ_INPROGRESS) {
246
247
248#ifdef IP_USE_DISABLE
249
250
251 disable_irq(irq);
252 disabled = 1;
253#else
254
255
256 fp->sr = (((fp->sr) & (~0x700))+0x200);
257 disabled = 1;
258#endif
259 goto iirq;
260 }
261 q40_state[irq] |= IRQ_INPROGRESS;
262 do_IRQ(irq, fp);
263 q40_state[irq] &= ~IRQ_INPROGRESS;
264
265
266
267
268
269 if (disabled) {
270#ifdef IP_USE_DISABLE
271 if (irq > 4) {
272 disabled = 0;
273 enable_irq(irq);
274 }
275#else
276 disabled = 0;
277
278#endif
279 }
280
281 return;
282 }
283 }
284 if (mer && ccleirq > 0 && !aliased_irq) {
285 pr_warn("ISA interrupt from unknown source? EIRQ_REG = %x\n",
286 mer);
287 ccleirq--;
288 }
289 }
290 iirq:
291 mir = master_inb(IIRQ_REG);
292
293 if (mir & Q40_IRQ_KEYB_MASK)
294 do_IRQ(Q40_IRQ_KEYBOARD, fp);
295
296 return;
297}
298
299void q40_irq_enable(struct irq_data *data)
300{
301 unsigned int irq = data->irq;
302
303 if (irq >= 5 && irq <= 15) {
304 mext_disabled--;
305 if (mext_disabled > 0)
306 pr_warn("q40_irq_enable : nested disable/enable\n");
307 if (mext_disabled == 0)
308 master_outb(1, EXT_ENABLE_REG);
309 }
310}
311
312
313void q40_irq_disable(struct irq_data *data)
314{
315 unsigned int irq = data->irq;
316
317
318
319
320
321
322 if (irq >= 5 && irq <= 15) {
323 master_outb(0, EXT_ENABLE_REG);
324 mext_disabled++;
325 if (mext_disabled > 1)
326 pr_info("disable_irq nesting count %d\n",
327 mext_disabled);
328 }
329}
330