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13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/war.h>
20
21
22
23
24
25#ifndef __STR
26#define __STR(x) #x
27#endif
28#ifndef STR
29#define STR(x) __STR(x)
30#endif
31
32
33
34
35#ifdef __ASSEMBLY__
36#define _ULCAST_
37#define _U64CAST_
38#else
39#define _ULCAST_ (unsigned long)
40#define _U64CAST_ (u64)
41#endif
42
43
44
45
46#define CP0_INDEX $0
47#define CP0_RANDOM $1
48#define CP0_ENTRYLO0 $2
49#define CP0_ENTRYLO1 $3
50#define CP0_CONF $3
51#define CP0_GLOBALNUMBER $3, 1
52#define CP0_CONTEXT $4
53#define CP0_PAGEMASK $5
54#define CP0_SEGCTL0 $5, 2
55#define CP0_SEGCTL1 $5, 3
56#define CP0_SEGCTL2 $5, 4
57#define CP0_WIRED $6
58#define CP0_INFO $7
59#define CP0_HWRENA $7
60#define CP0_BADVADDR $8
61#define CP0_BADINSTR $8, 1
62#define CP0_COUNT $9
63#define CP0_ENTRYHI $10
64#define CP0_GUESTCTL1 $10, 4
65#define CP0_GUESTCTL2 $10, 5
66#define CP0_GUESTCTL3 $10, 6
67#define CP0_COMPARE $11
68#define CP0_GUESTCTL0EXT $11, 4
69#define CP0_STATUS $12
70#define CP0_GUESTCTL0 $12, 6
71#define CP0_GTOFFSET $12, 7
72#define CP0_CAUSE $13
73#define CP0_EPC $14
74#define CP0_PRID $15
75#define CP0_EBASE $15, 1
76#define CP0_CMGCRBASE $15, 3
77#define CP0_CONFIG $16
78#define CP0_CONFIG3 $16, 3
79#define CP0_CONFIG5 $16, 5
80#define CP0_LLADDR $17
81#define CP0_WATCHLO $18
82#define CP0_WATCHHI $19
83#define CP0_XCONTEXT $20
84#define CP0_FRAMEMASK $21
85#define CP0_DIAGNOSTIC $22
86#define CP0_DEBUG $23
87#define CP0_DEPC $24
88#define CP0_PERFORMANCE $25
89#define CP0_ECC $26
90#define CP0_CACHEERR $27
91#define CP0_TAGLO $28
92#define CP0_TAGHI $29
93#define CP0_ERROREPC $30
94#define CP0_DESAVE $31
95
96
97
98
99
100
101
102#define CP0_IBASE $0
103#define CP0_IBOUND $1
104#define CP0_DBASE $2
105#define CP0_DBOUND $3
106#define CP0_CALG $17
107#define CP0_IWATCH $18
108#define CP0_DWATCH $19
109
110
111
112
113#define CP0_S1_DERRADDR0 $26
114#define CP0_S1_DERRADDR1 $27
115#define CP0_S1_INTCONTROL $20
116
117
118
119
120#define CP0_S2_SRSCTL $12
121
122
123
124
125#define CP0_S3_SRSMAP $12
126
127
128
129
130#define CP0_TX39_CACHE $7
131
132
133
134#define ENTRYLO_G (_ULCAST_(1) << 0)
135#define ENTRYLO_V (_ULCAST_(1) << 1)
136#define ENTRYLO_D (_ULCAST_(1) << 2)
137#define ENTRYLO_C_SHIFT 3
138#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
139
140
141#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
142#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
143#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
144#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
145
146
147#define MIPS_ENTRYLO_PFN_SHIFT 6
148#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
149#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
150
151
152
153
154#define MIPS_GLOBALNUMBER_VP_SHF 0
155#define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
156#define MIPS_GLOBALNUMBER_CORE_SHF 8
157#define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
158#define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
159#define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
160
161
162
163
164#ifdef CONFIG_CPU_VR41XX
165
166
167
168#define PM_1K 0x00000000
169#define PM_4K 0x00001800
170#define PM_16K 0x00007800
171#define PM_64K 0x0001f800
172#define PM_256K 0x0007f800
173
174#else
175
176#define PM_4K 0x00000000
177#define PM_8K 0x00002000
178#define PM_16K 0x00006000
179#define PM_32K 0x0000e000
180#define PM_64K 0x0001e000
181#define PM_128K 0x0003e000
182#define PM_256K 0x0007e000
183#define PM_512K 0x000fe000
184#define PM_1M 0x001fe000
185#define PM_2M 0x003fe000
186#define PM_4M 0x007fe000
187#define PM_8M 0x00ffe000
188#define PM_16M 0x01ffe000
189#define PM_32M 0x03ffe000
190#define PM_64M 0x07ffe000
191#define PM_256M 0x1fffe000
192#define PM_1G 0x7fffe000
193
194#endif
195
196
197
198
199#ifdef CONFIG_PAGE_SIZE_4KB
200#define PM_DEFAULT_MASK PM_4K
201#elif defined(CONFIG_PAGE_SIZE_8KB)
202#define PM_DEFAULT_MASK PM_8K
203#elif defined(CONFIG_PAGE_SIZE_16KB)
204#define PM_DEFAULT_MASK PM_16K
205#elif defined(CONFIG_PAGE_SIZE_32KB)
206#define PM_DEFAULT_MASK PM_32K
207#elif defined(CONFIG_PAGE_SIZE_64KB)
208#define PM_DEFAULT_MASK PM_64K
209#else
210#error Bad page size configuration!
211#endif
212
213
214
215
216#ifdef CONFIG_PAGE_SIZE_4KB
217#define PM_HUGE_MASK PM_1M
218#elif defined(CONFIG_PAGE_SIZE_8KB)
219#define PM_HUGE_MASK PM_4M
220#elif defined(CONFIG_PAGE_SIZE_16KB)
221#define PM_HUGE_MASK PM_16M
222#elif defined(CONFIG_PAGE_SIZE_32KB)
223#define PM_HUGE_MASK PM_64M
224#elif defined(CONFIG_PAGE_SIZE_64KB)
225#define PM_HUGE_MASK PM_256M
226#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
227#error Bad page size configuration for hugetlbfs!
228#endif
229
230
231
232
233#define MIPSR6_WIRED_LIMIT_SHIFT 16
234#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
235#define MIPSR6_WIRED_WIRED_SHIFT 0
236#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
237
238
239
240
241#define PL_4K 12
242#define PL_16K 14
243#define PL_64K 16
244#define PL_256K 18
245#define PL_1M 20
246#define PL_4M 22
247#define PL_16M 24
248#define PL_64M 26
249#define PL_256M 28
250
251
252
253
254#define PG_RIE (_ULCAST_(1) << 31)
255#define PG_XIE (_ULCAST_(1) << 30)
256#define PG_ELPA (_ULCAST_(1) << 29)
257#define PG_ESP (_ULCAST_(1) << 28)
258#define PG_IEC (_ULCAST_(1) << 27)
259
260
261#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
262#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
263#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
264
265
266
267
268#define IE_SW0 (_ULCAST_(1) << 8)
269#define IE_SW1 (_ULCAST_(1) << 9)
270#define IE_IRQ0 (_ULCAST_(1) << 10)
271#define IE_IRQ1 (_ULCAST_(1) << 11)
272#define IE_IRQ2 (_ULCAST_(1) << 12)
273#define IE_IRQ3 (_ULCAST_(1) << 13)
274#define IE_IRQ4 (_ULCAST_(1) << 14)
275#define IE_IRQ5 (_ULCAST_(1) << 15)
276
277
278
279
280#define C_SW0 (_ULCAST_(1) << 8)
281#define C_SW1 (_ULCAST_(1) << 9)
282#define C_IRQ0 (_ULCAST_(1) << 10)
283#define C_IRQ1 (_ULCAST_(1) << 11)
284#define C_IRQ2 (_ULCAST_(1) << 12)
285#define C_IRQ3 (_ULCAST_(1) << 13)
286#define C_IRQ4 (_ULCAST_(1) << 14)
287#define C_IRQ5 (_ULCAST_(1) << 15)
288
289
290
291
292#define ST0_IE 0x00000001
293#define ST0_EXL 0x00000002
294#define ST0_ERL 0x00000004
295#define ST0_KSU 0x00000018
296# define KSU_USER 0x00000010
297# define KSU_SUPERVISOR 0x00000008
298# define KSU_KERNEL 0x00000000
299#define ST0_UX 0x00000020
300#define ST0_SX 0x00000040
301#define ST0_KX 0x00000080
302#define ST0_DE 0x00010000
303#define ST0_CE 0x00020000
304
305
306
307
308
309
310#define ST0_CO 0x08000000
311
312
313
314
315#define ST0_IEC 0x00000001
316#define ST0_KUC 0x00000002
317#define ST0_IEP 0x00000004
318#define ST0_KUP 0x00000008
319#define ST0_IEO 0x00000010
320#define ST0_KUO 0x00000020
321
322#define ST0_ISC 0x00010000
323#define ST0_SWC 0x00020000
324#define ST0_CM 0x00080000
325
326
327
328
329#define ST0_UM (_ULCAST_(1) << 4)
330#define ST0_IL (_ULCAST_(1) << 23)
331#define ST0_DL (_ULCAST_(1) << 24)
332
333
334
335
336#define ST0_MX 0x01000000
337
338
339
340
341#define ST0_IM 0x0000ff00
342#define STATUSB_IP0 8
343#define STATUSF_IP0 (_ULCAST_(1) << 8)
344#define STATUSB_IP1 9
345#define STATUSF_IP1 (_ULCAST_(1) << 9)
346#define STATUSB_IP2 10
347#define STATUSF_IP2 (_ULCAST_(1) << 10)
348#define STATUSB_IP3 11
349#define STATUSF_IP3 (_ULCAST_(1) << 11)
350#define STATUSB_IP4 12
351#define STATUSF_IP4 (_ULCAST_(1) << 12)
352#define STATUSB_IP5 13
353#define STATUSF_IP5 (_ULCAST_(1) << 13)
354#define STATUSB_IP6 14
355#define STATUSF_IP6 (_ULCAST_(1) << 14)
356#define STATUSB_IP7 15
357#define STATUSF_IP7 (_ULCAST_(1) << 15)
358#define STATUSB_IP8 0
359#define STATUSF_IP8 (_ULCAST_(1) << 0)
360#define STATUSB_IP9 1
361#define STATUSF_IP9 (_ULCAST_(1) << 1)
362#define STATUSB_IP10 2
363#define STATUSF_IP10 (_ULCAST_(1) << 2)
364#define STATUSB_IP11 3
365#define STATUSF_IP11 (_ULCAST_(1) << 3)
366#define STATUSB_IP12 4
367#define STATUSF_IP12 (_ULCAST_(1) << 4)
368#define STATUSB_IP13 5
369#define STATUSF_IP13 (_ULCAST_(1) << 5)
370#define STATUSB_IP14 6
371#define STATUSF_IP14 (_ULCAST_(1) << 6)
372#define STATUSB_IP15 7
373#define STATUSF_IP15 (_ULCAST_(1) << 7)
374#define ST0_CH 0x00040000
375#define ST0_NMI 0x00080000
376#define ST0_SR 0x00100000
377#define ST0_TS 0x00200000
378#define ST0_BEV 0x00400000
379#define ST0_RE 0x02000000
380#define ST0_FR 0x04000000
381#define ST0_CU 0xf0000000
382#define ST0_CU0 0x10000000
383#define ST0_CU1 0x20000000
384#define ST0_CU2 0x40000000
385#define ST0_CU3 0x80000000
386#define ST0_XX 0x80000000
387
388
389
390
391#define INTCTLB_IPFDC 23
392#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
393#define INTCTLB_IPPCI 26
394#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
395#define INTCTLB_IPTI 29
396#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
397
398
399
400
401
402
403#define CAUSEB_EXCCODE 2
404#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
405#define CAUSEB_IP 8
406#define CAUSEF_IP (_ULCAST_(255) << 8)
407#define CAUSEB_IP0 8
408#define CAUSEF_IP0 (_ULCAST_(1) << 8)
409#define CAUSEB_IP1 9
410#define CAUSEF_IP1 (_ULCAST_(1) << 9)
411#define CAUSEB_IP2 10
412#define CAUSEF_IP2 (_ULCAST_(1) << 10)
413#define CAUSEB_IP3 11
414#define CAUSEF_IP3 (_ULCAST_(1) << 11)
415#define CAUSEB_IP4 12
416#define CAUSEF_IP4 (_ULCAST_(1) << 12)
417#define CAUSEB_IP5 13
418#define CAUSEF_IP5 (_ULCAST_(1) << 13)
419#define CAUSEB_IP6 14
420#define CAUSEF_IP6 (_ULCAST_(1) << 14)
421#define CAUSEB_IP7 15
422#define CAUSEF_IP7 (_ULCAST_(1) << 15)
423#define CAUSEB_FDCI 21
424#define CAUSEF_FDCI (_ULCAST_(1) << 21)
425#define CAUSEB_WP 22
426#define CAUSEF_WP (_ULCAST_(1) << 22)
427#define CAUSEB_IV 23
428#define CAUSEF_IV (_ULCAST_(1) << 23)
429#define CAUSEB_PCI 26
430#define CAUSEF_PCI (_ULCAST_(1) << 26)
431#define CAUSEB_DC 27
432#define CAUSEF_DC (_ULCAST_(1) << 27)
433#define CAUSEB_CE 28
434#define CAUSEF_CE (_ULCAST_(3) << 28)
435#define CAUSEB_TI 30
436#define CAUSEF_TI (_ULCAST_(1) << 30)
437#define CAUSEB_BD 31
438#define CAUSEF_BD (_ULCAST_(1) << 31)
439
440
441
442
443#define EXCCODE_INT 0
444#define EXCCODE_MOD 1
445#define EXCCODE_TLBL 2
446#define EXCCODE_TLBS 3
447#define EXCCODE_ADEL 4
448#define EXCCODE_ADES 5
449#define EXCCODE_IBE 6
450#define EXCCODE_DBE 7
451#define EXCCODE_SYS 8
452#define EXCCODE_BP 9
453#define EXCCODE_RI 10
454#define EXCCODE_CPU 11
455#define EXCCODE_OV 12
456#define EXCCODE_TR 13
457#define EXCCODE_MSAFPE 14
458#define EXCCODE_FPE 15
459#define EXCCODE_TLBRI 19
460#define EXCCODE_TLBXI 20
461#define EXCCODE_MSADIS 21
462#define EXCCODE_MDMX 22
463#define EXCCODE_WATCH 23
464#define EXCCODE_MCHECK 24
465#define EXCCODE_THREAD 25
466#define EXCCODE_DSPDIS 26
467#define EXCCODE_GE 27
468
469
470#define MIPS_EXCCODE_TLBPAR 16
471
472
473
474
475
476#define CONF_CM_CACHABLE_NO_WA 0
477#define CONF_CM_CACHABLE_WA 1
478#define CONF_CM_UNCACHED 2
479#define CONF_CM_CACHABLE_NONCOHERENT 3
480#define CONF_CM_CACHABLE_CE 4
481#define CONF_CM_CACHABLE_COW 5
482#define CONF_CM_CACHABLE_CUW 6
483#define CONF_CM_CACHABLE_ACCELERATED 7
484#define CONF_CM_CMASK 7
485#define CONF_BE (_ULCAST_(1) << 15)
486
487
488#define CONF_CU (_ULCAST_(1) << 3)
489#define CONF_DB (_ULCAST_(1) << 4)
490#define CONF_IB (_ULCAST_(1) << 5)
491#define CONF_DC (_ULCAST_(7) << 6)
492#define CONF_IC (_ULCAST_(7) << 9)
493#define CONF_EB (_ULCAST_(1) << 13)
494#define CONF_EM (_ULCAST_(1) << 14)
495#define CONF_SM (_ULCAST_(1) << 16)
496#define CONF_SC (_ULCAST_(1) << 17)
497#define CONF_EW (_ULCAST_(3) << 18)
498#define CONF_EP (_ULCAST_(15)<< 24)
499#define CONF_EC (_ULCAST_(7) << 28)
500#define CONF_CM (_ULCAST_(1) << 31)
501
502
503#define R4K_CONF_SW (_ULCAST_(1) << 20)
504#define R4K_CONF_SS (_ULCAST_(1) << 21)
505#define R4K_CONF_SB (_ULCAST_(3) << 22)
506
507
508#define R5K_CONF_SE (_ULCAST_(1) << 12)
509#define R5K_CONF_SS (_ULCAST_(3) << 20)
510
511
512#define RM7K_CONF_SE (_ULCAST_(1) << 3)
513#define RM7K_CONF_TE (_ULCAST_(1) << 12)
514#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
515#define RM7K_CONF_TC (_ULCAST_(1) << 17)
516#define RM7K_CONF_SI (_ULCAST_(3) << 20)
517#define RM7K_CONF_SC (_ULCAST_(1) << 31)
518
519
520#define R10K_CONF_DN (_ULCAST_(3) << 3)
521#define R10K_CONF_CT (_ULCAST_(1) << 5)
522#define R10K_CONF_PE (_ULCAST_(1) << 6)
523#define R10K_CONF_PM (_ULCAST_(3) << 7)
524#define R10K_CONF_EC (_ULCAST_(15)<< 9)
525#define R10K_CONF_SB (_ULCAST_(1) << 13)
526#define R10K_CONF_SK (_ULCAST_(1) << 14)
527#define R10K_CONF_SS (_ULCAST_(7) << 16)
528#define R10K_CONF_SC (_ULCAST_(7) << 19)
529#define R10K_CONF_DC (_ULCAST_(7) << 26)
530#define R10K_CONF_IC (_ULCAST_(7) << 29)
531
532
533#define VR41_CONF_CS (_ULCAST_(1) << 12)
534#define VR41_CONF_P4K (_ULCAST_(1) << 13)
535#define VR41_CONF_BP (_ULCAST_(1) << 16)
536#define VR41_CONF_M16 (_ULCAST_(1) << 20)
537#define VR41_CONF_AD (_ULCAST_(1) << 23)
538
539
540#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
541#define R30XX_CONF_REV (_ULCAST_(1) << 22)
542#define R30XX_CONF_AC (_ULCAST_(1) << 23)
543#define R30XX_CONF_RF (_ULCAST_(1) << 24)
544#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
545#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
546#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
547#define R30XX_CONF_SB (_ULCAST_(1) << 30)
548#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
549
550
551#define TX49_CONF_DC (_ULCAST_(1) << 16)
552#define TX49_CONF_IC (_ULCAST_(1) << 17)
553#define TX49_CONF_HALT (_ULCAST_(1) << 18)
554#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
555
556
557#define MIPS_CONF_VI (_ULCAST_(1) << 3)
558#define MIPS_CONF_MT (_ULCAST_(7) << 7)
559#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
560#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
561#define MIPS_CONF_AR (_ULCAST_(7) << 10)
562#define MIPS_CONF_AT (_ULCAST_(3) << 13)
563#define MIPS_CONF_M (_ULCAST_(1) << 31)
564
565
566
567
568#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
569#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
570#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
571#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
572#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
573#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
574#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
575#define MIPS_CONF1_DA_SHF 7
576#define MIPS_CONF1_DA_SZ 3
577#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
578#define MIPS_CONF1_DL_SHF 10
579#define MIPS_CONF1_DL_SZ 3
580#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
581#define MIPS_CONF1_DS_SHF 13
582#define MIPS_CONF1_DS_SZ 3
583#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
584#define MIPS_CONF1_IA_SHF 16
585#define MIPS_CONF1_IA_SZ 3
586#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
587#define MIPS_CONF1_IL_SHF 19
588#define MIPS_CONF1_IL_SZ 3
589#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
590#define MIPS_CONF1_IS_SHF 22
591#define MIPS_CONF1_IS_SZ 3
592#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
593#define MIPS_CONF1_TLBS_SHIFT (25)
594#define MIPS_CONF1_TLBS_SIZE (6)
595#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
596
597#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
598#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
599#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
600#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
601#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
602#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
603#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
604#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
605
606#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
607#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
608#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
609#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
610#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
611#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
612#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
613#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
614#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
615#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
616#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
617#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
618#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
619#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
620#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
621#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
622#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
623#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
624#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
625#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
626#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
627#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
628#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
629#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
630#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
631#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
632#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
633
634#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
635#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
636#define MIPS_CONF4_FTLBSETS_SHIFT (0)
637#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
638#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
639#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
640#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
641
642#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
643
644#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
645#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
646#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
647#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
648#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
649#define MIPS_CONF4_KSCREXIST_SHIFT (16)
650#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
651#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
652#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
653#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
654#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
655#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
656
657#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
658#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
659#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
660#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
661#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
662#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
663#define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
664#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
665#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
666#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
667#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
668#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
669#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
670#define MIPS_CONF5_K (_ULCAST_(1) << 30)
671
672#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
673
674#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
675
676#define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
677
678#define MIPS_CONF6_FTLBP_SHIFT (16)
679
680#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
681
682#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
683
684#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
685#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
686
687
688#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
689
690
691#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
692#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
693#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
694#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
695#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
696#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
697#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
698#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
699#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
700#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
701#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
702#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
703#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
704
705
706#define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
707#define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
708#define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
709#define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
710#define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
711#define MIPS_PERFCTRL_EVENT_S 5
712#define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
713#define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
714#define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
715#define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
716#define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
717#define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
718#define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
719#define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
720#define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
721
722
723#define MIPS_PERFCTRL_VPEID_S 16
724#define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
725#define MIPS_PERFCTRL_TCID_S 22
726#define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
727#define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
728#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
729#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
730#define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
731
732
733#define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
734
735
736#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
737
738
739#define MIPS_MAAR_VH (_U64CAST_(1) << 63)
740#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
741#define MIPS_MAAR_ADDR_SHIFT 12
742#define MIPS_MAAR_S (_ULCAST_(1) << 1)
743#define MIPS_MAAR_VL (_ULCAST_(1) << 0)
744
745
746#define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
747
748
749#define MIPS_EBASE_CPUNUM_SHIFT 0
750#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
751#define MIPS_EBASE_WG_SHIFT 11
752#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
753#define MIPS_EBASE_BASE_SHIFT 12
754#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
755
756
757#define MIPS_CMGCRB_BASE 11
758#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
759
760
761#define MIPS_LLADDR_LLB_SHIFT 0
762#define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
763
764
765
766
767#define MIPS_SEGCFG_PA_SHIFT 9
768#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
769#define MIPS_SEGCFG_AM_SHIFT 4
770#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
771#define MIPS_SEGCFG_EU_SHIFT 3
772#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
773#define MIPS_SEGCFG_C_SHIFT 0
774#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
775
776#define MIPS_SEGCFG_UUSK _ULCAST_(7)
777#define MIPS_SEGCFG_USK _ULCAST_(5)
778#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
779#define MIPS_SEGCFG_MUSK _ULCAST_(3)
780#define MIPS_SEGCFG_MSK _ULCAST_(2)
781#define MIPS_SEGCFG_MK _ULCAST_(1)
782#define MIPS_SEGCFG_UK _ULCAST_(0)
783
784#define MIPS_PWFIELD_GDI_SHIFT 24
785#define MIPS_PWFIELD_GDI_MASK 0x3f000000
786#define MIPS_PWFIELD_UDI_SHIFT 18
787#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
788#define MIPS_PWFIELD_MDI_SHIFT 12
789#define MIPS_PWFIELD_MDI_MASK 0x0003f000
790#define MIPS_PWFIELD_PTI_SHIFT 6
791#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
792#define MIPS_PWFIELD_PTEI_SHIFT 0
793#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
794
795#define MIPS_PWSIZE_PS_SHIFT 30
796#define MIPS_PWSIZE_PS_MASK 0x40000000
797#define MIPS_PWSIZE_GDW_SHIFT 24
798#define MIPS_PWSIZE_GDW_MASK 0x3f000000
799#define MIPS_PWSIZE_UDW_SHIFT 18
800#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
801#define MIPS_PWSIZE_MDW_SHIFT 12
802#define MIPS_PWSIZE_MDW_MASK 0x0003f000
803#define MIPS_PWSIZE_PTW_SHIFT 6
804#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
805#define MIPS_PWSIZE_PTEW_SHIFT 0
806#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
807
808#define MIPS_PWCTL_PWEN_SHIFT 31
809#define MIPS_PWCTL_PWEN_MASK 0x80000000
810#define MIPS_PWCTL_XK_SHIFT 28
811#define MIPS_PWCTL_XK_MASK 0x10000000
812#define MIPS_PWCTL_XS_SHIFT 27
813#define MIPS_PWCTL_XS_MASK 0x08000000
814#define MIPS_PWCTL_XU_SHIFT 26
815#define MIPS_PWCTL_XU_MASK 0x04000000
816#define MIPS_PWCTL_DPH_SHIFT 7
817#define MIPS_PWCTL_DPH_MASK 0x00000080
818#define MIPS_PWCTL_HUGEPG_SHIFT 6
819#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
820#define MIPS_PWCTL_PSN_SHIFT 0
821#define MIPS_PWCTL_PSN_MASK 0x0000003f
822
823
824#define MIPS_GCTL0_GM_SHIFT 31
825#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
826#define MIPS_GCTL0_RI_SHIFT 30
827#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
828#define MIPS_GCTL0_MC_SHIFT 29
829#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
830#define MIPS_GCTL0_CP0_SHIFT 28
831#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
832#define MIPS_GCTL0_AT_SHIFT 26
833#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
834#define MIPS_GCTL0_GT_SHIFT 25
835#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
836#define MIPS_GCTL0_CG_SHIFT 24
837#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
838#define MIPS_GCTL0_CF_SHIFT 23
839#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
840#define MIPS_GCTL0_G1_SHIFT 22
841#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
842#define MIPS_GCTL0_G0E_SHIFT 19
843#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
844#define MIPS_GCTL0_PT_SHIFT 18
845#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
846#define MIPS_GCTL0_RAD_SHIFT 9
847#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
848#define MIPS_GCTL0_DRG_SHIFT 8
849#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
850#define MIPS_GCTL0_G2_SHIFT 7
851#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
852#define MIPS_GCTL0_GEXC_SHIFT 2
853#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
854#define MIPS_GCTL0_SFC2_SHIFT 1
855#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
856#define MIPS_GCTL0_SFC1_SHIFT 0
857#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
858
859
860#define MIPS_GCTL0_AT_ROOT 1
861#define MIPS_GCTL0_AT_GUEST 3
862
863
864#define MIPS_GCTL0_GEXC_GPSI 0
865#define MIPS_GCTL0_GEXC_GSFC 1
866#define MIPS_GCTL0_GEXC_HC 2
867#define MIPS_GCTL0_GEXC_GRR 3
868#define MIPS_GCTL0_GEXC_GVA 8
869#define MIPS_GCTL0_GEXC_GHFC 9
870#define MIPS_GCTL0_GEXC_GPA 10
871
872
873#define MIPS_GCTL0EXT_RPW_SHIFT 8
874#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
875#define MIPS_GCTL0EXT_NCC_SHIFT 6
876#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
877#define MIPS_GCTL0EXT_CGI_SHIFT 4
878#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
879#define MIPS_GCTL0EXT_FCD_SHIFT 3
880#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
881#define MIPS_GCTL0EXT_OG_SHIFT 2
882#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
883#define MIPS_GCTL0EXT_BG_SHIFT 1
884#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
885#define MIPS_GCTL0EXT_MG_SHIFT 0
886#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
887
888
889#define MIPS_GCTL0EXT_RPW_BOTH 0
890#define MIPS_GCTL0EXT_RPW_GPA 2
891#define MIPS_GCTL0EXT_RPW_RVA 3
892
893
894#define MIPS_GCTL0EXT_NCC_IND 0
895#define MIPS_GCTL0EXT_NCC_MOD 1
896
897
898#define MIPS_GCTL1_ID_SHIFT 0
899#define MIPS_GCTL1_ID_WIDTH 8
900#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
901#define MIPS_GCTL1_RID_SHIFT 16
902#define MIPS_GCTL1_RID_WIDTH 8
903#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
904#define MIPS_GCTL1_EID_SHIFT 24
905#define MIPS_GCTL1_EID_WIDTH 8
906#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
907
908
909#define MIPS_GCTL1_ROOT_GUESTID 0
910
911
912#define MIPS_CDMMBASE_SIZE_SHIFT 0
913#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
914#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
915#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
916#define MIPS_CDMMBASE_ADDR_SHIFT 11
917#define MIPS_CDMMBASE_ADDR_START 15
918
919
920#define MIPS_HWR_CPUNUM 0
921#define MIPS_HWR_SYNCISTEP 1
922#define MIPS_HWR_CC 2
923#define MIPS_HWR_CCRES 3
924#define MIPS_HWR_ULR 29
925#define MIPS_HWR_IMPL1 30
926#define MIPS_HWR_IMPL2 31
927
928
929#define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
930#define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
931#define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
932#define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
933#define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
934#define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
935#define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
936
937
938
939
940#define TX39_CONF_ICS_SHIFT 19
941#define TX39_CONF_ICS_MASK 0x00380000
942#define TX39_CONF_ICS_1KB 0x00000000
943#define TX39_CONF_ICS_2KB 0x00080000
944#define TX39_CONF_ICS_4KB 0x00100000
945#define TX39_CONF_ICS_8KB 0x00180000
946#define TX39_CONF_ICS_16KB 0x00200000
947
948#define TX39_CONF_DCS_SHIFT 16
949#define TX39_CONF_DCS_MASK 0x00070000
950#define TX39_CONF_DCS_1KB 0x00000000
951#define TX39_CONF_DCS_2KB 0x00010000
952#define TX39_CONF_DCS_4KB 0x00020000
953#define TX39_CONF_DCS_8KB 0x00030000
954#define TX39_CONF_DCS_16KB 0x00040000
955
956#define TX39_CONF_CWFON 0x00004000
957#define TX39_CONF_WBON 0x00002000
958#define TX39_CONF_RF_SHIFT 10
959#define TX39_CONF_RF_MASK 0x00000c00
960#define TX39_CONF_DOZE 0x00000200
961#define TX39_CONF_HALT 0x00000100
962#define TX39_CONF_LOCK 0x00000080
963#define TX39_CONF_ICE 0x00000020
964#define TX39_CONF_DCE 0x00000010
965#define TX39_CONF_IRSIZE_SHIFT 2
966#define TX39_CONF_IRSIZE_MASK 0x0000000c
967#define TX39_CONF_DRSIZE_SHIFT 0
968#define TX39_CONF_DRSIZE_MASK 0x00000003
969
970
971
972
973
974#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
975
976#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
977
978#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
979
980
981#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
982
983#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
984
985#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
986
987#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
988
989
990#define CVMCTL_IPPCI_SHIFT 7
991#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
992#define CVMCTL_IPTI_SHIFT 4
993#define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
994
995
996#define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
997
998
999#define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
1000#define CVMVMCONF_MMUSIZEM1_S 12
1001#define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1002#define CVMVMCONF_RMMUSIZEM1_S 0
1003#define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1004
1005
1006
1007
1008#define CP1_REVISION $0
1009#define CP1_UFR $1
1010#define CP1_UNFR $4
1011#define CP1_FCCR $25
1012#define CP1_FEXR $26
1013#define CP1_FENR $28
1014#define CP1_STATUS $31
1015
1016
1017
1018
1019
1020#define MIPS_FPIR_S (_ULCAST_(1) << 16)
1021#define MIPS_FPIR_D (_ULCAST_(1) << 17)
1022#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1023#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1024#define MIPS_FPIR_W (_ULCAST_(1) << 20)
1025#define MIPS_FPIR_L (_ULCAST_(1) << 21)
1026#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1027#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1028#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1029#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1030
1031
1032
1033
1034#define MIPS_FCCR_CONDX_S 0
1035#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1036#define MIPS_FCCR_COND0_S 0
1037#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1038#define MIPS_FCCR_COND1_S 1
1039#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1040#define MIPS_FCCR_COND2_S 2
1041#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1042#define MIPS_FCCR_COND3_S 3
1043#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1044#define MIPS_FCCR_COND4_S 4
1045#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1046#define MIPS_FCCR_COND5_S 5
1047#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1048#define MIPS_FCCR_COND6_S 6
1049#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1050#define MIPS_FCCR_COND7_S 7
1051#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1052
1053
1054
1055
1056#define MIPS_FENR_FS_S 2
1057#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1058
1059
1060
1061
1062#define FPU_CSR_COND_S 23
1063#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1064
1065#define FPU_CSR_FS_S 24
1066#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1067
1068#define FPU_CSR_CONDX_S 25
1069#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1070#define FPU_CSR_COND1_S 25
1071#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1072#define FPU_CSR_COND2_S 26
1073#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1074#define FPU_CSR_COND3_S 27
1075#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1076#define FPU_CSR_COND4_S 28
1077#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1078#define FPU_CSR_COND5_S 29
1079#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1080#define FPU_CSR_COND6_S 30
1081#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1082#define FPU_CSR_COND7_S 31
1083#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1084
1085
1086
1087
1088
1089#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1090
1091#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1092#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1093
1094
1095
1096
1097
1098
1099#define FPU_CSR_ALL_X 0x0003f000
1100#define FPU_CSR_UNI_X 0x00020000
1101#define FPU_CSR_INV_X 0x00010000
1102#define FPU_CSR_DIV_X 0x00008000
1103#define FPU_CSR_OVF_X 0x00004000
1104#define FPU_CSR_UDF_X 0x00002000
1105#define FPU_CSR_INE_X 0x00001000
1106
1107#define FPU_CSR_ALL_E 0x00000f80
1108#define FPU_CSR_INV_E 0x00000800
1109#define FPU_CSR_DIV_E 0x00000400
1110#define FPU_CSR_OVF_E 0x00000200
1111#define FPU_CSR_UDF_E 0x00000100
1112#define FPU_CSR_INE_E 0x00000080
1113
1114#define FPU_CSR_ALL_S 0x0000007c
1115#define FPU_CSR_INV_S 0x00000040
1116#define FPU_CSR_DIV_S 0x00000020
1117#define FPU_CSR_OVF_S 0x00000010
1118#define FPU_CSR_UDF_S 0x00000008
1119#define FPU_CSR_INE_S 0x00000004
1120
1121
1122#define FPU_CSR_RM 0x00000003
1123#define FPU_CSR_RN 0x0
1124#define FPU_CSR_RZ 0x1
1125#define FPU_CSR_RU 0x2
1126#define FPU_CSR_RD 0x3
1127
1128
1129#ifndef __ASSEMBLY__
1130
1131
1132
1133
1134#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1135 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1136#define get_isa16_mode(x) ((x) & 0x1)
1137#define msk_isa16_mode(x) ((x) & ~0x1)
1138#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1139#else
1140#define get_isa16_mode(x) 0
1141#define msk_isa16_mode(x) (x)
1142#define set_isa16_mode(x) do { } while(0)
1143#endif
1144
1145
1146
1147
1148
1149static inline int mm_insn_16bit(u16 insn)
1150{
1151 u16 opcode = (insn >> 10) & 0x7;
1152
1153 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1154}
1155
1156
1157
1158
1159#ifdef CONFIG_CPU_MICROMIPS
1160#define _ASM_INSN16_IF_MM(_enc) \
1161 ".insn\n\t" \
1162 ".hword (" #_enc ")\n\t"
1163#define _ASM_INSN32_IF_MM(_enc) \
1164 ".insn\n\t" \
1165 ".hword ((" #_enc ") >> 16)\n\t" \
1166 ".hword ((" #_enc ") & 0xffff)\n\t"
1167#else
1168#define _ASM_INSN_IF_MIPS(_enc) \
1169 ".insn\n\t" \
1170 ".word (" #_enc ")\n\t"
1171#endif
1172
1173#ifndef _ASM_INSN16_IF_MM
1174#define _ASM_INSN16_IF_MM(_enc)
1175#endif
1176#ifndef _ASM_INSN32_IF_MM
1177#define _ASM_INSN32_IF_MM(_enc)
1178#endif
1179#ifndef _ASM_INSN_IF_MIPS
1180#define _ASM_INSN_IF_MIPS(_enc)
1181#endif
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205#define _IFC_REG(n) \
1206 ".ifc \\r, $" #n "\n\t" \
1207 "\\var = " #n "\n\t" \
1208 ".endif\n\t"
1209
1210__asm__(".macro parse_r var r\n\t"
1211 "\\var = -1\n\t"
1212 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
1213 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
1214 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
1215 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1216 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1217 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1218 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1219 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1220 ".iflt \\var\n\t"
1221 ".error \"Unable to parse register name \\r\"\n\t"
1222 ".endif\n\t"
1223 ".endm");
1224
1225#undef _IFC_REG
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236#define _ASM_MACRO_0(OP, ENC) \
1237 __asm__(".macro " #OP "\n\t" \
1238 ENC \
1239 ".endm")
1240
1241
1242#define _ASM_MACRO_2R(OP, R1, R2, ENC) \
1243 __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
1244 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1245 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1246 ENC \
1247 ".endm")
1248
1249
1250#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
1251 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1252 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1253 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1254 "parse_r __" #R3 ", \\" #R3 "\n\t" \
1255 ENC \
1256 ".endm")
1257
1258
1259#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
1260 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1261 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1262 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1263 ENC \
1264 ".endm")
1265
1266
1267
1268
1269static inline void tlbinvf(void)
1270{
1271 __asm__ __volatile__(
1272 ".set push\n\t"
1273 ".set noreorder\n\t"
1274 "# tlbinvf\n\t"
1275 _ASM_INSN_IF_MIPS(0x42000004)
1276 _ASM_INSN32_IF_MM(0x0000537c)
1277 ".set pop");
1278}
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288#define read_r10k_perf_cntr(counter) \
1289({ \
1290 unsigned int __res; \
1291 __asm__ __volatile__( \
1292 "mfpc\t%0, %1" \
1293 : "=r" (__res) \
1294 : "i" (counter)); \
1295 \
1296 __res; \
1297})
1298
1299#define write_r10k_perf_cntr(counter,val) \
1300do { \
1301 __asm__ __volatile__( \
1302 "mtpc\t%0, %1" \
1303 : \
1304 : "r" (val), "i" (counter)); \
1305} while (0)
1306
1307#define read_r10k_perf_event(counter) \
1308({ \
1309 unsigned int __res; \
1310 __asm__ __volatile__( \
1311 "mfps\t%0, %1" \
1312 : "=r" (__res) \
1313 : "i" (counter)); \
1314 \
1315 __res; \
1316})
1317
1318#define write_r10k_perf_cntl(counter,val) \
1319do { \
1320 __asm__ __volatile__( \
1321 "mtps\t%0, %1" \
1322 : \
1323 : "r" (val), "i" (counter)); \
1324} while (0)
1325
1326
1327
1328
1329
1330
1331#define ___read_32bit_c0_register(source, sel, vol) \
1332({ unsigned int __res; \
1333 if (sel == 0) \
1334 __asm__ vol( \
1335 "mfc0\t%0, " #source "\n\t" \
1336 : "=r" (__res)); \
1337 else \
1338 __asm__ vol( \
1339 ".set\tmips32\n\t" \
1340 "mfc0\t%0, " #source ", " #sel "\n\t" \
1341 ".set\tmips0\n\t" \
1342 : "=r" (__res)); \
1343 __res; \
1344})
1345
1346#define ___read_64bit_c0_register(source, sel, vol) \
1347({ unsigned long long __res; \
1348 if (sizeof(unsigned long) == 4) \
1349 __res = __read_64bit_c0_split(source, sel, vol); \
1350 else if (sel == 0) \
1351 __asm__ vol( \
1352 ".set\tmips3\n\t" \
1353 "dmfc0\t%0, " #source "\n\t" \
1354 ".set\tmips0" \
1355 : "=r" (__res)); \
1356 else \
1357 __asm__ vol( \
1358 ".set\tmips64\n\t" \
1359 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1360 ".set\tmips0" \
1361 : "=r" (__res)); \
1362 __res; \
1363})
1364
1365#define __read_32bit_c0_register(source, sel) \
1366 ___read_32bit_c0_register(source, sel, __volatile__)
1367
1368#define __read_const_32bit_c0_register(source, sel) \
1369 ___read_32bit_c0_register(source, sel,)
1370
1371#define __read_64bit_c0_register(source, sel) \
1372 ___read_64bit_c0_register(source, sel, __volatile__)
1373
1374#define __read_const_64bit_c0_register(source, sel) \
1375 ___read_64bit_c0_register(source, sel,)
1376
1377#define __write_32bit_c0_register(register, sel, value) \
1378do { \
1379 if (sel == 0) \
1380 __asm__ __volatile__( \
1381 "mtc0\t%z0, " #register "\n\t" \
1382 : : "Jr" ((unsigned int)(value))); \
1383 else \
1384 __asm__ __volatile__( \
1385 ".set\tmips32\n\t" \
1386 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1387 ".set\tmips0" \
1388 : : "Jr" ((unsigned int)(value))); \
1389} while (0)
1390
1391#define __write_64bit_c0_register(register, sel, value) \
1392do { \
1393 if (sizeof(unsigned long) == 4) \
1394 __write_64bit_c0_split(register, sel, value); \
1395 else if (sel == 0) \
1396 __asm__ __volatile__( \
1397 ".set\tmips3\n\t" \
1398 "dmtc0\t%z0, " #register "\n\t" \
1399 ".set\tmips0" \
1400 : : "Jr" (value)); \
1401 else \
1402 __asm__ __volatile__( \
1403 ".set\tmips64\n\t" \
1404 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1405 ".set\tmips0" \
1406 : : "Jr" (value)); \
1407} while (0)
1408
1409#define __read_ulong_c0_register(reg, sel) \
1410 ((sizeof(unsigned long) == 4) ? \
1411 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1412 (unsigned long) __read_64bit_c0_register(reg, sel))
1413
1414#define __read_const_ulong_c0_register(reg, sel) \
1415 ((sizeof(unsigned long) == 4) ? \
1416 (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
1417 (unsigned long) __read_const_64bit_c0_register(reg, sel))
1418
1419#define __write_ulong_c0_register(reg, sel, val) \
1420do { \
1421 if (sizeof(unsigned long) == 4) \
1422 __write_32bit_c0_register(reg, sel, val); \
1423 else \
1424 __write_64bit_c0_register(reg, sel, val); \
1425} while (0)
1426
1427
1428
1429
1430#define __read_32bit_c0_ctrl_register(source) \
1431({ unsigned int __res; \
1432 __asm__ __volatile__( \
1433 "cfc0\t%0, " #source "\n\t" \
1434 : "=r" (__res)); \
1435 __res; \
1436})
1437
1438#define __write_32bit_c0_ctrl_register(register, value) \
1439do { \
1440 __asm__ __volatile__( \
1441 "ctc0\t%z0, " #register "\n\t" \
1442 : : "Jr" ((unsigned int)(value))); \
1443} while (0)
1444
1445
1446
1447
1448
1449#define __read_64bit_c0_split(source, sel, vol) \
1450({ \
1451 unsigned long long __val; \
1452 unsigned long __flags; \
1453 \
1454 local_irq_save(__flags); \
1455 if (sel == 0) \
1456 __asm__ vol( \
1457 ".set\tmips64\n\t" \
1458 "dmfc0\t%L0, " #source "\n\t" \
1459 "dsra\t%M0, %L0, 32\n\t" \
1460 "sll\t%L0, %L0, 0\n\t" \
1461 ".set\tmips0" \
1462 : "=r" (__val)); \
1463 else \
1464 __asm__ vol( \
1465 ".set\tmips64\n\t" \
1466 "dmfc0\t%L0, " #source ", " #sel "\n\t" \
1467 "dsra\t%M0, %L0, 32\n\t" \
1468 "sll\t%L0, %L0, 0\n\t" \
1469 ".set\tmips0" \
1470 : "=r" (__val)); \
1471 local_irq_restore(__flags); \
1472 \
1473 __val; \
1474})
1475
1476#define __write_64bit_c0_split(source, sel, val) \
1477do { \
1478 unsigned long long __tmp; \
1479 unsigned long __flags; \
1480 \
1481 local_irq_save(__flags); \
1482 if (sel == 0) \
1483 __asm__ __volatile__( \
1484 ".set\tmips64\n\t" \
1485 "dsll\t%L0, %L1, 32\n\t" \
1486 "dsrl\t%L0, %L0, 32\n\t" \
1487 "dsll\t%M0, %M1, 32\n\t" \
1488 "or\t%L0, %L0, %M0\n\t" \
1489 "dmtc0\t%L0, " #source "\n\t" \
1490 ".set\tmips0" \
1491 : "=&r,r" (__tmp) \
1492 : "r,0" (val)); \
1493 else \
1494 __asm__ __volatile__( \
1495 ".set\tmips64\n\t" \
1496 "dsll\t%L0, %L1, 32\n\t" \
1497 "dsrl\t%L0, %L0, 32\n\t" \
1498 "dsll\t%M0, %M1, 32\n\t" \
1499 "or\t%L0, %L0, %M0\n\t" \
1500 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1501 ".set\tmips0" \
1502 : "=&r,r" (__tmp) \
1503 : "r,0" (val)); \
1504 local_irq_restore(__flags); \
1505} while (0)
1506
1507#ifndef TOOLCHAIN_SUPPORTS_XPA
1508_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1509 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1510 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1511_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1512 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1513 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1514#define _ASM_SET_XPA ""
1515#else
1516#define _ASM_SET_XPA ".set\txpa\n\t"
1517#endif
1518
1519#define __readx_32bit_c0_register(source, sel) \
1520({ \
1521 unsigned int __res; \
1522 \
1523 __asm__ __volatile__( \
1524 " .set push \n" \
1525 " .set mips32r2 \n" \
1526 _ASM_SET_XPA \
1527 " mfhc0 %0, " #source ", %1 \n" \
1528 " .set pop \n" \
1529 : "=r" (__res) \
1530 : "i" (sel)); \
1531 __res; \
1532})
1533
1534#define __writex_32bit_c0_register(register, sel, value) \
1535do { \
1536 __asm__ __volatile__( \
1537 " .set push \n" \
1538 " .set mips32r2 \n" \
1539 _ASM_SET_XPA \
1540 " mthc0 %z0, " #register ", %1 \n" \
1541 " .set pop \n" \
1542 : \
1543 : "Jr" (value), "i" (sel)); \
1544} while (0)
1545
1546#define read_c0_index() __read_32bit_c0_register($0, 0)
1547#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1548
1549#define read_c0_random() __read_32bit_c0_register($1, 0)
1550#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1551
1552#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1553#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1554
1555#define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1556#define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1557
1558#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1559#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1560
1561#define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1562#define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1563
1564#define read_c0_conf() __read_32bit_c0_register($3, 0)
1565#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1566
1567#define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
1568
1569#define read_c0_context() __read_ulong_c0_register($4, 0)
1570#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1571
1572#define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1573#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1574
1575#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1576#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1577
1578#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1579#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1580
1581#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1582#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1583
1584#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1585#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1586
1587#define read_c0_wired() __read_32bit_c0_register($6, 0)
1588#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1589
1590#define read_c0_info() __read_32bit_c0_register($7, 0)
1591
1592#define read_c0_cache() __read_32bit_c0_register($7, 0)
1593#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1594
1595#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1596#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1597
1598#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1599#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1600
1601#define read_c0_count() __read_32bit_c0_register($9, 0)
1602#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1603
1604#define read_c0_count2() __read_32bit_c0_register($9, 6)
1605#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1606
1607#define read_c0_count3() __read_32bit_c0_register($9, 7)
1608#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1609
1610#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1611#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1612
1613#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1614#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1615
1616#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1617#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1618
1619#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1620#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1621
1622#define read_c0_compare() __read_32bit_c0_register($11, 0)
1623#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1624
1625#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1626#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1627
1628#define read_c0_compare2() __read_32bit_c0_register($11, 6)
1629#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1630
1631#define read_c0_compare3() __read_32bit_c0_register($11, 7)
1632#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1633
1634#define read_c0_status() __read_32bit_c0_register($12, 0)
1635
1636#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1637
1638#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1639#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1640
1641#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1642#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1643
1644#define read_c0_cause() __read_32bit_c0_register($13, 0)
1645#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1646
1647#define read_c0_epc() __read_ulong_c0_register($14, 0)
1648#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1649
1650#define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1651
1652#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1653
1654#define read_c0_config() __read_32bit_c0_register($16, 0)
1655#define read_c0_config1() __read_32bit_c0_register($16, 1)
1656#define read_c0_config2() __read_32bit_c0_register($16, 2)
1657#define read_c0_config3() __read_32bit_c0_register($16, 3)
1658#define read_c0_config4() __read_32bit_c0_register($16, 4)
1659#define read_c0_config5() __read_32bit_c0_register($16, 5)
1660#define read_c0_config6() __read_32bit_c0_register($16, 6)
1661#define read_c0_config7() __read_32bit_c0_register($16, 7)
1662#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1663#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1664#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1665#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1666#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1667#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1668#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1669#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1670
1671#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1672#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1673#define read_c0_maar() __read_ulong_c0_register($17, 1)
1674#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1675#define read_c0_maari() __read_32bit_c0_register($17, 2)
1676#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1677
1678
1679
1680
1681#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1682#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1683#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1684#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1685#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1686#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1687#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1688#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1689#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1690#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1691#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1692#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1693#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1694#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1695#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1696#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1697
1698
1699
1700
1701#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1702#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1703#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1704#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1705#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1706#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1707#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1708#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1709
1710#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1711#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1712#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1713#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1714#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1715#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1716#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1717#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1718
1719#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1720#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1721
1722#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1723#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1724
1725#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1726#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1727
1728#define read_c0_diag() __read_32bit_c0_register($22, 0)
1729#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1730
1731
1732#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1733#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1734
1735#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1736#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1737
1738#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1739#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1740
1741#define read_c0_diag3() __read_32bit_c0_register($22, 3)
1742#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1743
1744#define read_c0_diag4() __read_32bit_c0_register($22, 4)
1745#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1746
1747#define read_c0_diag5() __read_32bit_c0_register($22, 5)
1748#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1749
1750#define read_c0_debug() __read_32bit_c0_register($23, 0)
1751#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1752
1753#define read_c0_depc() __read_ulong_c0_register($24, 0)
1754#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1755
1756
1757
1758
1759#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1760#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1761#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1762#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1763#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1764#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1765#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1766#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1767#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1768#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1769#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1770#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1771#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1772#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1773#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1774#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1775#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1776#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1777#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1778#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1779#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1780#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1781#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1782#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1783
1784#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1785#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1786
1787#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1788#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1789
1790#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1791
1792#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1793#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1794
1795#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1796#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1797
1798#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1799#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1800
1801#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1802#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1803
1804#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1805#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1806
1807#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1808#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1809
1810#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1811#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1812
1813
1814#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1815#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1816
1817#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1818#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1819
1820#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1821#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1822
1823#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1824#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1825
1826#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1827#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1828
1829#define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1830#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1831
1832#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1833#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1834
1835
1836#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1837#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1838
1839#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1840#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1841
1842#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1843#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1844
1845
1846#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1847#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1848
1849#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1850#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1851
1852#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1853#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1854
1855#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1856#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1857
1858#define read_c0_pgd() __read_64bit_c0_register($9, 7)
1859#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1860
1861#define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1862#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1863
1864
1865#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1866#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1867
1868#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1869#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1870
1871#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1872#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1873
1874#define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
1875#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1876
1877#define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
1878#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1879
1880
1881
1882
1883
1884#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1885#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1886
1887#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1888#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1889
1890
1891#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1892#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1893
1894#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1895#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1896
1897#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1898#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1899
1900
1901#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1902#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1903
1904#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1905#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1906
1907#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1908#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1909
1910#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1911#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1912
1913#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1914#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1915
1916
1917#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1918#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1919
1920#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1921#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1922
1923#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1924#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1925
1926#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1927#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1928
1929#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1930#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1931
1932#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1933#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1934
1935
1936
1937
1938
1939#ifndef TOOLCHAIN_SUPPORTS_VIRT
1940_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
1941 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
1942 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1943_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
1944 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
1945 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1946_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
1947 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
1948 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1949_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
1950 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
1951 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1952_ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010)
1953 _ASM_INSN32_IF_MM(0x0000017c));
1954_ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009)
1955 _ASM_INSN32_IF_MM(0x0000117c));
1956_ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a)
1957 _ASM_INSN32_IF_MM(0x0000217c));
1958_ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e)
1959 _ASM_INSN32_IF_MM(0x0000317c));
1960_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
1961 _ASM_INSN32_IF_MM(0x0000517c));
1962#define _ASM_SET_VIRT ""
1963#else
1964#define _ASM_SET_VIRT ".set\tvirt\n\t"
1965#endif
1966
1967#define __read_32bit_gc0_register(source, sel) \
1968({ int __res; \
1969 __asm__ __volatile__( \
1970 ".set\tpush\n\t" \
1971 ".set\tmips32r2\n\t" \
1972 _ASM_SET_VIRT \
1973 "mfgc0\t%0, " #source ", %1\n\t" \
1974 ".set\tpop" \
1975 : "=r" (__res) \
1976 : "i" (sel)); \
1977 __res; \
1978})
1979
1980#define __read_64bit_gc0_register(source, sel) \
1981({ unsigned long long __res; \
1982 __asm__ __volatile__( \
1983 ".set\tpush\n\t" \
1984 ".set\tmips64r2\n\t" \
1985 _ASM_SET_VIRT \
1986 "dmfgc0\t%0, " #source ", %1\n\t" \
1987 ".set\tpop" \
1988 : "=r" (__res) \
1989 : "i" (sel)); \
1990 __res; \
1991})
1992
1993#define __write_32bit_gc0_register(register, sel, value) \
1994do { \
1995 __asm__ __volatile__( \
1996 ".set\tpush\n\t" \
1997 ".set\tmips32r2\n\t" \
1998 _ASM_SET_VIRT \
1999 "mtgc0\t%z0, " #register ", %1\n\t" \
2000 ".set\tpop" \
2001 : : "Jr" ((unsigned int)(value)), \
2002 "i" (sel)); \
2003} while (0)
2004
2005#define __write_64bit_gc0_register(register, sel, value) \
2006do { \
2007 __asm__ __volatile__( \
2008 ".set\tpush\n\t" \
2009 ".set\tmips64r2\n\t" \
2010 _ASM_SET_VIRT \
2011 "dmtgc0\t%z0, " #register ", %1\n\t" \
2012 ".set\tpop" \
2013 : : "Jr" (value), \
2014 "i" (sel)); \
2015} while (0)
2016
2017#define __read_ulong_gc0_register(reg, sel) \
2018 ((sizeof(unsigned long) == 4) ? \
2019 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
2020 (unsigned long) __read_64bit_gc0_register(reg, sel))
2021
2022#define __write_ulong_gc0_register(reg, sel, val) \
2023do { \
2024 if (sizeof(unsigned long) == 4) \
2025 __write_32bit_gc0_register(reg, sel, val); \
2026 else \
2027 __write_64bit_gc0_register(reg, sel, val); \
2028} while (0)
2029
2030#define read_gc0_index() __read_32bit_gc0_register($0, 0)
2031#define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2032
2033#define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2034#define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2035
2036#define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2037#define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2038
2039#define read_gc0_context() __read_ulong_gc0_register($4, 0)
2040#define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2041
2042#define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
2043#define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
2044
2045#define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
2046#define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
2047
2048#define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
2049#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
2050
2051#define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2052#define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2053
2054#define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
2055#define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
2056
2057#define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
2058#define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
2059
2060#define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
2061#define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
2062
2063#define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
2064#define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
2065
2066#define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
2067#define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
2068
2069#define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
2070#define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
2071
2072#define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
2073#define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
2074
2075#define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2076#define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2077
2078#define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
2079#define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
2080
2081#define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2082#define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2083
2084#define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2085#define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2086
2087#define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
2088#define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
2089
2090#define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
2091#define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
2092
2093#define read_gc0_count() __read_32bit_gc0_register($9, 0)
2094
2095#define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2096#define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2097
2098#define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2099#define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2100
2101#define read_gc0_status() __read_32bit_gc0_register($12, 0)
2102#define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2103
2104#define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
2105#define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
2106
2107#define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2108#define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2109
2110#define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2111#define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2112
2113#define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2114
2115#define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
2116#define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
2117
2118#define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
2119#define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
2120
2121#define read_gc0_config() __read_32bit_gc0_register($16, 0)
2122#define read_gc0_config1() __read_32bit_gc0_register($16, 1)
2123#define read_gc0_config2() __read_32bit_gc0_register($16, 2)
2124#define read_gc0_config3() __read_32bit_gc0_register($16, 3)
2125#define read_gc0_config4() __read_32bit_gc0_register($16, 4)
2126#define read_gc0_config5() __read_32bit_gc0_register($16, 5)
2127#define read_gc0_config6() __read_32bit_gc0_register($16, 6)
2128#define read_gc0_config7() __read_32bit_gc0_register($16, 7)
2129#define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2130#define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
2131#define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
2132#define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
2133#define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
2134#define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
2135#define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
2136#define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
2137
2138#define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2139#define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2140
2141#define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2142#define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2143#define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2144#define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2145#define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2146#define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2147#define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2148#define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2149#define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2150#define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2151#define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2152#define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2153#define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2154#define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2155#define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2156#define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2157
2158#define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2159#define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
2160#define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
2161#define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
2162#define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
2163#define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
2164#define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
2165#define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
2166#define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2167#define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
2168#define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
2169#define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
2170#define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
2171#define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
2172#define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
2173#define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
2174
2175#define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2176#define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2177
2178#define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2179#define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2180#define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2181#define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2182#define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2183#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2184#define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2185#define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2186#define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2187#define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2188#define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2189#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2190#define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2191#define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2192#define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2193#define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2194#define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2195#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2196#define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2197#define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2198#define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2199#define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2200#define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2201#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
2202
2203#define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2204#define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2205
2206#define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
2207#define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
2208#define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
2209#define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
2210#define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
2211#define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
2212#define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
2213#define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
2214#define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
2215#define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
2216#define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
2217#define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
2218
2219
2220#define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
2221#define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
2222
2223#define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
2224#define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
2225
2226#define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
2227#define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
2228
2229#define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
2230#define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
2231
2232
2233
2234
2235#define _read_32bit_cp1_register(source, gas_hardfloat) \
2236({ \
2237 unsigned int __res; \
2238 \
2239 __asm__ __volatile__( \
2240 " .set push \n" \
2241 " .set reorder \n" \
2242 " # gas fails to assemble cfc1 for some archs, \n" \
2243 " # like Octeon. \n" \
2244 " .set mips1 \n" \
2245 " "STR(gas_hardfloat)" \n" \
2246 " cfc1 %0,"STR(source)" \n" \
2247 " .set pop \n" \
2248 : "=r" (__res)); \
2249 __res; \
2250})
2251
2252#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2253do { \
2254 __asm__ __volatile__( \
2255 " .set push \n" \
2256 " .set reorder \n" \
2257 " "STR(gas_hardfloat)" \n" \
2258 " ctc1 %0,"STR(dest)" \n" \
2259 " .set pop \n" \
2260 : : "r" (val)); \
2261} while (0)
2262
2263#ifdef GAS_HAS_SET_HARDFLOAT
2264#define read_32bit_cp1_register(source) \
2265 _read_32bit_cp1_register(source, .set hardfloat)
2266#define write_32bit_cp1_register(dest, val) \
2267 _write_32bit_cp1_register(dest, val, .set hardfloat)
2268#else
2269#define read_32bit_cp1_register(source) \
2270 _read_32bit_cp1_register(source, )
2271#define write_32bit_cp1_register(dest, val) \
2272 _write_32bit_cp1_register(dest, val, )
2273#endif
2274
2275#ifdef HAVE_AS_DSP
2276#define rddsp(mask) \
2277({ \
2278 unsigned int __dspctl; \
2279 \
2280 __asm__ __volatile__( \
2281 " .set push \n" \
2282 " .set dsp \n" \
2283 " rddsp %0, %x1 \n" \
2284 " .set pop \n" \
2285 : "=r" (__dspctl) \
2286 : "i" (mask)); \
2287 __dspctl; \
2288})
2289
2290#define wrdsp(val, mask) \
2291do { \
2292 __asm__ __volatile__( \
2293 " .set push \n" \
2294 " .set dsp \n" \
2295 " wrdsp %0, %x1 \n" \
2296 " .set pop \n" \
2297 : \
2298 : "r" (val), "i" (mask)); \
2299} while (0)
2300
2301#define mflo0() \
2302({ \
2303 long mflo0; \
2304 __asm__( \
2305 " .set push \n" \
2306 " .set dsp \n" \
2307 " mflo %0, $ac0 \n" \
2308 " .set pop \n" \
2309 : "=r" (mflo0)); \
2310 mflo0; \
2311})
2312
2313#define mflo1() \
2314({ \
2315 long mflo1; \
2316 __asm__( \
2317 " .set push \n" \
2318 " .set dsp \n" \
2319 " mflo %0, $ac1 \n" \
2320 " .set pop \n" \
2321 : "=r" (mflo1)); \
2322 mflo1; \
2323})
2324
2325#define mflo2() \
2326({ \
2327 long mflo2; \
2328 __asm__( \
2329 " .set push \n" \
2330 " .set dsp \n" \
2331 " mflo %0, $ac2 \n" \
2332 " .set pop \n" \
2333 : "=r" (mflo2)); \
2334 mflo2; \
2335})
2336
2337#define mflo3() \
2338({ \
2339 long mflo3; \
2340 __asm__( \
2341 " .set push \n" \
2342 " .set dsp \n" \
2343 " mflo %0, $ac3 \n" \
2344 " .set pop \n" \
2345 : "=r" (mflo3)); \
2346 mflo3; \
2347})
2348
2349#define mfhi0() \
2350({ \
2351 long mfhi0; \
2352 __asm__( \
2353 " .set push \n" \
2354 " .set dsp \n" \
2355 " mfhi %0, $ac0 \n" \
2356 " .set pop \n" \
2357 : "=r" (mfhi0)); \
2358 mfhi0; \
2359})
2360
2361#define mfhi1() \
2362({ \
2363 long mfhi1; \
2364 __asm__( \
2365 " .set push \n" \
2366 " .set dsp \n" \
2367 " mfhi %0, $ac1 \n" \
2368 " .set pop \n" \
2369 : "=r" (mfhi1)); \
2370 mfhi1; \
2371})
2372
2373#define mfhi2() \
2374({ \
2375 long mfhi2; \
2376 __asm__( \
2377 " .set push \n" \
2378 " .set dsp \n" \
2379 " mfhi %0, $ac2 \n" \
2380 " .set pop \n" \
2381 : "=r" (mfhi2)); \
2382 mfhi2; \
2383})
2384
2385#define mfhi3() \
2386({ \
2387 long mfhi3; \
2388 __asm__( \
2389 " .set push \n" \
2390 " .set dsp \n" \
2391 " mfhi %0, $ac3 \n" \
2392 " .set pop \n" \
2393 : "=r" (mfhi3)); \
2394 mfhi3; \
2395})
2396
2397
2398#define mtlo0(x) \
2399({ \
2400 __asm__( \
2401 " .set push \n" \
2402 " .set dsp \n" \
2403 " mtlo %0, $ac0 \n" \
2404 " .set pop \n" \
2405 : \
2406 : "r" (x)); \
2407})
2408
2409#define mtlo1(x) \
2410({ \
2411 __asm__( \
2412 " .set push \n" \
2413 " .set dsp \n" \
2414 " mtlo %0, $ac1 \n" \
2415 " .set pop \n" \
2416 : \
2417 : "r" (x)); \
2418})
2419
2420#define mtlo2(x) \
2421({ \
2422 __asm__( \
2423 " .set push \n" \
2424 " .set dsp \n" \
2425 " mtlo %0, $ac2 \n" \
2426 " .set pop \n" \
2427 : \
2428 : "r" (x)); \
2429})
2430
2431#define mtlo3(x) \
2432({ \
2433 __asm__( \
2434 " .set push \n" \
2435 " .set dsp \n" \
2436 " mtlo %0, $ac3 \n" \
2437 " .set pop \n" \
2438 : \
2439 : "r" (x)); \
2440})
2441
2442#define mthi0(x) \
2443({ \
2444 __asm__( \
2445 " .set push \n" \
2446 " .set dsp \n" \
2447 " mthi %0, $ac0 \n" \
2448 " .set pop \n" \
2449 : \
2450 : "r" (x)); \
2451})
2452
2453#define mthi1(x) \
2454({ \
2455 __asm__( \
2456 " .set push \n" \
2457 " .set dsp \n" \
2458 " mthi %0, $ac1 \n" \
2459 " .set pop \n" \
2460 : \
2461 : "r" (x)); \
2462})
2463
2464#define mthi2(x) \
2465({ \
2466 __asm__( \
2467 " .set push \n" \
2468 " .set dsp \n" \
2469 " mthi %0, $ac2 \n" \
2470 " .set pop \n" \
2471 : \
2472 : "r" (x)); \
2473})
2474
2475#define mthi3(x) \
2476({ \
2477 __asm__( \
2478 " .set push \n" \
2479 " .set dsp \n" \
2480 " mthi %0, $ac3 \n" \
2481 " .set pop \n" \
2482 : \
2483 : "r" (x)); \
2484})
2485
2486#else
2487
2488#define rddsp(mask) \
2489({ \
2490 unsigned int __res; \
2491 \
2492 __asm__ __volatile__( \
2493 " .set push \n" \
2494 " .set noat \n" \
2495 " # rddsp $1, %x1 \n" \
2496 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2497 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2498 " move %0, $1 \n" \
2499 " .set pop \n" \
2500 : "=r" (__res) \
2501 : "i" (mask)); \
2502 __res; \
2503})
2504
2505#define wrdsp(val, mask) \
2506do { \
2507 __asm__ __volatile__( \
2508 " .set push \n" \
2509 " .set noat \n" \
2510 " move $1, %0 \n" \
2511 " # wrdsp $1, %x1 \n" \
2512 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2513 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2514 " .set pop \n" \
2515 : \
2516 : "r" (val), "i" (mask)); \
2517} while (0)
2518
2519#define _dsp_mfxxx(ins) \
2520({ \
2521 unsigned long __treg; \
2522 \
2523 __asm__ __volatile__( \
2524 " .set push \n" \
2525 " .set noat \n" \
2526 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2527 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2528 " move %0, $1 \n" \
2529 " .set pop \n" \
2530 : "=r" (__treg) \
2531 : "i" (ins)); \
2532 __treg; \
2533})
2534
2535#define _dsp_mtxxx(val, ins) \
2536do { \
2537 __asm__ __volatile__( \
2538 " .set push \n" \
2539 " .set noat \n" \
2540 " move $1, %0 \n" \
2541 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2542 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2543 " .set pop \n" \
2544 : \
2545 : "r" (val), "i" (ins)); \
2546} while (0)
2547
2548#ifdef CONFIG_CPU_MICROMIPS
2549
2550#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2551#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2552
2553#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2554#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2555
2556#else
2557
2558#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2559#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2560
2561#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2562#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2563
2564#endif
2565
2566#define mflo0() _dsp_mflo(0)
2567#define mflo1() _dsp_mflo(1)
2568#define mflo2() _dsp_mflo(2)
2569#define mflo3() _dsp_mflo(3)
2570
2571#define mfhi0() _dsp_mfhi(0)
2572#define mfhi1() _dsp_mfhi(1)
2573#define mfhi2() _dsp_mfhi(2)
2574#define mfhi3() _dsp_mfhi(3)
2575
2576#define mtlo0(x) _dsp_mtlo(x, 0)
2577#define mtlo1(x) _dsp_mtlo(x, 1)
2578#define mtlo2(x) _dsp_mtlo(x, 2)
2579#define mtlo3(x) _dsp_mtlo(x, 3)
2580
2581#define mthi0(x) _dsp_mthi(x, 0)
2582#define mthi1(x) _dsp_mthi(x, 1)
2583#define mthi2(x) _dsp_mthi(x, 2)
2584#define mthi3(x) _dsp_mthi(x, 3)
2585
2586#endif
2587
2588
2589
2590
2591
2592
2593static inline void tlb_probe(void)
2594{
2595 __asm__ __volatile__(
2596 ".set noreorder\n\t"
2597 "tlbp\n\t"
2598 ".set reorder");
2599}
2600
2601static inline void tlb_read(void)
2602{
2603#if MIPS34K_MISSED_ITLB_WAR
2604 int res = 0;
2605
2606 __asm__ __volatile__(
2607 " .set push \n"
2608 " .set noreorder \n"
2609 " .set noat \n"
2610 " .set mips32r2 \n"
2611 " .word 0x41610001 # dvpe $1 \n"
2612 " move %0, $1 \n"
2613 " ehb \n"
2614 " .set pop \n"
2615 : "=r" (res));
2616
2617 instruction_hazard();
2618#endif
2619
2620 __asm__ __volatile__(
2621 ".set noreorder\n\t"
2622 "tlbr\n\t"
2623 ".set reorder");
2624
2625#if MIPS34K_MISSED_ITLB_WAR
2626 if ((res & _ULCAST_(1)))
2627 __asm__ __volatile__(
2628 " .set push \n"
2629 " .set noreorder \n"
2630 " .set noat \n"
2631 " .set mips32r2 \n"
2632 " .word 0x41600021 # evpe \n"
2633 " ehb \n"
2634 " .set pop \n");
2635#endif
2636}
2637
2638static inline void tlb_write_indexed(void)
2639{
2640 __asm__ __volatile__(
2641 ".set noreorder\n\t"
2642 "tlbwi\n\t"
2643 ".set reorder");
2644}
2645
2646static inline void tlb_write_random(void)
2647{
2648 __asm__ __volatile__(
2649 ".set noreorder\n\t"
2650 "tlbwr\n\t"
2651 ".set reorder");
2652}
2653
2654
2655
2656
2657
2658
2659static inline void guest_tlb_probe(void)
2660{
2661 __asm__ __volatile__(
2662 ".set push\n\t"
2663 ".set noreorder\n\t"
2664 _ASM_SET_VIRT
2665 "tlbgp\n\t"
2666 ".set pop");
2667}
2668
2669static inline void guest_tlb_read(void)
2670{
2671 __asm__ __volatile__(
2672 ".set push\n\t"
2673 ".set noreorder\n\t"
2674 _ASM_SET_VIRT
2675 "tlbgr\n\t"
2676 ".set pop");
2677}
2678
2679static inline void guest_tlb_write_indexed(void)
2680{
2681 __asm__ __volatile__(
2682 ".set push\n\t"
2683 ".set noreorder\n\t"
2684 _ASM_SET_VIRT
2685 "tlbgwi\n\t"
2686 ".set pop");
2687}
2688
2689static inline void guest_tlb_write_random(void)
2690{
2691 __asm__ __volatile__(
2692 ".set push\n\t"
2693 ".set noreorder\n\t"
2694 _ASM_SET_VIRT
2695 "tlbgwr\n\t"
2696 ".set pop");
2697}
2698
2699
2700
2701
2702static inline void guest_tlbinvf(void)
2703{
2704 __asm__ __volatile__(
2705 ".set push\n\t"
2706 ".set noreorder\n\t"
2707 _ASM_SET_VIRT
2708 "tlbginvf\n\t"
2709 ".set pop");
2710}
2711
2712
2713
2714
2715#define __BUILD_SET_COMMON(name) \
2716static inline unsigned int \
2717set_##name(unsigned int set) \
2718{ \
2719 unsigned int res, new; \
2720 \
2721 res = read_##name(); \
2722 new = res | set; \
2723 write_##name(new); \
2724 \
2725 return res; \
2726} \
2727 \
2728static inline unsigned int \
2729clear_##name(unsigned int clear) \
2730{ \
2731 unsigned int res, new; \
2732 \
2733 res = read_##name(); \
2734 new = res & ~clear; \
2735 write_##name(new); \
2736 \
2737 return res; \
2738} \
2739 \
2740static inline unsigned int \
2741change_##name(unsigned int change, unsigned int val) \
2742{ \
2743 unsigned int res, new; \
2744 \
2745 res = read_##name(); \
2746 new = res & ~change; \
2747 new |= (val & change); \
2748 write_##name(new); \
2749 \
2750 return res; \
2751}
2752
2753
2754
2755
2756#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2757
2758__BUILD_SET_C0(status)
2759__BUILD_SET_C0(cause)
2760__BUILD_SET_C0(config)
2761__BUILD_SET_C0(config5)
2762__BUILD_SET_C0(intcontrol)
2763__BUILD_SET_C0(intctl)
2764__BUILD_SET_C0(srsmap)
2765__BUILD_SET_C0(pagegrain)
2766__BUILD_SET_C0(guestctl0)
2767__BUILD_SET_C0(guestctl0ext)
2768__BUILD_SET_C0(guestctl1)
2769__BUILD_SET_C0(guestctl2)
2770__BUILD_SET_C0(guestctl3)
2771__BUILD_SET_C0(brcm_config_0)
2772__BUILD_SET_C0(brcm_bus_pll)
2773__BUILD_SET_C0(brcm_reset)
2774__BUILD_SET_C0(brcm_cmt_intr)
2775__BUILD_SET_C0(brcm_cmt_ctrl)
2776__BUILD_SET_C0(brcm_config)
2777__BUILD_SET_C0(brcm_mode)
2778
2779
2780
2781
2782#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2783
2784__BUILD_SET_GC0(wired)
2785__BUILD_SET_GC0(status)
2786__BUILD_SET_GC0(cause)
2787__BUILD_SET_GC0(ebase)
2788__BUILD_SET_GC0(config1)
2789
2790
2791
2792
2793
2794static inline unsigned int get_ebase_cpunum(void)
2795{
2796 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2797}
2798
2799#endif
2800
2801#endif
2802