linux/arch/mips/include/asm/sn/ioc3.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) 1999, 2000 Ralf Baechle
   4 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   5 */
   6#ifndef _IOC3_H
   7#define _IOC3_H
   8
   9#include <linux/types.h>
  10
  11/* SUPERIO uart register map */
  12typedef volatile struct ioc3_uartregs {
  13        union {
  14                volatile u8     rbr;    /* read only, DLAB == 0 */
  15                volatile u8     thr;    /* write only, DLAB == 0 */
  16                volatile u8     dll;    /* DLAB == 1 */
  17        } u1;
  18        union {
  19                volatile u8     ier;    /* DLAB == 0 */
  20                volatile u8     dlm;    /* DLAB == 1 */
  21        } u2;
  22        union {
  23                volatile u8     iir;    /* read only */
  24                volatile u8     fcr;    /* write only */
  25        } u3;
  26        volatile u8         iu_lcr;
  27        volatile u8         iu_mcr;
  28        volatile u8         iu_lsr;
  29        volatile u8         iu_msr;
  30        volatile u8         iu_scr;
  31} ioc3_uregs_t;
  32
  33#define iu_rbr u1.rbr
  34#define iu_thr u1.thr
  35#define iu_dll u1.dll
  36#define iu_ier u2.ier
  37#define iu_dlm u2.dlm
  38#define iu_iir u3.iir
  39#define iu_fcr u3.fcr
  40
  41struct ioc3_sioregs {
  42        volatile u8             fill[0x141];    /* starts at 0x141 */
  43
  44        volatile u8             uartc;
  45        volatile u8             kbdcg;
  46
  47        volatile u8             fill0[0x150 - 0x142 - 1];
  48
  49        volatile u8             pp_data;
  50        volatile u8             pp_dsr;
  51        volatile u8             pp_dcr;
  52
  53        volatile u8             fill1[0x158 - 0x152 - 1];
  54
  55        volatile u8             pp_fifa;
  56        volatile u8             pp_cfgb;
  57        volatile u8             pp_ecr;
  58
  59        volatile u8             fill2[0x168 - 0x15a - 1];
  60
  61        volatile u8             rtcad;
  62        volatile u8             rtcdat;
  63
  64        volatile u8             fill3[0x170 - 0x169 - 1];
  65
  66        struct ioc3_uartregs    uartb;  /* 0x20170  */
  67        struct ioc3_uartregs    uarta;  /* 0x20178  */
  68};
  69
  70/* Register layout of IOC3 in configuration space.  */
  71struct ioc3 {
  72        volatile u32    pad0[7];        /* 0x00000  */
  73        volatile u32    sio_ir;         /* 0x0001c  */
  74        volatile u32    sio_ies;        /* 0x00020  */
  75        volatile u32    sio_iec;        /* 0x00024  */
  76        volatile u32    sio_cr;         /* 0x00028  */
  77        volatile u32    int_out;        /* 0x0002c  */
  78        volatile u32    mcr;            /* 0x00030  */
  79
  80        /* General Purpose I/O registers  */
  81        volatile u32    gpcr_s;         /* 0x00034  */
  82        volatile u32    gpcr_c;         /* 0x00038  */
  83        volatile u32    gpdr;           /* 0x0003c  */
  84        volatile u32    gppr_0;         /* 0x00040  */
  85        volatile u32    gppr_1;         /* 0x00044  */
  86        volatile u32    gppr_2;         /* 0x00048  */
  87        volatile u32    gppr_3;         /* 0x0004c  */
  88        volatile u32    gppr_4;         /* 0x00050  */
  89        volatile u32    gppr_5;         /* 0x00054  */
  90        volatile u32    gppr_6;         /* 0x00058  */
  91        volatile u32    gppr_7;         /* 0x0005c  */
  92        volatile u32    gppr_8;         /* 0x00060  */
  93        volatile u32    gppr_9;         /* 0x00064  */
  94        volatile u32    gppr_10;        /* 0x00068  */
  95        volatile u32    gppr_11;        /* 0x0006c  */
  96        volatile u32    gppr_12;        /* 0x00070  */
  97        volatile u32    gppr_13;        /* 0x00074  */
  98        volatile u32    gppr_14;        /* 0x00078  */
  99        volatile u32    gppr_15;        /* 0x0007c  */
 100
 101        /* Parallel Port Registers  */
 102        volatile u32    ppbr_h_a;       /* 0x00080  */
 103        volatile u32    ppbr_l_a;       /* 0x00084  */
 104        volatile u32    ppcr_a;         /* 0x00088  */
 105        volatile u32    ppcr;           /* 0x0008c  */
 106        volatile u32    ppbr_h_b;       /* 0x00090  */
 107        volatile u32    ppbr_l_b;       /* 0x00094  */
 108        volatile u32    ppcr_b;         /* 0x00098  */
 109
 110        /* Keyboard and Mouse Registers  */
 111        volatile u32    km_csr;         /* 0x0009c  */
 112        volatile u32    k_rd;           /* 0x000a0  */
 113        volatile u32    m_rd;           /* 0x000a4  */
 114        volatile u32    k_wd;           /* 0x000a8  */
 115        volatile u32    m_wd;           /* 0x000ac  */
 116
 117        /* Serial Port Registers  */
 118        volatile u32    sbbr_h;         /* 0x000b0  */
 119        volatile u32    sbbr_l;         /* 0x000b4  */
 120        volatile u32    sscr_a;         /* 0x000b8  */
 121        volatile u32    stpir_a;        /* 0x000bc  */
 122        volatile u32    stcir_a;        /* 0x000c0  */
 123        volatile u32    srpir_a;        /* 0x000c4  */
 124        volatile u32    srcir_a;        /* 0x000c8  */
 125        volatile u32    srtr_a;         /* 0x000cc  */
 126        volatile u32    shadow_a;       /* 0x000d0  */
 127        volatile u32    sscr_b;         /* 0x000d4  */
 128        volatile u32    stpir_b;        /* 0x000d8  */
 129        volatile u32    stcir_b;        /* 0x000dc  */
 130        volatile u32    srpir_b;        /* 0x000e0  */
 131        volatile u32    srcir_b;        /* 0x000e4  */
 132        volatile u32    srtr_b;         /* 0x000e8  */
 133        volatile u32    shadow_b;       /* 0x000ec  */
 134
 135        /* Ethernet Registers  */
 136        volatile u32    emcr;           /* 0x000f0  */
 137        volatile u32    eisr;           /* 0x000f4  */
 138        volatile u32    eier;           /* 0x000f8  */
 139        volatile u32    ercsr;          /* 0x000fc  */
 140        volatile u32    erbr_h;         /* 0x00100  */
 141        volatile u32    erbr_l;         /* 0x00104  */
 142        volatile u32    erbar;          /* 0x00108  */
 143        volatile u32    ercir;          /* 0x0010c  */
 144        volatile u32    erpir;          /* 0x00110  */
 145        volatile u32    ertr;           /* 0x00114  */
 146        volatile u32    etcsr;          /* 0x00118  */
 147        volatile u32    ersr;           /* 0x0011c  */
 148        volatile u32    etcdc;          /* 0x00120  */
 149        volatile u32    ebir;           /* 0x00124  */
 150        volatile u32    etbr_h;         /* 0x00128  */
 151        volatile u32    etbr_l;         /* 0x0012c  */
 152        volatile u32    etcir;          /* 0x00130  */
 153        volatile u32    etpir;          /* 0x00134  */
 154        volatile u32    emar_h;         /* 0x00138  */
 155        volatile u32    emar_l;         /* 0x0013c  */
 156        volatile u32    ehar_h;         /* 0x00140  */
 157        volatile u32    ehar_l;         /* 0x00144  */
 158        volatile u32    micr;           /* 0x00148  */
 159        volatile u32    midr_r;         /* 0x0014c  */
 160        volatile u32    midr_w;         /* 0x00150  */
 161        volatile u32    pad1[(0x20000 - 0x00154) / 4];
 162
 163        /* SuperIO Registers  XXX */
 164        struct ioc3_sioregs     sregs;  /* 0x20000 */
 165        volatile u32    pad2[(0x40000 - 0x20180) / 4];
 166
 167        /* SSRAM Diagnostic Access */
 168        volatile u32    ssram[(0x80000 - 0x40000) / 4];
 169
 170        /* Bytebus device offsets
 171           0x80000 -   Access to the generic devices selected with   DEV0
 172           0x9FFFF     bytebus DEV_SEL_0
 173           0xA0000 -   Access to the generic devices selected with   DEV1
 174           0xBFFFF     bytebus DEV_SEL_1
 175           0xC0000 -   Access to the generic devices selected with   DEV2
 176           0xDFFFF     bytebus DEV_SEL_2
 177           0xE0000 -   Access to the generic devices selected with   DEV3
 178           0xFFFFF     bytebus DEV_SEL_3  */
 179};
 180
 181/*
 182 * Ethernet RX Buffer
 183 */
 184struct ioc3_erxbuf {
 185        u32     w0;                     /* first word (valid,bcnt,cksum) */
 186        u32     err;                    /* second word various errors */
 187        /* next comes n bytes of padding */
 188        /* then the received ethernet frame itself */
 189};
 190
 191#define ERXBUF_IPCKSUM_MASK     0x0000ffff
 192#define ERXBUF_BYTECNT_MASK     0x07ff0000
 193#define ERXBUF_BYTECNT_SHIFT    16
 194#define ERXBUF_V                0x80000000
 195
 196#define ERXBUF_CRCERR           0x00000001      /* aka RSV15 */
 197#define ERXBUF_FRAMERR          0x00000002      /* aka RSV14 */
 198#define ERXBUF_CODERR           0x00000004      /* aka RSV13 */
 199#define ERXBUF_INVPREAMB        0x00000008      /* aka RSV18 */
 200#define ERXBUF_LOLEN            0x00007000      /* aka RSV2_0 */
 201#define ERXBUF_HILEN            0x03ff0000      /* aka RSV12_3 */
 202#define ERXBUF_MULTICAST        0x04000000      /* aka RSV16 */
 203#define ERXBUF_BROADCAST        0x08000000      /* aka RSV17 */
 204#define ERXBUF_LONGEVENT        0x10000000      /* aka RSV19 */
 205#define ERXBUF_BADPKT           0x20000000      /* aka RSV20 */
 206#define ERXBUF_GOODPKT          0x40000000      /* aka RSV21 */
 207#define ERXBUF_CARRIER          0x80000000      /* aka RSV22 */
 208
 209/*
 210 * Ethernet TX Descriptor
 211 */
 212#define ETXD_DATALEN    104
 213struct ioc3_etxd {
 214        u32     cmd;                            /* command field */
 215        u32     bufcnt;                         /* buffer counts field */
 216        u64     p1;                             /* buffer pointer 1 */
 217        u64     p2;                             /* buffer pointer 2 */
 218        u8      data[ETXD_DATALEN];             /* opt. tx data */
 219};
 220
 221#define ETXD_BYTECNT_MASK       0x000007ff      /* total byte count */
 222#define ETXD_INTWHENDONE        0x00001000      /* intr when done */
 223#define ETXD_D0V                0x00010000      /* data 0 valid */
 224#define ETXD_B1V                0x00020000      /* buf 1 valid */
 225#define ETXD_B2V                0x00040000      /* buf 2 valid */
 226#define ETXD_DOCHECKSUM         0x00080000      /* insert ip cksum */
 227#define ETXD_CHKOFF_MASK        0x07f00000      /* cksum byte offset */
 228#define ETXD_CHKOFF_SHIFT       20
 229
 230#define ETXD_D0CNT_MASK         0x0000007f
 231#define ETXD_B1CNT_MASK         0x0007ff00
 232#define ETXD_B1CNT_SHIFT        8
 233#define ETXD_B2CNT_MASK         0x7ff00000
 234#define ETXD_B2CNT_SHIFT        20
 235
 236/*
 237 * Bytebus device space
 238 */
 239#define IOC3_BYTEBUS_DEV0       0x80000L
 240#define IOC3_BYTEBUS_DEV1       0xa0000L
 241#define IOC3_BYTEBUS_DEV2       0xc0000L
 242#define IOC3_BYTEBUS_DEV3       0xe0000L
 243
 244/* ------------------------------------------------------------------------- */
 245
 246/* Superio Registers (PIO Access) */
 247#define IOC3_SIO_BASE           0x20000
 248#define IOC3_SIO_UARTC          (IOC3_SIO_BASE+0x141)   /* UART Config */
 249#define IOC3_SIO_KBDCG          (IOC3_SIO_BASE+0x142)   /* KBD Config */
 250#define IOC3_SIO_PP_BASE        (IOC3_SIO_BASE+PP_BASE)         /* Parallel Port */
 251#define IOC3_SIO_RTC_BASE       (IOC3_SIO_BASE+0x168)   /* Real Time Clock */
 252#define IOC3_SIO_UB_BASE        (IOC3_SIO_BASE+UARTB_BASE)      /* UART B */
 253#define IOC3_SIO_UA_BASE        (IOC3_SIO_BASE+UARTA_BASE)      /* UART A */
 254
 255/* SSRAM Diagnostic Access */
 256#define IOC3_SSRAM      IOC3_RAM_OFF    /* base of SSRAM diagnostic access */
 257#define IOC3_SSRAM_LEN  0x40000 /* 256kb (address space size, may not be fully populated) */
 258#define IOC3_SSRAM_DM   0x0000ffff      /* data mask */
 259#define IOC3_SSRAM_PM   0x00010000      /* parity mask */
 260
 261/* bitmasks for PCI_SCR */
 262#define PCI_SCR_PAR_RESP_EN     0x00000040      /* enb PCI parity checking */
 263#define PCI_SCR_SERR_EN         0x00000100      /* enable the SERR# driver */
 264#define PCI_SCR_DROP_MODE_EN    0x00008000      /* drop pios on parity err */
 265#define PCI_SCR_RX_SERR         (0x1 << 16)
 266#define PCI_SCR_DROP_MODE       (0x1 << 17)
 267#define PCI_SCR_SIG_PAR_ERR     (0x1 << 24)
 268#define PCI_SCR_SIG_TAR_ABRT    (0x1 << 27)
 269#define PCI_SCR_RX_TAR_ABRT     (0x1 << 28)
 270#define PCI_SCR_SIG_MST_ABRT    (0x1 << 29)
 271#define PCI_SCR_SIG_SERR        (0x1 << 30)
 272#define PCI_SCR_PAR_ERR         (0x1 << 31)
 273
 274/* bitmasks for IOC3_KM_CSR */
 275#define KM_CSR_K_WRT_PEND 0x00000001    /* kbd port xmitting or resetting */
 276#define KM_CSR_M_WRT_PEND 0x00000002    /* mouse port xmitting or resetting */
 277#define KM_CSR_K_LCB      0x00000004    /* Line Cntrl Bit for last KBD write */
 278#define KM_CSR_M_LCB      0x00000008    /* same for mouse */
 279#define KM_CSR_K_DATA     0x00000010    /* state of kbd data line */
 280#define KM_CSR_K_CLK      0x00000020    /* state of kbd clock line */
 281#define KM_CSR_K_PULL_DATA 0x00000040   /* pull kbd data line low */
 282#define KM_CSR_K_PULL_CLK 0x00000080    /* pull kbd clock line low */
 283#define KM_CSR_M_DATA     0x00000100    /* state of ms data line */
 284#define KM_CSR_M_CLK      0x00000200    /* state of ms clock line */
 285#define KM_CSR_M_PULL_DATA 0x00000400   /* pull ms data line low */
 286#define KM_CSR_M_PULL_CLK 0x00000800    /* pull ms clock line low */
 287#define KM_CSR_EMM_MODE   0x00001000    /* emulation mode */
 288#define KM_CSR_SIM_MODE   0x00002000    /* clock X8 */
 289#define KM_CSR_K_SM_IDLE  0x00004000    /* Keyboard is idle */
 290#define KM_CSR_M_SM_IDLE  0x00008000    /* Mouse is idle */
 291#define KM_CSR_K_TO       0x00010000    /* Keyboard trying to send/receive */
 292#define KM_CSR_M_TO       0x00020000    /* Mouse trying to send/receive */
 293#define KM_CSR_K_TO_EN    0x00040000    /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
 294                                           SIO_IR to assert */
 295#define KM_CSR_M_TO_EN    0x00080000    /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
 296                                           SIO_IR to assert */
 297#define KM_CSR_K_CLAMP_ONE      0x00100000      /* Pull K_CLK low after rec. one char */
 298#define KM_CSR_M_CLAMP_ONE      0x00200000      /* Pull M_CLK low after rec. one char */
 299#define KM_CSR_K_CLAMP_THREE    0x00400000      /* Pull K_CLK low after rec. three chars */
 300#define KM_CSR_M_CLAMP_THREE    0x00800000      /* Pull M_CLK low after rec. three char */
 301
 302/* bitmasks for IOC3_K_RD and IOC3_M_RD */
 303#define KM_RD_DATA_2    0x000000ff      /* 3rd char recvd since last read */
 304#define KM_RD_DATA_2_SHIFT 0
 305#define KM_RD_DATA_1    0x0000ff00      /* 2nd char recvd since last read */
 306#define KM_RD_DATA_1_SHIFT 8
 307#define KM_RD_DATA_0    0x00ff0000      /* 1st char recvd since last read */
 308#define KM_RD_DATA_0_SHIFT 16
 309#define KM_RD_FRAME_ERR_2 0x01000000    /*  framing or parity error in byte 2 */
 310#define KM_RD_FRAME_ERR_1 0x02000000    /* same for byte 1 */
 311#define KM_RD_FRAME_ERR_0 0x04000000    /* same for byte 0 */
 312
 313#define KM_RD_KBD_MSE   0x08000000      /* 0 if from kbd, 1 if from mouse */
 314#define KM_RD_OFLO      0x10000000      /* 4th char recvd before this read */
 315#define KM_RD_VALID_2   0x20000000      /* DATA_2 valid */
 316#define KM_RD_VALID_1   0x40000000      /* DATA_1 valid */
 317#define KM_RD_VALID_0   0x80000000      /* DATA_0 valid */
 318#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
 319
 320/* bitmasks for IOC3_K_WD & IOC3_M_WD */
 321#define KM_WD_WRT_DATA  0x000000ff      /* write to keyboard/mouse port */
 322#define KM_WD_WRT_DATA_SHIFT 0
 323
 324/* bitmasks for serial RX status byte */
 325#define RXSB_OVERRUN    0x01    /* char(s) lost */
 326#define RXSB_PAR_ERR    0x02    /* parity error */
 327#define RXSB_FRAME_ERR  0x04    /* framing error */
 328#define RXSB_BREAK      0x08    /* break character */
 329#define RXSB_CTS        0x10    /* state of CTS */
 330#define RXSB_DCD        0x20    /* state of DCD */
 331#define RXSB_MODEM_VALID 0x40   /* DCD, CTS and OVERRUN are valid */
 332#define RXSB_DATA_VALID 0x80    /* data byte, FRAME_ERR PAR_ERR & BREAK valid */
 333
 334/* bitmasks for serial TX control byte */
 335#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
 336#define TXCB_INVALID    0x00    /* byte is invalid */
 337#define TXCB_VALID      0x40    /* byte is valid */
 338#define TXCB_MCR        0x80    /* data<7:0> to modem control register */
 339#define TXCB_DELAY      0xc0    /* delay data<7:0> mSec */
 340
 341/* bitmasks for IOC3_SBBR_L */
 342#define SBBR_L_SIZE     0x00000001      /* 0 == 1KB rings, 1 == 4KB rings */
 343#define SBBR_L_BASE     0xfffff000      /* lower serial ring base addr */
 344
 345/* bitmasks for IOC3_SSCR_<A:B> */
 346#define SSCR_RX_THRESHOLD 0x000001ff    /* hiwater mark */
 347#define SSCR_TX_TIMER_BUSY 0x00010000   /* TX timer in progress */
 348#define SSCR_HFC_EN     0x00020000      /* hardware flow control enabled */
 349#define SSCR_RX_RING_DCD 0x00040000     /* post RX record on delta-DCD */
 350#define SSCR_RX_RING_CTS 0x00080000     /* post RX record on delta-CTS */
 351#define SSCR_HIGH_SPD   0x00100000      /* 4X speed */
 352#define SSCR_DIAG       0x00200000      /* bypass clock divider for sim */
 353#define SSCR_RX_DRAIN   0x08000000      /* drain RX buffer to memory */
 354#define SSCR_DMA_EN     0x10000000      /* enable ring buffer DMA */
 355#define SSCR_DMA_PAUSE  0x20000000      /* pause DMA */
 356#define SSCR_PAUSE_STATE 0x40000000     /* sets when PAUSE takes effect */
 357#define SSCR_RESET      0x80000000      /* reset DMA channels */
 358
 359/* all producer/consumer pointers are the same bitfield */
 360#define PROD_CONS_PTR_4K 0x00000ff8     /* for 4K buffers */
 361#define PROD_CONS_PTR_1K 0x000003f8     /* for 1K buffers */
 362#define PROD_CONS_PTR_OFF 3
 363
 364/* bitmasks for IOC3_SRCIR_<A:B> */
 365#define SRCIR_ARM       0x80000000      /* arm RX timer */
 366
 367/* bitmasks for IOC3_SRPIR_<A:B> */
 368#define SRPIR_BYTE_CNT  0x07000000      /* bytes in packer */
 369#define SRPIR_BYTE_CNT_SHIFT 24
 370
 371/* bitmasks for IOC3_STCIR_<A:B> */
 372#define STCIR_BYTE_CNT  0x0f000000      /* bytes in unpacker */
 373#define STCIR_BYTE_CNT_SHIFT 24
 374
 375/* bitmasks for IOC3_SHADOW_<A:B> */
 376#define SHADOW_DR       0x00000001      /* data ready */
 377#define SHADOW_OE       0x00000002      /* overrun error */
 378#define SHADOW_PE       0x00000004      /* parity error */
 379#define SHADOW_FE       0x00000008      /* framing error */
 380#define SHADOW_BI       0x00000010      /* break interrupt */
 381#define SHADOW_THRE     0x00000020      /* transmit holding register empty */
 382#define SHADOW_TEMT     0x00000040      /* transmit shift register empty */
 383#define SHADOW_RFCE     0x00000080      /* char in RX fifo has an error */
 384#define SHADOW_DCTS     0x00010000      /* delta clear to send */
 385#define SHADOW_DDCD     0x00080000      /* delta data carrier detect */
 386#define SHADOW_CTS      0x00100000      /* clear to send */
 387#define SHADOW_DCD      0x00800000      /* data carrier detect */
 388#define SHADOW_DTR      0x01000000      /* data terminal ready */
 389#define SHADOW_RTS      0x02000000      /* request to send */
 390#define SHADOW_OUT1     0x04000000      /* 16550 OUT1 bit */
 391#define SHADOW_OUT2     0x08000000      /* 16550 OUT2 bit */
 392#define SHADOW_LOOP     0x10000000      /* loopback enabled */
 393
 394/* bitmasks for IOC3_SRTR_<A:B> */
 395#define SRTR_CNT        0x00000fff      /* reload value for RX timer */
 396#define SRTR_CNT_VAL    0x0fff0000      /* current value of RX timer */
 397#define SRTR_CNT_VAL_SHIFT 16
 398#define SRTR_HZ         16000   /* SRTR clock frequency */
 399
 400/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES  */
 401#define SIO_IR_SA_TX_MT         0x00000001      /* Serial port A TX empty */
 402#define SIO_IR_SA_RX_FULL       0x00000002      /* port A RX buf full */
 403#define SIO_IR_SA_RX_HIGH       0x00000004      /* port A RX hiwat */
 404#define SIO_IR_SA_RX_TIMER      0x00000008      /* port A RX timeout */
 405#define SIO_IR_SA_DELTA_DCD     0x00000010      /* port A delta DCD */
 406#define SIO_IR_SA_DELTA_CTS     0x00000020      /* port A delta CTS */
 407#define SIO_IR_SA_INT           0x00000040      /* port A pass-thru intr */
 408#define SIO_IR_SA_TX_EXPLICIT   0x00000080      /* port A explicit TX thru */
 409#define SIO_IR_SA_MEMERR        0x00000100      /* port A PCI error */
 410#define SIO_IR_SB_TX_MT         0x00000200      /* */
 411#define SIO_IR_SB_RX_FULL       0x00000400      /* */
 412#define SIO_IR_SB_RX_HIGH       0x00000800      /* */
 413#define SIO_IR_SB_RX_TIMER      0x00001000      /* */
 414#define SIO_IR_SB_DELTA_DCD     0x00002000      /* */
 415#define SIO_IR_SB_DELTA_CTS     0x00004000      /* */
 416#define SIO_IR_SB_INT           0x00008000      /* */
 417#define SIO_IR_SB_TX_EXPLICIT   0x00010000      /* */
 418#define SIO_IR_SB_MEMERR        0x00020000      /* */
 419#define SIO_IR_PP_INT           0x00040000      /* P port pass-thru intr */
 420#define SIO_IR_PP_INTA          0x00080000      /* PP context A thru */
 421#define SIO_IR_PP_INTB          0x00100000      /* PP context B thru */
 422#define SIO_IR_PP_MEMERR        0x00200000      /* PP PCI error */
 423#define SIO_IR_KBD_INT          0x00400000      /* kbd/mouse intr */
 424#define SIO_IR_RT_INT           0x08000000      /* RT output pulse */
 425#define SIO_IR_GEN_INT1         0x10000000      /* RT input pulse */
 426#define SIO_IR_GEN_INT_SHIFT    28
 427
 428/* per device interrupt masks */
 429#define SIO_IR_SA               (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
 430                                 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
 431                                 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
 432                                 SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
 433                                 SIO_IR_SA_MEMERR)
 434#define SIO_IR_SB               (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
 435                                 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
 436                                 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
 437                                 SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
 438                                 SIO_IR_SB_MEMERR)
 439#define SIO_IR_PP               (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
 440                                 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
 441#define SIO_IR_RT               (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
 442
 443/* macro to load pending interrupts */
 444#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
 445                                 PCI_INW(&((mem)->sio_ies_ro)))
 446
 447/* bitmasks for SIO_CR */
 448#define SIO_CR_SIO_RESET        0x00000001      /* reset the SIO */
 449#define SIO_CR_SER_A_BASE       0x000000fe      /* DMA poll addr port A */
 450#define SIO_CR_SER_A_BASE_SHIFT 1
 451#define SIO_CR_SER_B_BASE       0x00007f00      /* DMA poll addr port B */
 452#define SIO_CR_SER_B_BASE_SHIFT 8
 453#define SIO_SR_CMD_PULSE        0x00078000      /* byte bus strobe length */
 454#define SIO_CR_CMD_PULSE_SHIFT  15
 455#define SIO_CR_ARB_DIAG         0x00380000      /* cur !enet PCI requet (ro) */
 456#define SIO_CR_ARB_DIAG_TXA     0x00000000
 457#define SIO_CR_ARB_DIAG_RXA     0x00080000
 458#define SIO_CR_ARB_DIAG_TXB     0x00100000
 459#define SIO_CR_ARB_DIAG_RXB     0x00180000
 460#define SIO_CR_ARB_DIAG_PP      0x00200000
 461#define SIO_CR_ARB_DIAG_IDLE    0x00400000      /* 0 -> active request (ro) */
 462
 463/* bitmasks for INT_OUT */
 464#define INT_OUT_COUNT   0x0000ffff      /* pulse interval timer */
 465#define INT_OUT_MODE    0x00070000      /* mode mask */
 466#define INT_OUT_MODE_0  0x00000000      /* set output to 0 */
 467#define INT_OUT_MODE_1  0x00040000      /* set output to 1 */
 468#define INT_OUT_MODE_1PULSE 0x00050000  /* send 1 pulse */
 469#define INT_OUT_MODE_PULSES 0x00060000  /* send 1 pulse every interval */
 470#define INT_OUT_MODE_SQW 0x00070000     /* toggle output every interval */
 471#define INT_OUT_DIAG    0x40000000      /* diag mode */
 472#define INT_OUT_INT_OUT 0x80000000      /* current state of INT_OUT */
 473
 474/* time constants for INT_OUT */
 475#define INT_OUT_NS_PER_TICK (30 * 260)  /* 30 ns PCI clock, divisor=260 */
 476#define INT_OUT_TICKS_PER_PULSE 3       /* outgoing pulse lasts 3 ticks */
 477#define INT_OUT_US_TO_COUNT(x)          /* convert uS to a count value */ \
 478        (((x) * 10 + INT_OUT_NS_PER_TICK / 200) *       \
 479         100 / INT_OUT_NS_PER_TICK - 1)
 480#define INT_OUT_COUNT_TO_US(x)          /* convert count value to uS */ \
 481        (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
 482#define INT_OUT_MIN_TICKS 3     /* min period is width of pulse in "ticks" */
 483#define INT_OUT_MAX_TICKS INT_OUT_COUNT         /* largest possible count */
 484
 485/* bitmasks for GPCR */
 486#define GPCR_DIR        0x000000ff      /* tristate pin input or output */
 487#define GPCR_DIR_PIN(x) (1<<(x))        /* access one of the DIR bits */
 488#define GPCR_EDGE       0x000f0000      /* extint edge or level sensitive */
 489#define GPCR_EDGE_PIN(x) (1<<((x)+15))  /* access one of the EDGE bits */
 490
 491/* values for GPCR */
 492#define GPCR_INT_OUT_EN 0x00100000      /* enable INT_OUT to pin 0 */
 493#define GPCR_MLAN_EN    0x00200000      /* enable MCR to pin 8 */
 494#define GPCR_DIR_SERA_XCVR 0x00000080   /* Port A Transceiver select enable */
 495#define GPCR_DIR_SERB_XCVR 0x00000040   /* Port B Transceiver select enable */
 496#define GPCR_DIR_PHY_RST   0x00000020   /* ethernet PHY reset enable */
 497
 498/* defs for some of the generic I/O pins */
 499#define GPCR_PHY_RESET          0x20    /* pin is output to PHY reset */
 500#define GPCR_UARTB_MODESEL      0x40    /* pin is output to port B mode sel */
 501#define GPCR_UARTA_MODESEL      0x80    /* pin is output to port A mode sel */
 502
 503#define GPPR_PHY_RESET_PIN      5       /* GIO pin controlling phy reset */
 504#define GPPR_UARTB_MODESEL_PIN  6       /* GIO pin controlling uart b mode select */
 505#define GPPR_UARTA_MODESEL_PIN  7       /* GIO pin controlling uart a mode select */
 506
 507#define EMCR_DUPLEX             0x00000001
 508#define EMCR_PROMISC            0x00000002
 509#define EMCR_PADEN              0x00000004
 510#define EMCR_RXOFF_MASK         0x000001f8
 511#define EMCR_RXOFF_SHIFT        3
 512#define EMCR_RAMPAR             0x00000200
 513#define EMCR_BADPAR             0x00000800
 514#define EMCR_BUFSIZ             0x00001000
 515#define EMCR_TXDMAEN            0x00002000
 516#define EMCR_TXEN               0x00004000
 517#define EMCR_RXDMAEN            0x00008000
 518#define EMCR_RXEN               0x00010000
 519#define EMCR_LOOPBACK           0x00020000
 520#define EMCR_ARB_DIAG           0x001c0000
 521#define EMCR_ARB_DIAG_IDLE      0x00200000
 522#define EMCR_RST                0x80000000
 523
 524#define EISR_RXTIMERINT         0x00000001
 525#define EISR_RXTHRESHINT        0x00000002
 526#define EISR_RXOFLO             0x00000004
 527#define EISR_RXBUFOFLO          0x00000008
 528#define EISR_RXMEMERR           0x00000010
 529#define EISR_RXPARERR           0x00000020
 530#define EISR_TXEMPTY            0x00010000
 531#define EISR_TXRTRY             0x00020000
 532#define EISR_TXEXDEF            0x00040000
 533#define EISR_TXLCOL             0x00080000
 534#define EISR_TXGIANT            0x00100000
 535#define EISR_TXBUFUFLO          0x00200000
 536#define EISR_TXEXPLICIT         0x00400000
 537#define EISR_TXCOLLWRAP         0x00800000
 538#define EISR_TXDEFERWRAP        0x01000000
 539#define EISR_TXMEMERR           0x02000000
 540#define EISR_TXPARERR           0x04000000
 541
 542#define ERCSR_THRESH_MASK       0x000001ff      /* enet RX threshold */
 543#define ERCSR_RX_TMR            0x40000000      /* simulation only */
 544#define ERCSR_DIAG_OFLO         0x80000000      /* simulation only */
 545
 546#define ERBR_ALIGNMENT          4096
 547#define ERBR_L_RXRINGBASE_MASK  0xfffff000
 548
 549#define ERBAR_BARRIER_BIT       0x0100
 550#define ERBAR_RXBARR_MASK       0xffff0000
 551#define ERBAR_RXBARR_SHIFT      16
 552
 553#define ERCIR_RXCONSUME_MASK    0x00000fff
 554
 555#define ERPIR_RXPRODUCE_MASK    0x00000fff
 556#define ERPIR_ARM               0x80000000
 557
 558#define ERTR_CNT_MASK           0x000007ff
 559
 560#define ETCSR_IPGT_MASK         0x0000007f
 561#define ETCSR_IPGR1_MASK        0x00007f00
 562#define ETCSR_IPGR1_SHIFT       8
 563#define ETCSR_IPGR2_MASK        0x007f0000
 564#define ETCSR_IPGR2_SHIFT       16
 565#define ETCSR_NOTXCLK           0x80000000
 566
 567#define ETCDC_COLLCNT_MASK      0x0000ffff
 568#define ETCDC_DEFERCNT_MASK     0xffff0000
 569#define ETCDC_DEFERCNT_SHIFT    16
 570
 571#define ETBR_ALIGNMENT          (64*1024)
 572#define ETBR_L_RINGSZ_MASK      0x00000001
 573#define ETBR_L_RINGSZ128        0
 574#define ETBR_L_RINGSZ512        1
 575#define ETBR_L_TXRINGBASE_MASK  0xffffc000
 576
 577#define ETCIR_TXCONSUME_MASK    0x0000ffff
 578#define ETCIR_IDLE              0x80000000
 579
 580#define ETPIR_TXPRODUCE_MASK    0x0000ffff
 581
 582#define EBIR_TXBUFPROD_MASK     0x0000001f
 583#define EBIR_TXBUFCONS_MASK     0x00001f00
 584#define EBIR_TXBUFCONS_SHIFT    8
 585#define EBIR_RXBUFPROD_MASK     0x007fc000
 586#define EBIR_RXBUFPROD_SHIFT    14
 587#define EBIR_RXBUFCONS_MASK     0xff800000
 588#define EBIR_RXBUFCONS_SHIFT    23
 589
 590#define MICR_REGADDR_MASK       0x0000001f
 591#define MICR_PHYADDR_MASK       0x000003e0
 592#define MICR_PHYADDR_SHIFT      5
 593#define MICR_READTRIG           0x00000400
 594#define MICR_BUSY               0x00000800
 595
 596#define MIDR_DATA_MASK          0x0000ffff
 597
 598#define ERXBUF_IPCKSUM_MASK     0x0000ffff
 599#define ERXBUF_BYTECNT_MASK     0x07ff0000
 600#define ERXBUF_BYTECNT_SHIFT    16
 601#define ERXBUF_V                0x80000000
 602
 603#define ERXBUF_CRCERR           0x00000001      /* aka RSV15 */
 604#define ERXBUF_FRAMERR          0x00000002      /* aka RSV14 */
 605#define ERXBUF_CODERR           0x00000004      /* aka RSV13 */
 606#define ERXBUF_INVPREAMB        0x00000008      /* aka RSV18 */
 607#define ERXBUF_LOLEN            0x00007000      /* aka RSV2_0 */
 608#define ERXBUF_HILEN            0x03ff0000      /* aka RSV12_3 */
 609#define ERXBUF_MULTICAST        0x04000000      /* aka RSV16 */
 610#define ERXBUF_BROADCAST        0x08000000      /* aka RSV17 */
 611#define ERXBUF_LONGEVENT        0x10000000      /* aka RSV19 */
 612#define ERXBUF_BADPKT           0x20000000      /* aka RSV20 */
 613#define ERXBUF_GOODPKT          0x40000000      /* aka RSV21 */
 614#define ERXBUF_CARRIER          0x80000000      /* aka RSV22 */
 615
 616#define ETXD_BYTECNT_MASK       0x000007ff      /* total byte count */
 617#define ETXD_INTWHENDONE        0x00001000      /* intr when done */
 618#define ETXD_D0V                0x00010000      /* data 0 valid */
 619#define ETXD_B1V                0x00020000      /* buf 1 valid */
 620#define ETXD_B2V                0x00040000      /* buf 2 valid */
 621#define ETXD_DOCHECKSUM         0x00080000      /* insert ip cksum */
 622#define ETXD_CHKOFF_MASK        0x07f00000      /* cksum byte offset */
 623#define ETXD_CHKOFF_SHIFT       20
 624
 625#define ETXD_D0CNT_MASK         0x0000007f
 626#define ETXD_B1CNT_MASK         0x0007ff00
 627#define ETXD_B1CNT_SHIFT        8
 628#define ETXD_B2CNT_MASK         0x7ff00000
 629#define ETXD_B2CNT_SHIFT        20
 630
 631typedef enum ioc3_subdevs_e {
 632    ioc3_subdev_ether,
 633    ioc3_subdev_generic,
 634    ioc3_subdev_nic,
 635    ioc3_subdev_kbms,
 636    ioc3_subdev_ttya,
 637    ioc3_subdev_ttyb,
 638    ioc3_subdev_ecpp,
 639    ioc3_subdev_rt,
 640    ioc3_nsubdevs
 641} ioc3_subdev_t;
 642
 643/* subdevice disable bits,
 644 * from the standard INFO_LBL_SUBDEVS
 645 */
 646#define IOC3_SDB_ETHER          (1<<ioc3_subdev_ether)
 647#define IOC3_SDB_GENERIC        (1<<ioc3_subdev_generic)
 648#define IOC3_SDB_NIC            (1<<ioc3_subdev_nic)
 649#define IOC3_SDB_KBMS           (1<<ioc3_subdev_kbms)
 650#define IOC3_SDB_TTYA           (1<<ioc3_subdev_ttya)
 651#define IOC3_SDB_TTYB           (1<<ioc3_subdev_ttyb)
 652#define IOC3_SDB_ECPP           (1<<ioc3_subdev_ecpp)
 653#define IOC3_SDB_RT             (1<<ioc3_subdev_rt)
 654
 655#define IOC3_ALL_SUBDEVS        ((1<<ioc3_nsubdevs)-1)
 656
 657#define IOC3_SDB_SERIAL         (IOC3_SDB_TTYA|IOC3_SDB_TTYB)
 658
 659#define IOC3_STD_SUBDEVS        IOC3_ALL_SUBDEVS
 660
 661#define IOC3_INTA_SUBDEVS       IOC3_SDB_ETHER
 662#define IOC3_INTB_SUBDEVS       (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)
 663
 664#endif /* _IOC3_H */
 665