LXR linux/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h

   1/* MN103E010 on-board DMA controller registers
   2 *
   3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
   4 * Written by David Howells (dhowells@redhat.com)
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public Licence
   8 * as published by the Free Software Foundation; either version
   9 * 2 of the Licence, or (at your option) any later version.
  10 */
  11
  12#ifndef _ASM_PROC_DMACTL_REGS_H
  13#define _ASM_PROC_DMACTL_REGS_H
  14
  15#include <asm/cpu-regs.h>
  16
  17#ifdef __KERNEL__
  18
  19/* DMA registers */
  20#define DMxCTR(N)               __SYSREG(0xd2000000 + ((N) * 0x100), u32)       /* control reg */
  21#define DMxCTR_BG               0x0000001f      /* transfer request source */
  22#define DMxCTR_BG_SOFT          0x00000000      /* - software source */
  23#define DMxCTR_BG_SC0TX         0x00000002      /* - serial port 0 transmission */
  24#define DMxCTR_BG_SC0RX         0x00000003      /* - serial port 0 reception */
  25#define DMxCTR_BG_SC1TX         0x00000004      /* - serial port 1 transmission */
  26#define DMxCTR_BG_SC1RX         0x00000005      /* - serial port 1 reception */
  27#define DMxCTR_BG_SC2TX         0x00000006      /* - serial port 2 transmission */
  28#define DMxCTR_BG_SC2RX         0x00000007      /* - serial port 2 reception */
  29#define DMxCTR_BG_TM0UFLOW      0x00000008      /* - timer 0 underflow */
  30#define DMxCTR_BG_TM1UFLOW      0x00000009      /* - timer 1 underflow */
  31#define DMxCTR_BG_TM2UFLOW      0x0000000a      /* - timer 2 underflow */
  32#define DMxCTR_BG_TM3UFLOW      0x0000000b      /* - timer 3 underflow */
  33#define DMxCTR_BG_TM6ACMPCAP    0x0000000c      /* - timer 6A compare/capture */
  34#define DMxCTR_BG_AFE           0x0000000d      /* - analogue front-end interrupt source */
  35#define DMxCTR_BG_ADC           0x0000000e      /* - A/D conversion end interrupt source */
  36#define DMxCTR_BG_IRDA          0x0000000f      /* - IrDA interrupt source */
  37#define DMxCTR_BG_RTC           0x00000010      /* - RTC interrupt source */
  38#define DMxCTR_BG_XIRQ0         0x00000011      /* - XIRQ0 pin interrupt source */
  39#define DMxCTR_BG_XIRQ1         0x00000012      /* - XIRQ1 pin interrupt source */
  40#define DMxCTR_BG_XDMR0         0x00000013      /* - external request 0 source (XDMR0 pin) */
  41#define DMxCTR_BG_XDMR1         0x00000014      /* - external request 1 source (XDMR1 pin) */
  42#define DMxCTR_SAM              0x000000e0      /* DMA transfer src addr mode */
  43#define DMxCTR_SAM_INCR         0x00000000      /* - increment */
  44#define DMxCTR_SAM_DECR         0x00000020      /* - decrement */
  45#define DMxCTR_SAM_FIXED        0x00000040      /* - fixed */
  46#define DMxCTR_DAM              0x00000000      /* DMA transfer dest addr mode */
  47#define DMxCTR_DAM_INCR         0x00000000      /* - increment */
  48#define DMxCTR_DAM_DECR         0x00000100      /* - decrement */
  49#define DMxCTR_DAM_FIXED        0x00000200      /* - fixed */
  50#define DMxCTR_TM               0x00001800      /* DMA transfer mode */
  51#define DMxCTR_TM_BATCH         0x00000000      /* - batch transfer */
  52#define DMxCTR_TM_INTERM        0x00001000      /* - intermittent transfer */
  53#define DMxCTR_UT               0x00006000      /* DMA transfer unit */
  54#define DMxCTR_UT_1             0x00000000      /* - 1 byte */
  55#define DMxCTR_UT_2             0x00002000      /* - 2 byte */
  56#define DMxCTR_UT_4             0x00004000      /* - 4 byte */
  57#define DMxCTR_UT_16            0x00006000      /* - 16 byte */
  58#define DMxCTR_TEN              0x00010000      /* DMA channel transfer enable */
  59#define DMxCTR_RQM              0x00060000      /* external request input source mode */
  60#define DMxCTR_RQM_FALLEDGE     0x00000000      /* - falling edge */
  61#define DMxCTR_RQM_RISEEDGE     0x00020000      /* - rising edge */
  62#define DMxCTR_RQM_LOLEVEL      0x00040000      /* - low level */
  63#define DMxCTR_RQM_HILEVEL      0x00060000      /* - high level */
  64#define DMxCTR_RQF              0x01000000      /* DMA transfer request flag */
  65#define DMxCTR_XEND             0x80000000      /* DMA transfer end flag */
  66
  67#define DMxSRC(N)               __SYSREG(0xd2000004 + ((N) * 0x100), u32)       /* control reg */
  68
  69#define DMxDST(N)               __SYSREG(0xd2000008 + ((N) * 0x100), u32)       /* src addr reg */
  70
  71#define DMxSIZ(N)               __SYSREG(0xd200000c + ((N) * 0x100), u32)       /* dest addr reg */
  72#define DMxSIZ_CT               0x000fffff      /* number of bytes to transfer */
  73
  74#define DMxCYC(N)               __SYSREG(0xd2000010 + ((N) * 0x100), u32)       /* intermittent
  75                                                                                 * size reg */
  76#define DMxCYC_CYC              0x000000ff      /* number of interrmittent transfers -1 */
  77
  78#define DM0IRQ                  16              /* DMA channel 0 complete IRQ */
  79#define DM1IRQ                  17              /* DMA channel 1 complete IRQ */
  80#define DM2IRQ                  18              /* DMA channel 2 complete IRQ */
  81#define DM3IRQ                  19              /* DMA channel 3 complete IRQ */
  82
  83#define DM0ICR                  GxICR(DM0IRQ)   /* DMA channel 0 complete intr ctrl reg */
  84#define DM1ICR                  GxICR(DM0IR1)   /* DMA channel 1 complete intr ctrl reg */
  85#define DM2ICR                  GxICR(DM0IR2)   /* DMA channel 2 complete intr ctrl reg */
  86#define DM3ICR                  GxICR(DM0IR3)   /* DMA channel 3 complete intr ctrl reg */
  87
  88#ifndef __ASSEMBLY__
  89
  90struct mn10300_dmactl_regs {
  91        u32             ctr;
  92        const void      *src;
  93        void            *dst;
  94        u32             siz;
  95        u32             cyc;
  96} __attribute__((aligned(0x100)));
  97
  98#endif /* __ASSEMBLY__ */
  99
 100#endif /* __KERNEL__ */
 101
 102#endif /* _ASM_PROC_DMACTL_REGS_H */
 103