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22#include <linux/dma-mapping.h>
23#include <linux/dma-debug.h>
24#include <linux/export.h>
25
26#include <asm/cpuinfo.h>
27#include <asm/spr_defs.h>
28#include <asm/tlbflush.h>
29
30static int
31page_set_nocache(pte_t *pte, unsigned long addr,
32 unsigned long next, struct mm_walk *walk)
33{
34 unsigned long cl;
35 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
36
37 pte_val(*pte) |= _PAGE_CI;
38
39
40
41
42
43 flush_tlb_page(NULL, addr);
44
45
46 for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size)
47 mtspr(SPR_DCBFR, cl);
48
49 return 0;
50}
51
52static int
53page_clear_nocache(pte_t *pte, unsigned long addr,
54 unsigned long next, struct mm_walk *walk)
55{
56 pte_val(*pte) &= ~_PAGE_CI;
57
58
59
60
61
62 flush_tlb_page(NULL, addr);
63
64 return 0;
65}
66
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81
82
83static void *
84or1k_dma_alloc(struct device *dev, size_t size,
85 dma_addr_t *dma_handle, gfp_t gfp,
86 unsigned long attrs)
87{
88 unsigned long va;
89 void *page;
90 struct mm_walk walk = {
91 .pte_entry = page_set_nocache,
92 .mm = &init_mm
93 };
94
95 page = alloc_pages_exact(size, gfp);
96 if (!page)
97 return NULL;
98
99
100 *dma_handle = __pa(page);
101
102 va = (unsigned long)page;
103
104 if ((attrs & DMA_ATTR_NON_CONSISTENT) == 0) {
105
106
107
108
109 if (walk_page_range(va, va + size, &walk)) {
110 free_pages_exact(page, size);
111 return NULL;
112 }
113 }
114
115 return (void *)va;
116}
117
118static void
119or1k_dma_free(struct device *dev, size_t size, void *vaddr,
120 dma_addr_t dma_handle, unsigned long attrs)
121{
122 unsigned long va = (unsigned long)vaddr;
123 struct mm_walk walk = {
124 .pte_entry = page_clear_nocache,
125 .mm = &init_mm
126 };
127
128 if ((attrs & DMA_ATTR_NON_CONSISTENT) == 0) {
129
130 WARN_ON(walk_page_range(va, va + size, &walk));
131 }
132
133 free_pages_exact(vaddr, size);
134}
135
136static dma_addr_t
137or1k_map_page(struct device *dev, struct page *page,
138 unsigned long offset, size_t size,
139 enum dma_data_direction dir,
140 unsigned long attrs)
141{
142 unsigned long cl;
143 dma_addr_t addr = page_to_phys(page) + offset;
144 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
145
146 if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
147 return addr;
148
149 switch (dir) {
150 case DMA_TO_DEVICE:
151
152 for (cl = addr; cl < addr + size;
153 cl += cpuinfo->dcache_block_size)
154 mtspr(SPR_DCBFR, cl);
155 break;
156 case DMA_FROM_DEVICE:
157
158 for (cl = addr; cl < addr + size;
159 cl += cpuinfo->dcache_block_size)
160 mtspr(SPR_DCBIR, cl);
161 break;
162 default:
163
164
165
166
167
168 break;
169 }
170
171 return addr;
172}
173
174static void
175or1k_unmap_page(struct device *dev, dma_addr_t dma_handle,
176 size_t size, enum dma_data_direction dir,
177 unsigned long attrs)
178{
179
180}
181
182static int
183or1k_map_sg(struct device *dev, struct scatterlist *sg,
184 int nents, enum dma_data_direction dir,
185 unsigned long attrs)
186{
187 struct scatterlist *s;
188 int i;
189
190 for_each_sg(sg, s, nents, i) {
191 s->dma_address = or1k_map_page(dev, sg_page(s), s->offset,
192 s->length, dir, 0);
193 }
194
195 return nents;
196}
197
198static void
199or1k_unmap_sg(struct device *dev, struct scatterlist *sg,
200 int nents, enum dma_data_direction dir,
201 unsigned long attrs)
202{
203 struct scatterlist *s;
204 int i;
205
206 for_each_sg(sg, s, nents, i) {
207 or1k_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, 0);
208 }
209}
210
211static void
212or1k_sync_single_for_cpu(struct device *dev,
213 dma_addr_t dma_handle, size_t size,
214 enum dma_data_direction dir)
215{
216 unsigned long cl;
217 dma_addr_t addr = dma_handle;
218 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
219
220
221 for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size)
222 mtspr(SPR_DCBIR, cl);
223}
224
225static void
226or1k_sync_single_for_device(struct device *dev,
227 dma_addr_t dma_handle, size_t size,
228 enum dma_data_direction dir)
229{
230 unsigned long cl;
231 dma_addr_t addr = dma_handle;
232 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
233
234
235 for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size)
236 mtspr(SPR_DCBFR, cl);
237}
238
239const struct dma_map_ops or1k_dma_map_ops = {
240 .alloc = or1k_dma_alloc,
241 .free = or1k_dma_free,
242 .map_page = or1k_map_page,
243 .unmap_page = or1k_unmap_page,
244 .map_sg = or1k_map_sg,
245 .unmap_sg = or1k_unmap_sg,
246 .sync_single_for_cpu = or1k_sync_single_for_cpu,
247 .sync_single_for_device = or1k_sync_single_for_device,
248};
249EXPORT_SYMBOL(or1k_dma_map_ops);
250
251
252#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
253
254static int __init dma_init(void)
255{
256 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
257
258 return 0;
259}
260fs_initcall(dma_init);
261