linux/arch/parisc/kernel/time.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *  linux/arch/parisc/kernel/time.c
   4 *
   5 *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
   6 *  Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King
   7 *  Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org)
   8 *
   9 * 1994-07-02  Alan Modra
  10 *             fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
  11 * 1998-12-20  Updated NTP code according to technical memorandum Jan '96
  12 *             "A Kernel Model for Precision Timekeeping" by Dave Mills
  13 */
  14#include <linux/errno.h>
  15#include <linux/module.h>
  16#include <linux/rtc.h>
  17#include <linux/sched.h>
  18#include <linux/sched/clock.h>
  19#include <linux/sched_clock.h>
  20#include <linux/kernel.h>
  21#include <linux/param.h>
  22#include <linux/string.h>
  23#include <linux/mm.h>
  24#include <linux/interrupt.h>
  25#include <linux/time.h>
  26#include <linux/init.h>
  27#include <linux/smp.h>
  28#include <linux/profile.h>
  29#include <linux/clocksource.h>
  30#include <linux/platform_device.h>
  31#include <linux/ftrace.h>
  32
  33#include <linux/uaccess.h>
  34#include <asm/io.h>
  35#include <asm/irq.h>
  36#include <asm/page.h>
  37#include <asm/param.h>
  38#include <asm/pdc.h>
  39#include <asm/led.h>
  40
  41#include <linux/timex.h>
  42
  43static unsigned long clocktick __read_mostly;   /* timer cycles per tick */
  44
  45/*
  46 * We keep time on PA-RISC Linux by using the Interval Timer which is
  47 * a pair of registers; one is read-only and one is write-only; both
  48 * accessed through CR16.  The read-only register is 32 or 64 bits wide,
  49 * and increments by 1 every CPU clock tick.  The architecture only
  50 * guarantees us a rate between 0.5 and 2, but all implementations use a
  51 * rate of 1.  The write-only register is 32-bits wide.  When the lowest
  52 * 32 bits of the read-only register compare equal to the write-only
  53 * register, it raises a maskable external interrupt.  Each processor has
  54 * an Interval Timer of its own and they are not synchronised.  
  55 *
  56 * We want to generate an interrupt every 1/HZ seconds.  So we program
  57 * CR16 to interrupt every @clocktick cycles.  The it_value in cpu_data
  58 * is programmed with the intended time of the next tick.  We can be
  59 * held off for an arbitrarily long period of time by interrupts being
  60 * disabled, so we may miss one or more ticks.
  61 */
  62irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
  63{
  64        unsigned long now;
  65        unsigned long next_tick;
  66        unsigned long ticks_elapsed = 0;
  67        unsigned int cpu = smp_processor_id();
  68        struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
  69
  70        /* gcc can optimize for "read-only" case with a local clocktick */
  71        unsigned long cpt = clocktick;
  72
  73        profile_tick(CPU_PROFILING);
  74
  75        /* Initialize next_tick to the old expected tick time. */
  76        next_tick = cpuinfo->it_value;
  77
  78        /* Calculate how many ticks have elapsed. */
  79        now = mfctl(16);
  80        do {
  81                ++ticks_elapsed;
  82                next_tick += cpt;
  83        } while (next_tick - now > cpt);
  84
  85        /* Store (in CR16 cycles) up to when we are accounting right now. */
  86        cpuinfo->it_value = next_tick;
  87
  88        /* Go do system house keeping. */
  89        if (cpu == 0)
  90                xtime_update(ticks_elapsed);
  91
  92        update_process_times(user_mode(get_irq_regs()));
  93
  94        /* Skip clockticks on purpose if we know we would miss those.
  95         * The new CR16 must be "later" than current CR16 otherwise
  96         * itimer would not fire until CR16 wrapped - e.g 4 seconds
  97         * later on a 1Ghz processor. We'll account for the missed
  98         * ticks on the next timer interrupt.
  99         * We want IT to fire modulo clocktick even if we miss/skip some.
 100         * But those interrupts don't in fact get delivered that regularly.
 101         *
 102         * "next_tick - now" will always give the difference regardless
 103         * if one or the other wrapped. If "now" is "bigger" we'll end up
 104         * with a very large unsigned number.
 105         */
 106        now = mfctl(16);
 107        while (next_tick - now > cpt)
 108                next_tick += cpt;
 109
 110        /* Program the IT when to deliver the next interrupt.
 111         * Only bottom 32-bits of next_tick are writable in CR16!
 112         * Timer interrupt will be delivered at least a few hundred cycles
 113         * after the IT fires, so if we are too close (<= 8000 cycles) to the
 114         * next cycle, simply skip it.
 115         */
 116        if (next_tick - now <= 8000)
 117                next_tick += cpt;
 118        mtctl(next_tick, 16);
 119
 120        return IRQ_HANDLED;
 121}
 122
 123
 124unsigned long profile_pc(struct pt_regs *regs)
 125{
 126        unsigned long pc = instruction_pointer(regs);
 127
 128        if (regs->gr[0] & PSW_N)
 129                pc -= 4;
 130
 131#ifdef CONFIG_SMP
 132        if (in_lock_functions(pc))
 133                pc = regs->gr[2];
 134#endif
 135
 136        return pc;
 137}
 138EXPORT_SYMBOL(profile_pc);
 139
 140
 141/* clock source code */
 142
 143static u64 notrace read_cr16(struct clocksource *cs)
 144{
 145        return get_cycles();
 146}
 147
 148static struct clocksource clocksource_cr16 = {
 149        .name                   = "cr16",
 150        .rating                 = 300,
 151        .read                   = read_cr16,
 152        .mask                   = CLOCKSOURCE_MASK(BITS_PER_LONG),
 153        .flags                  = CLOCK_SOURCE_IS_CONTINUOUS,
 154};
 155
 156void __init start_cpu_itimer(void)
 157{
 158        unsigned int cpu = smp_processor_id();
 159        unsigned long next_tick = mfctl(16) + clocktick;
 160
 161        mtctl(next_tick, 16);           /* kick off Interval Timer (CR16) */
 162
 163        per_cpu(cpu_data, cpu).it_value = next_tick;
 164}
 165
 166#if IS_ENABLED(CONFIG_RTC_DRV_GENERIC)
 167static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm)
 168{
 169        struct pdc_tod tod_data;
 170
 171        memset(tm, 0, sizeof(*tm));
 172        if (pdc_tod_read(&tod_data) < 0)
 173                return -EOPNOTSUPP;
 174
 175        /* we treat tod_sec as unsigned, so this can work until year 2106 */
 176        rtc_time64_to_tm(tod_data.tod_sec, tm);
 177        return rtc_valid_tm(tm);
 178}
 179
 180static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm)
 181{
 182        time64_t secs = rtc_tm_to_time64(tm);
 183
 184        if (pdc_tod_set(secs, 0) < 0)
 185                return -EOPNOTSUPP;
 186
 187        return 0;
 188}
 189
 190static const struct rtc_class_ops rtc_generic_ops = {
 191        .read_time = rtc_generic_get_time,
 192        .set_time = rtc_generic_set_time,
 193};
 194
 195static int __init rtc_init(void)
 196{
 197        struct platform_device *pdev;
 198
 199        pdev = platform_device_register_data(NULL, "rtc-generic", -1,
 200                                             &rtc_generic_ops,
 201                                             sizeof(rtc_generic_ops));
 202
 203        return PTR_ERR_OR_ZERO(pdev);
 204}
 205device_initcall(rtc_init);
 206#endif
 207
 208void read_persistent_clock(struct timespec *ts)
 209{
 210        static struct pdc_tod tod_data;
 211        if (pdc_tod_read(&tod_data) == 0) {
 212                ts->tv_sec = tod_data.tod_sec;
 213                ts->tv_nsec = tod_data.tod_usec * 1000;
 214        } else {
 215                printk(KERN_ERR "Error reading tod clock\n");
 216                ts->tv_sec = 0;
 217                ts->tv_nsec = 0;
 218        }
 219}
 220
 221
 222static u64 notrace read_cr16_sched_clock(void)
 223{
 224        return get_cycles();
 225}
 226
 227
 228/*
 229 * timer interrupt and sched_clock() initialization
 230 */
 231
 232void __init time_init(void)
 233{
 234        unsigned long cr16_hz;
 235
 236        clocktick = (100 * PAGE0->mem_10msec) / HZ;
 237        start_cpu_itimer();     /* get CPU 0 started */
 238
 239        cr16_hz = 100 * PAGE0->mem_10msec;  /* Hz */
 240
 241        /* register as sched_clock source */
 242        sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz);
 243}
 244
 245static int __init init_cr16_clocksource(void)
 246{
 247        /*
 248         * The cr16 interval timers are not syncronized across CPUs on
 249         * different sockets, so mark them unstable and lower rating on
 250         * multi-socket SMP systems.
 251         */
 252        if (num_online_cpus() > 1 && !running_on_qemu) {
 253                int cpu;
 254                unsigned long cpu0_loc;
 255                cpu0_loc = per_cpu(cpu_data, 0).cpu_loc;
 256
 257                for_each_online_cpu(cpu) {
 258                        if (cpu == 0)
 259                                continue;
 260                        if ((cpu0_loc != 0) &&
 261                            (cpu0_loc == per_cpu(cpu_data, cpu).cpu_loc))
 262                                continue;
 263
 264                        clocksource_cr16.name = "cr16_unstable";
 265                        clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
 266                        clocksource_cr16.rating = 0;
 267                        break;
 268                }
 269        }
 270
 271        /* XXX: We may want to mark sched_clock stable here if cr16 clocks are
 272         *      in sync:
 273         *      (clocksource_cr16.flags == CLOCK_SOURCE_IS_CONTINUOUS) */
 274
 275        /* register at clocksource framework */
 276        clocksource_register_hz(&clocksource_cr16,
 277                100 * PAGE0->mem_10msec);
 278
 279        return 0;
 280}
 281
 282device_initcall(init_cr16_clocksource);
 283