1/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2/* 3 * Copyright (C) 2001 PPC64 Team, IBM Corp 4 * 5 * This struct defines the way the registers are stored on the 6 * kernel stack during a system call or other kernel entry. 7 * 8 * this should only contain volatile regs 9 * since we can keep non-volatile in the thread_struct 10 * should set this up when only volatiles are saved 11 * by intr code. 12 * 13 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure 14 * that the overall structure is a multiple of 16 bytes in length. 15 * 16 * Note that the offsets of the fields in this struct correspond with 17 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24#ifndef _UAPI_ASM_POWERPC_PTRACE_H 25#define _UAPI_ASM_POWERPC_PTRACE_H 26 27 28#include <linux/types.h> 29 30#ifndef __ASSEMBLY__ 31 32struct pt_regs { 33 unsigned long gpr[32]; 34 unsigned long nip; 35 unsigned long msr; 36 unsigned long orig_gpr3; /* Used for restarting system calls */ 37 unsigned long ctr; 38 unsigned long link; 39 unsigned long xer; 40 unsigned long ccr; 41#ifdef __powerpc64__ 42 unsigned long softe; /* Soft enabled/disabled */ 43#else 44 unsigned long mq; /* 601 only (not used at present) */ 45 /* Used on APUS to hold IPL value. */ 46#endif 47 unsigned long trap; /* Reason for being here */ 48 /* N.B. for critical exceptions on 4xx, the dar and dsisr 49 fields are overloaded to hold srr0 and srr1. */ 50 unsigned long dar; /* Fault registers */ 51 unsigned long dsisr; /* on 4xx/Book-E used for ESR */ 52 unsigned long result; /* Result of a system call */ 53}; 54 55#endif /* __ASSEMBLY__ */ 56 57 58/* 59 * Offsets used by 'ptrace' system call interface. 60 * These can't be changed without breaking binary compatibility 61 * with MkLinux, etc. 62 */ 63#define PT_R0 0 64#define PT_R1 1 65#define PT_R2 2 66#define PT_R3 3 67#define PT_R4 4 68#define PT_R5 5 69#define PT_R6 6 70#define PT_R7 7 71#define PT_R8 8 72#define PT_R9 9 73#define PT_R10 10 74#define PT_R11 11 75#define PT_R12 12 76#define PT_R13 13 77#define PT_R14 14 78#define PT_R15 15 79#define PT_R16 16 80#define PT_R17 17 81#define PT_R18 18 82#define PT_R19 19 83#define PT_R20 20 84#define PT_R21 21 85#define PT_R22 22 86#define PT_R23 23 87#define PT_R24 24 88#define PT_R25 25 89#define PT_R26 26 90#define PT_R27 27 91#define PT_R28 28 92#define PT_R29 29 93#define PT_R30 30 94#define PT_R31 31 95 96#define PT_NIP 32 97#define PT_MSR 33 98#define PT_ORIG_R3 34 99#define PT_CTR 35 100#define PT_LNK 36 101#define PT_XER 37 102#define PT_CCR 38 103#ifndef __powerpc64__ 104#define PT_MQ 39 105#else 106#define PT_SOFTE 39 107#endif 108#define PT_TRAP 40 109#define PT_DAR 41 110#define PT_DSISR 42 111#define PT_RESULT 43 112#define PT_DSCR 44 113#define PT_REGS_COUNT 44 114 115#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ 116 117#ifndef __powerpc64__ 118 119#define PT_FPR31 (PT_FPR0 + 2*31) 120#define PT_FPSCR (PT_FPR0 + 2*32 + 1) 121 122#else /* __powerpc64__ */ 123 124#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */ 125 126 127#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */ 128#define PT_VSCR (PT_VR0 + 32*2 + 1) 129#define PT_VRSAVE (PT_VR0 + 33*2) 130 131 132/* 133 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31 134 */ 135#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */ 136#define PT_VSR31 (PT_VSR0 + 2*31) 137#endif /* __powerpc64__ */ 138 139/* 140 * Get/set all the altivec registers v0..v31, vscr, vrsave, in one go. 141 * The transfer totals 34 quadword. Quadwords 0-31 contain the 142 * corresponding vector registers. Quadword 32 contains the vscr as the 143 * last word (offset 12) within that quadword. Quadword 33 contains the 144 * vrsave as the first word (offset 0) within the quadword. 145 * 146 * This definition of the VMX state is compatible with the current PPC32 147 * ptrace interface. This allows signal handling and ptrace to use the same 148 * structures. This also simplifies the implementation of a bi-arch 149 * (combined (32- and 64-bit) gdb. 150 */ 151#define PTRACE_GETVRREGS 0x12 152#define PTRACE_SETVRREGS 0x13 153 154/* Get/set all the upper 32-bits of the SPE registers, accumulator, and 155 * spefscr, in one go */ 156#define PTRACE_GETEVRREGS 0x14 157#define PTRACE_SETEVRREGS 0x15 158 159/* Get the first 32 128bit VSX registers */ 160#define PTRACE_GETVSRREGS 0x1b 161#define PTRACE_SETVSRREGS 0x1c 162 163/* 164 * Get or set a debug register. The first 16 are DABR registers and the 165 * second 16 are IABR registers. 166 */ 167#define PTRACE_GET_DEBUGREG 0x19 168#define PTRACE_SET_DEBUGREG 0x1a 169 170/* (new) PTRACE requests using the same numbers as x86 and the same 171 * argument ordering. Additionally, they support more registers too 172 */ 173#define PTRACE_GETREGS 0xc 174#define PTRACE_SETREGS 0xd 175#define PTRACE_GETFPREGS 0xe 176#define PTRACE_SETFPREGS 0xf 177#define PTRACE_GETREGS64 0x16 178#define PTRACE_SETREGS64 0x17 179 180/* Calls to trace a 64bit program from a 32bit program */ 181#define PPC_PTRACE_PEEKTEXT_3264 0x95 182#define PPC_PTRACE_PEEKDATA_3264 0x94 183#define PPC_PTRACE_POKETEXT_3264 0x93 184#define PPC_PTRACE_POKEDATA_3264 0x92 185#define PPC_PTRACE_PEEKUSR_3264 0x91 186#define PPC_PTRACE_POKEUSR_3264 0x90 187 188#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ 189 190#define PPC_PTRACE_GETHWDBGINFO 0x89 191#define PPC_PTRACE_SETHWDEBUG 0x88 192#define PPC_PTRACE_DELHWDEBUG 0x87 193 194#ifndef __ASSEMBLY__ 195 196struct ppc_debug_info { 197 __u32 version; /* Only version 1 exists to date */ 198 __u32 num_instruction_bps; 199 __u32 num_data_bps; 200 __u32 num_condition_regs; 201 __u32 data_bp_alignment; 202 __u32 sizeof_condition; /* size of the DVC register */ 203 __u64 features; 204}; 205 206#endif /* __ASSEMBLY__ */ 207 208/* 209 * features will have bits indication whether there is support for: 210 */ 211#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001 212#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002 213#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004 214#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008 215#define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x0000000000000010 216 217#ifndef __ASSEMBLY__ 218 219struct ppc_hw_breakpoint { 220 __u32 version; /* currently, version must be 1 */ 221 __u32 trigger_type; /* only some combinations allowed */ 222 __u32 addr_mode; /* address match mode */ 223 __u32 condition_mode; /* break/watchpoint condition flags */ 224 __u64 addr; /* break/watchpoint address */ 225 __u64 addr2; /* range end or mask */ 226 __u64 condition_value; /* contents of the DVC register */ 227}; 228 229#endif /* __ASSEMBLY__ */ 230 231/* 232 * Trigger Type 233 */ 234#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001 235#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002 236#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004 237#define PPC_BREAKPOINT_TRIGGER_RW \ 238 (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE) 239 240/* 241 * Address Mode 242 */ 243#define PPC_BREAKPOINT_MODE_EXACT 0x00000000 244#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001 245#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002 246#define PPC_BREAKPOINT_MODE_MASK 0x00000003 247 248/* 249 * Condition Mode 250 */ 251#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003 252#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000 253#define PPC_BREAKPOINT_CONDITION_AND 0x00000001 254#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND 255#define PPC_BREAKPOINT_CONDITION_OR 0x00000002 256#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003 257#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 258#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 259#define PPC_BREAKPOINT_CONDITION_BE(n) \ 260 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) 261 262#endif /* _UAPI_ASM_POWERPC_PTRACE_H */ 263