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24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/pci.h>
27#include <linux/irq.h>
28#include <linux/interrupt.h>
29
30#include <asm/byteorder.h>
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <linux/uaccess.h>
34#include <asm/machdep.h>
35#include <asm/pci-bridge.h>
36#include <asm/tsi108.h>
37#include <asm/tsi108_pci.h>
38#include <asm/tsi108_irq.h>
39#include <asm/prom.h>
40
41#undef DEBUG
42#ifdef DEBUG
43#define DBG(x...) printk(x)
44#else
45#define DBG(x...)
46#endif
47
48#define tsi_mk_config_addr(bus, devfunc, offset) \
49 ((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)
50
51u32 tsi108_pci_cfg_base;
52static u32 tsi108_pci_cfg_phys;
53u32 tsi108_csr_vir_base;
54static struct irq_domain *pci_irq_host;
55
56extern u32 get_vir_csrbase(void);
57extern u32 tsi108_read_reg(u32 reg_offset);
58extern void tsi108_write_reg(u32 reg_offset, u32 val);
59
60int
61tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
62 int offset, int len, u32 val)
63{
64 volatile unsigned char *cfg_addr;
65 struct pci_controller *hose = pci_bus_to_host(bus);
66
67 if (ppc_md.pci_exclude_device)
68 if (ppc_md.pci_exclude_device(hose, bus->number, devfunc))
69 return PCIBIOS_DEVICE_NOT_FOUND;
70
71 cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
72 devfunc, offset) |
73 (offset & 0x03));
74
75#ifdef DEBUG
76 printk("PCI CFG write : ");
77 printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
78 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
79 printk("data = 0x%08x\n", val);
80#endif
81
82 switch (len) {
83 case 1:
84 out_8((u8 *) cfg_addr, val);
85 break;
86 case 2:
87 out_le16((u16 *) cfg_addr, val);
88 break;
89 default:
90 out_le32((u32 *) cfg_addr, val);
91 break;
92 }
93
94 return PCIBIOS_SUCCESSFUL;
95}
96
97void tsi108_clear_pci_error(u32 pci_cfg_base)
98{
99 u32 err_stat, err_addr, pci_stat;
100
101
102
103
104
105
106
107
108 err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
109 err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);
110
111 if (err_stat & TSI108_PB_ERRCS_ES) {
112
113 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
114 TSI108_PB_ERRCS_ES);
115
116
117 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
118 TSI108_PB_ISR_PBS_RD_ERR);
119
120
121 if ((err_addr & 0xFF000000) == pci_cfg_base) {
122 pci_stat =
123 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
124 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
125 pci_stat);
126 }
127 }
128
129 return;
130}
131
132#define __tsi108_read_pci_config(x, addr, op) \
133 __asm__ __volatile__( \
134 " "op" %0,0,%1\n" \
135 "1: eieio\n" \
136 "2:\n" \
137 ".section .fixup,\"ax\"\n" \
138 "3: li %0,-1\n" \
139 " b 2b\n" \
140 ".previous\n" \
141 EX_TABLE(1b, 3b) \
142 : "=r"(x) : "r"(addr))
143
144int
145tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
146 int len, u32 * val)
147{
148 volatile unsigned char *cfg_addr;
149 struct pci_controller *hose = pci_bus_to_host(bus);
150 u32 temp;
151
152 if (ppc_md.pci_exclude_device)
153 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
154 return PCIBIOS_DEVICE_NOT_FOUND;
155
156 cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
157 devfn,
158 offset) | (offset &
159 0x03));
160
161 switch (len) {
162 case 1:
163 __tsi108_read_pci_config(temp, cfg_addr, "lbzx");
164 break;
165 case 2:
166 __tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
167 break;
168 default:
169 __tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
170 break;
171 }
172
173 *val = temp;
174
175#ifdef DEBUG
176 if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
177 printk("PCI CFG read : ");
178 printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
179 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
180 printk("data = 0x%x\n", *val);
181 }
182#endif
183 return PCIBIOS_SUCCESSFUL;
184}
185
186void tsi108_clear_pci_cfg_error(void)
187{
188 tsi108_clear_pci_error(tsi108_pci_cfg_phys);
189}
190
191static struct pci_ops tsi108_direct_pci_ops = {
192 .read = tsi108_direct_read_config,
193 .write = tsi108_direct_write_config,
194};
195
196int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
197{
198 int len;
199 struct pci_controller *hose;
200 struct resource rsrc;
201 const int *bus_range;
202 int has_address = 0;
203
204
205 tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
206 tsi108_pci_cfg_phys = cfg_phys;
207 DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__,
208 tsi108_pci_cfg_base);
209
210
211 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
212
213
214 bus_range = of_get_property(dev, "bus-range", &len);
215 if (bus_range == NULL || len < 2 * sizeof(int)) {
216 printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
217 " bus 0\n", dev);
218 }
219
220 hose = pcibios_alloc_controller(dev);
221
222 if (!hose) {
223 printk("PCI Host bridge init failed\n");
224 return -ENOMEM;
225 }
226
227 hose->first_busno = bus_range ? bus_range[0] : 0;
228 hose->last_busno = bus_range ? bus_range[1] : 0xff;
229
230 (hose)->ops = &tsi108_direct_pci_ops;
231
232 printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
233 "Firmware bus number: %d->%d\n",
234 rsrc.start, hose->first_busno, hose->last_busno);
235
236
237
238 pci_process_bridge_OF_ranges(hose, dev, primary);
239 return 0;
240}
241
242
243
244
245
246static void tsi108_pci_int_mask(u_int irq)
247{
248 u_int irp_cfg;
249 int int_line = (irq - IRQ_PCI_INTAD_BASE);
250
251 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
252 mb();
253 irp_cfg |= (1 << int_line);
254 irp_cfg &= ~(3 << (8 + (int_line * 2)));
255 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
256 mb();
257 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
258}
259
260static void tsi108_pci_int_unmask(u_int irq)
261{
262 u_int irp_cfg;
263 int int_line = (irq - IRQ_PCI_INTAD_BASE);
264
265 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
266 mb();
267 irp_cfg &= ~(1 << int_line);
268 irp_cfg |= (3 << (8 + (int_line * 2)));
269 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
270 mb();
271}
272
273static void init_pci_source(void)
274{
275 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
276 0x0000ff00);
277 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
278 TSI108_PCI_IRP_ENABLE_P_INT);
279 mb();
280}
281
282static inline unsigned int get_pci_source(void)
283{
284 u_int temp = 0;
285 int irq = -1;
286 int i;
287 u_int pci_irp_stat;
288 static int mask = 0;
289
290
291 pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
292 mb();
293
294 if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
295
296 temp =
297 tsi108_read_reg(TSI108_PCI_OFFSET +
298 TSI108_PCI_IRP_INTAD) & 0xf;
299 mb();
300 for (i = 0; i < 4; i++, mask++) {
301 if (temp & (1 << mask % 4)) {
302 irq = IRQ_PCI_INTA + mask % 4;
303 mask++;
304 break;
305 }
306 }
307
308
309 temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
310 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
311 temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
312 mb();
313 (void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
314 mb();
315 }
316#ifdef DEBUG
317 else {
318 printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
319 pci_irp_stat =
320 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
321 temp =
322 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
323 mb();
324 printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
325 temp =
326 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
327 mb();
328 printk("cfg_ctl=0x%08x ", temp);
329 temp =
330 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
331 mb();
332 printk("irp_enable=0x%08x\n", temp);
333 }
334#endif
335
336 return irq;
337}
338
339
340
341
342
343
344static void tsi108_pci_irq_unmask(struct irq_data *d)
345{
346 tsi108_pci_int_unmask(d->irq);
347
348
349 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
350 tsi108_read_reg(TSI108_PCI_OFFSET +
351 TSI108_PCI_IRP_ENABLE) |
352 TSI108_PCI_IRP_ENABLE_P_INT);
353 mb();
354}
355
356static void tsi108_pci_irq_mask(struct irq_data *d)
357{
358 tsi108_pci_int_mask(d->irq);
359}
360
361static void tsi108_pci_irq_ack(struct irq_data *d)
362{
363 tsi108_pci_int_mask(d->irq);
364}
365
366
367
368
369
370static struct irq_chip tsi108_pci_irq = {
371 .name = "tsi108_PCI_int",
372 .irq_mask = tsi108_pci_irq_mask,
373 .irq_ack = tsi108_pci_irq_ack,
374 .irq_unmask = tsi108_pci_irq_unmask,
375};
376
377static int pci_irq_host_xlate(struct irq_domain *h, struct device_node *ct,
378 const u32 *intspec, unsigned int intsize,
379 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
380{
381 *out_hwirq = intspec[0];
382 *out_flags = IRQ_TYPE_LEVEL_HIGH;
383 return 0;
384}
385
386static int pci_irq_host_map(struct irq_domain *h, unsigned int virq,
387 irq_hw_number_t hw)
388{ unsigned int irq;
389 DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
390 if ((virq >= 1) && (virq <= 4)){
391 irq = virq + IRQ_PCI_INTAD_BASE - 1;
392 irq_set_status_flags(irq, IRQ_LEVEL);
393 irq_set_chip(irq, &tsi108_pci_irq);
394 }
395 return 0;
396}
397
398static const struct irq_domain_ops pci_irq_domain_ops = {
399 .map = pci_irq_host_map,
400 .xlate = pci_irq_host_xlate,
401};
402
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414
415
416void __init tsi108_pci_int_init(struct device_node *node)
417{
418 DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
419
420 pci_irq_host = irq_domain_add_legacy_isa(node, &pci_irq_domain_ops, NULL);
421 if (pci_irq_host == NULL) {
422 printk(KERN_ERR "pci_irq_host: failed to allocate irq domain!\n");
423 return;
424 }
425
426 init_pci_source();
427}
428
429void tsi108_irq_cascade(struct irq_desc *desc)
430{
431 struct irq_chip *chip = irq_desc_get_chip(desc);
432 unsigned int cascade_irq = get_pci_source();
433
434 if (cascade_irq)
435 generic_handle_irq(cascade_irq);
436
437 chip->irq_eoi(&desc->irq_data);
438}
439
