LXR linux/arch/x86/include/asm/irq

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef _ASM_X86_IRQ_VECTORS_H
   3#define _ASM_X86_IRQ_VECTORS_H
   4
   5#include <linux/threads.h>
   6/*
   7 * Linux IRQ vector layout.
   8 *
   9 * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can
  10 * be defined by Linux. They are used as a jump table by the CPU when a
  11 * given vector is triggered - by a CPU-external, CPU-internal or
  12 * software-triggered event.
  13 *
  14 * Linux sets the kernel code address each entry jumps to early during
  15 * bootup, and never changes them. This is the general layout of the
  16 * IDT entries:
  17 *
  18 *  Vectors   0 ...  31 : system traps and exceptions - hardcoded events
  19 *  Vectors  32 ... 127 : device interrupts
  20 *  Vector  128         : legacy int80 syscall interface
  21 *  Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 except 204 : device interrupts
  22 *  Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts
  23 *
  24 * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
  25 *
  26 * This file enumerates the exact layout of them:
  27 */
  28
  29#define NMI_VECTOR                      0x02
  30#define MCE_VECTOR                      0x12
  31
  32/*
  33 * IDT vectors usable for external interrupt sources start at 0x20.
  34 * (0x80 is the syscall vector, 0x30-0x3f are for ISA)
  35 */
  36#define FIRST_EXTERNAL_VECTOR           0x20
  37/*
  38 * We start allocating at 0x21 to spread out vectors evenly between
  39 * priority levels. (0x80 is the syscall vector)
  40 */
  41#define VECTOR_OFFSET_START             1
  42
  43/*
  44 * Reserve the lowest usable vector (and hence lowest priority)  0x20 for
  45 * triggering cleanup after irq migration. 0x21-0x2f will still be used
  46 * for device interrupts.
  47 */
  48#define IRQ_MOVE_CLEANUP_VECTOR         FIRST_EXTERNAL_VECTOR
  49
  50#define IA32_SYSCALL_VECTOR             0x80
  51
  52/*
  53 * Vectors 0x30-0x3f are used for ISA interrupts.
  54 *   round up to the next 16-vector boundary
  55 */
  56#define ISA_IRQ_VECTOR(irq)             (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq)
  57
  58/*
  59 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
  60 *
  61 *  some of the following vectors are 'rare', they are merged
  62 *  into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
  63 *  TLB, reschedule and local APIC vectors are performance-critical.
  64 */
  65
  66#define SPURIOUS_APIC_VECTOR            0xff
  67/*
  68 * Sanity check
  69 */
  70#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
  71# error SPURIOUS_APIC_VECTOR definition error
  72#endif
  73
  74#define ERROR_APIC_VECTOR               0xfe
  75#define RESCHEDULE_VECTOR               0xfd
  76#define CALL_FUNCTION_VECTOR            0xfc
  77#define CALL_FUNCTION_SINGLE_VECTOR     0xfb
  78#define THERMAL_APIC_VECTOR             0xfa
  79#define THRESHOLD_APIC_VECTOR           0xf9
  80#define REBOOT_VECTOR                   0xf8
  81
  82/*
  83 * Generic system vector for platform specific use
  84 */
  85#define X86_PLATFORM_IPI_VECTOR         0xf7
  86
  87/*
  88 * IRQ work vector:
  89 */
  90#define IRQ_WORK_VECTOR                 0xf6
  91
  92#define UV_BAU_MESSAGE                  0xf5
  93#define DEFERRED_ERROR_VECTOR           0xf4
  94
  95/* Vector on which hypervisor callbacks will be delivered */
  96#define HYPERVISOR_CALLBACK_VECTOR      0xf3
  97
  98/* Vector for KVM to deliver posted interrupt IPI */
  99#ifdef CONFIG_HAVE_KVM
 100#define POSTED_INTR_VECTOR              0xf2
 101#define POSTED_INTR_WAKEUP_VECTOR       0xf1
 102#define POSTED_INTR_NESTED_VECTOR       0xf0
 103#endif
 104
 105#define MANAGED_IRQ_SHUTDOWN_VECTOR     0xef
 106
 107#if IS_ENABLED(CONFIG_HYPERV)
 108#define HYPERV_REENLIGHTENMENT_VECTOR   0xee
 109#endif
 110
 111#define LOCAL_TIMER_VECTOR              0xed
 112
 113#define NR_VECTORS                       256
 114
 115#ifdef CONFIG_X86_LOCAL_APIC
 116#define FIRST_SYSTEM_VECTOR             LOCAL_TIMER_VECTOR
 117#else
 118#define FIRST_SYSTEM_VECTOR             NR_VECTORS
 119#endif
 120
 121#define FPU_IRQ                           13
 122
 123/*
 124 * Size the maximum number of interrupts.
 125 *
 126 * If the irq_desc[] array has a sparse layout, we can size things
 127 * generously - it scales up linearly with the maximum number of CPUs,
 128 * and the maximum number of IO-APICs, whichever is higher.
 129 *
 130 * In other cases we size more conservatively, to not create too large
 131 * static arrays.
 132 */
 133
 134#define NR_IRQS_LEGACY                  16
 135
 136#define CPU_VECTOR_LIMIT                (64 * NR_CPUS)
 137#define IO_APIC_VECTOR_LIMIT            (32 * MAX_IO_APICS)
 138
 139#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_PCI_MSI)
 140#define NR_IRQS                                         \
 141        (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ?      \
 142                (NR_VECTORS + CPU_VECTOR_LIMIT)  :      \
 143                (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
 144#elif defined(CONFIG_X86_IO_APIC)
 145#define NR_IRQS                         (NR_VECTORS + IO_APIC_VECTOR_LIMIT)
 146#elif defined(CONFIG_PCI_MSI)
 147#define NR_IRQS                         (NR_VECTORS + CPU_VECTOR_LIMIT)
 148#else
 149#define NR_IRQS                         NR_IRQS_LEGACY
 150#endif
 151
 152#endif /* _ASM_X86_IRQ_VECTORS_H */
 153