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8#include <linux/clk-provider.h>
9#include <linux/err.h>
10#include <linux/device.h>
11#include <linux/of_address.h>
12#include <linux/slab.h>
13
14static DEFINE_SPINLOCK(clklock);
15
16#define MAX_FREQ 33333333
17#define MIN_FREQ 8000000
18
19struct pll_clock {
20 struct clk_hw hw;
21 void __iomem *sckcr;
22 void __iomem *pllcr;
23};
24
25#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
26
27static unsigned long pll_recalc_rate(struct clk_hw *hw,
28 unsigned long parent_rate)
29{
30 struct pll_clock *pll_clock = to_pll_clock(hw);
31 int mul = 1 << (readb(pll_clock->pllcr) & 3);
32
33 return parent_rate * mul;
34}
35
36static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
37 unsigned long *prate)
38{
39 int i, m = -1;
40 long offset[3];
41
42 if (rate > MAX_FREQ)
43 rate = MAX_FREQ;
44 if (rate < MIN_FREQ)
45 rate = MIN_FREQ;
46
47 for (i = 0; i < 3; i++)
48 offset[i] = abs(rate - (*prate * (1 << i)));
49 for (i = 0; i < 3; i++)
50 if (m < 0)
51 m = i;
52 else
53 m = (offset[i] < offset[m])?i:m;
54
55 return *prate * (1 << m);
56}
57
58static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long parent_rate)
60{
61 int pll;
62 unsigned char val;
63 unsigned long flags;
64 struct pll_clock *pll_clock = to_pll_clock(hw);
65
66 pll = ((rate / parent_rate) / 2) & 0x03;
67 spin_lock_irqsave(&clklock, flags);
68 val = readb(pll_clock->sckcr);
69 val |= 0x08;
70 writeb(val, pll_clock->sckcr);
71 val = readb(pll_clock->pllcr);
72 val &= ~0x03;
73 val |= pll;
74 writeb(val, pll_clock->pllcr);
75 spin_unlock_irqrestore(&clklock, flags);
76 return 0;
77}
78
79static const struct clk_ops pll_ops = {
80 .recalc_rate = pll_recalc_rate,
81 .round_rate = pll_round_rate,
82 .set_rate = pll_set_rate,
83};
84
85static void __init h8s2678_pll_clk_setup(struct device_node *node)
86{
87 unsigned int num_parents;
88 const char *clk_name = node->name;
89 const char *parent_name;
90 struct pll_clock *pll_clock;
91 struct clk_init_data init;
92 int ret;
93
94 num_parents = of_clk_get_parent_count(node);
95 if (!num_parents) {
96 pr_err("%s: no parent found\n", clk_name);
97 return;
98 }
99
100
101 pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL);
102 if (!pll_clock)
103 return;
104
105 pll_clock->sckcr = of_iomap(node, 0);
106 if (pll_clock->sckcr == NULL) {
107 pr_err("%s: failed to map divide register\n", clk_name);
108 goto free_clock;
109 }
110
111 pll_clock->pllcr = of_iomap(node, 1);
112 if (pll_clock->pllcr == NULL) {
113 pr_err("%s: failed to map multiply register\n", clk_name);
114 goto unmap_sckcr;
115 }
116
117 parent_name = of_clk_get_parent_name(node, 0);
118 init.name = clk_name;
119 init.ops = &pll_ops;
120 init.flags = CLK_IS_BASIC;
121 init.parent_names = &parent_name;
122 init.num_parents = 1;
123 pll_clock->hw.init = &init;
124
125 ret = clk_hw_register(NULL, &pll_clock->hw);
126 if (ret) {
127 pr_err("%s: failed to register %s div clock (%d)\n",
128 __func__, clk_name, ret);
129 goto unmap_pllcr;
130 }
131
132 of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
133 return;
134
135unmap_pllcr:
136 iounmap(pll_clock->pllcr);
137unmap_sckcr:
138 iounmap(pll_clock->sckcr);
139free_clock:
140 kfree(pll_clock);
141}
142
143CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
144 h8s2678_pll_clk_setup);
145
