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15#include <linux/clk-provider.h>
16#include <linux/err.h>
17#include <linux/export.h>
18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/mutex.h>
22#include <linux/mfd/qcom_rpm.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/platform_device.h>
26
27#include <dt-bindings/mfd/qcom-rpm.h>
28#include <dt-bindings/clock/qcom,rpmcc.h>
29
30#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
31#define QCOM_RPM_SCALING_ENABLE_ID 0x2
32
33#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
34 static struct clk_rpm _platform##_##_active; \
35 static struct clk_rpm _platform##_##_name = { \
36 .rpm_clk_id = (r_id), \
37 .peer = &_platform##_##_active, \
38 .rate = INT_MAX, \
39 .hw.init = &(struct clk_init_data){ \
40 .ops = &clk_rpm_ops, \
41 .name = #_name, \
42 .parent_names = (const char *[]){ "pxo_board" }, \
43 .num_parents = 1, \
44 }, \
45 }; \
46 static struct clk_rpm _platform##_##_active = { \
47 .rpm_clk_id = (r_id), \
48 .peer = &_platform##_##_name, \
49 .active_only = true, \
50 .rate = INT_MAX, \
51 .hw.init = &(struct clk_init_data){ \
52 .ops = &clk_rpm_ops, \
53 .name = #_active, \
54 .parent_names = (const char *[]){ "pxo_board" }, \
55 .num_parents = 1, \
56 }, \
57 }
58
59#define DEFINE_CLK_RPM_FIXED(_platform, _name, _active, r_id, r) \
60 static struct clk_rpm _platform##_##_name = { \
61 .rpm_clk_id = (r_id), \
62 .rate = (r), \
63 .hw.init = &(struct clk_init_data){ \
64 .ops = &clk_rpm_fixed_ops, \
65 .name = #_name, \
66 .parent_names = (const char *[]){ "pxo" }, \
67 .num_parents = 1, \
68 }, \
69 }
70
71#define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \
72 static struct clk_rpm _platform##_##_active; \
73 static struct clk_rpm _platform##_##_name = { \
74 .rpm_clk_id = (r_id), \
75 .active_only = true, \
76 .peer = &_platform##_##_active, \
77 .rate = (r), \
78 .branch = true, \
79 .hw.init = &(struct clk_init_data){ \
80 .ops = &clk_rpm_branch_ops, \
81 .name = #_name, \
82 .parent_names = (const char *[]){ "pxo_board" }, \
83 .num_parents = 1, \
84 }, \
85 }; \
86 static struct clk_rpm _platform##_##_active = { \
87 .rpm_clk_id = (r_id), \
88 .peer = &_platform##_##_name, \
89 .rate = (r), \
90 .branch = true, \
91 .hw.init = &(struct clk_init_data){ \
92 .ops = &clk_rpm_branch_ops, \
93 .name = #_active, \
94 .parent_names = (const char *[]){ "pxo_board" }, \
95 .num_parents = 1, \
96 }, \
97 }
98
99#define DEFINE_CLK_RPM_CXO_BRANCH(_platform, _name, _active, r_id, r) \
100 static struct clk_rpm _platform##_##_active; \
101 static struct clk_rpm _platform##_##_name = { \
102 .rpm_clk_id = (r_id), \
103 .peer = &_platform##_##_active, \
104 .rate = (r), \
105 .branch = true, \
106 .hw.init = &(struct clk_init_data){ \
107 .ops = &clk_rpm_branch_ops, \
108 .name = #_name, \
109 .parent_names = (const char *[]){ "cxo_board" }, \
110 .num_parents = 1, \
111 }, \
112 }; \
113 static struct clk_rpm _platform##_##_active = { \
114 .rpm_clk_id = (r_id), \
115 .active_only = true, \
116 .peer = &_platform##_##_name, \
117 .rate = (r), \
118 .branch = true, \
119 .hw.init = &(struct clk_init_data){ \
120 .ops = &clk_rpm_branch_ops, \
121 .name = #_active, \
122 .parent_names = (const char *[]){ "cxo_board" }, \
123 .num_parents = 1, \
124 }, \
125 }
126
127#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
128
129struct clk_rpm {
130 const int rpm_clk_id;
131 const bool active_only;
132 unsigned long rate;
133 bool enabled;
134 bool branch;
135 struct clk_rpm *peer;
136 struct clk_hw hw;
137 struct qcom_rpm *rpm;
138};
139
140struct rpm_cc {
141 struct qcom_rpm *rpm;
142 struct clk_rpm **clks;
143 size_t num_clks;
144};
145
146struct rpm_clk_desc {
147 struct clk_rpm **clks;
148 size_t num_clks;
149};
150
151static DEFINE_MUTEX(rpm_clk_lock);
152
153static int clk_rpm_handoff(struct clk_rpm *r)
154{
155 int ret;
156 u32 value = INT_MAX;
157
158
159
160
161
162 if (r->rpm_clk_id == QCOM_RPM_PLL_4)
163 return 0;
164
165 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
166 r->rpm_clk_id, &value, 1);
167 if (ret)
168 return ret;
169 ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
170 r->rpm_clk_id, &value, 1);
171 if (ret)
172 return ret;
173
174 return 0;
175}
176
177static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
178{
179 u32 value = DIV_ROUND_UP(rate, 1000);
180
181 return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
182 r->rpm_clk_id, &value, 1);
183}
184
185static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
186{
187 u32 value = DIV_ROUND_UP(rate, 1000);
188
189 return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
190 r->rpm_clk_id, &value, 1);
191}
192
193static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
194 unsigned long *active, unsigned long *sleep)
195{
196 *active = rate;
197
198
199
200
201
202 if (r->active_only)
203 *sleep = 0;
204 else
205 *sleep = *active;
206}
207
208static int clk_rpm_prepare(struct clk_hw *hw)
209{
210 struct clk_rpm *r = to_clk_rpm(hw);
211 struct clk_rpm *peer = r->peer;
212 unsigned long this_rate = 0, this_sleep_rate = 0;
213 unsigned long peer_rate = 0, peer_sleep_rate = 0;
214 unsigned long active_rate, sleep_rate;
215 int ret = 0;
216
217 mutex_lock(&rpm_clk_lock);
218
219
220 if (!r->rate)
221 goto out;
222
223 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
224
225
226 if (peer->enabled)
227 to_active_sleep(peer, peer->rate,
228 &peer_rate, &peer_sleep_rate);
229
230 active_rate = max(this_rate, peer_rate);
231
232 if (r->branch)
233 active_rate = !!active_rate;
234
235 ret = clk_rpm_set_rate_active(r, active_rate);
236 if (ret)
237 goto out;
238
239 sleep_rate = max(this_sleep_rate, peer_sleep_rate);
240 if (r->branch)
241 sleep_rate = !!sleep_rate;
242
243 ret = clk_rpm_set_rate_sleep(r, sleep_rate);
244 if (ret)
245
246 ret = clk_rpm_set_rate_active(r, peer_rate);
247
248out:
249 if (!ret)
250 r->enabled = true;
251
252 mutex_unlock(&rpm_clk_lock);
253
254 return ret;
255}
256
257static void clk_rpm_unprepare(struct clk_hw *hw)
258{
259 struct clk_rpm *r = to_clk_rpm(hw);
260 struct clk_rpm *peer = r->peer;
261 unsigned long peer_rate = 0, peer_sleep_rate = 0;
262 unsigned long active_rate, sleep_rate;
263 int ret;
264
265 mutex_lock(&rpm_clk_lock);
266
267 if (!r->rate)
268 goto out;
269
270
271 if (peer->enabled)
272 to_active_sleep(peer, peer->rate, &peer_rate,
273 &peer_sleep_rate);
274
275 active_rate = r->branch ? !!peer_rate : peer_rate;
276 ret = clk_rpm_set_rate_active(r, active_rate);
277 if (ret)
278 goto out;
279
280 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
281 ret = clk_rpm_set_rate_sleep(r, sleep_rate);
282 if (ret)
283 goto out;
284
285 r->enabled = false;
286
287out:
288 mutex_unlock(&rpm_clk_lock);
289}
290
291static int clk_rpm_fixed_prepare(struct clk_hw *hw)
292{
293 struct clk_rpm *r = to_clk_rpm(hw);
294 u32 value = 1;
295 int ret;
296
297 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
298 r->rpm_clk_id, &value, 1);
299 if (!ret)
300 r->enabled = true;
301
302 return ret;
303}
304
305static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
306{
307 struct clk_rpm *r = to_clk_rpm(hw);
308 u32 value = 0;
309 int ret;
310
311 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
312 r->rpm_clk_id, &value, 1);
313 if (!ret)
314 r->enabled = false;
315}
316
317static int clk_rpm_set_rate(struct clk_hw *hw,
318 unsigned long rate, unsigned long parent_rate)
319{
320 struct clk_rpm *r = to_clk_rpm(hw);
321 struct clk_rpm *peer = r->peer;
322 unsigned long active_rate, sleep_rate;
323 unsigned long this_rate = 0, this_sleep_rate = 0;
324 unsigned long peer_rate = 0, peer_sleep_rate = 0;
325 int ret = 0;
326
327 mutex_lock(&rpm_clk_lock);
328
329 if (!r->enabled)
330 goto out;
331
332 to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
333
334
335 if (peer->enabled)
336 to_active_sleep(peer, peer->rate,
337 &peer_rate, &peer_sleep_rate);
338
339 active_rate = max(this_rate, peer_rate);
340 ret = clk_rpm_set_rate_active(r, active_rate);
341 if (ret)
342 goto out;
343
344 sleep_rate = max(this_sleep_rate, peer_sleep_rate);
345 ret = clk_rpm_set_rate_sleep(r, sleep_rate);
346 if (ret)
347 goto out;
348
349 r->rate = rate;
350
351out:
352 mutex_unlock(&rpm_clk_lock);
353
354 return ret;
355}
356
357static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
358 unsigned long *parent_rate)
359{
360
361
362
363
364
365 return rate;
366}
367
368static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
369 unsigned long parent_rate)
370{
371 struct clk_rpm *r = to_clk_rpm(hw);
372
373
374
375
376
377
378 return r->rate;
379}
380
381static const struct clk_ops clk_rpm_fixed_ops = {
382 .prepare = clk_rpm_fixed_prepare,
383 .unprepare = clk_rpm_fixed_unprepare,
384 .round_rate = clk_rpm_round_rate,
385 .recalc_rate = clk_rpm_recalc_rate,
386};
387
388static const struct clk_ops clk_rpm_ops = {
389 .prepare = clk_rpm_prepare,
390 .unprepare = clk_rpm_unprepare,
391 .set_rate = clk_rpm_set_rate,
392 .round_rate = clk_rpm_round_rate,
393 .recalc_rate = clk_rpm_recalc_rate,
394};
395
396static const struct clk_ops clk_rpm_branch_ops = {
397 .prepare = clk_rpm_prepare,
398 .unprepare = clk_rpm_unprepare,
399 .round_rate = clk_rpm_round_rate,
400 .recalc_rate = clk_rpm_recalc_rate,
401};
402
403
404DEFINE_CLK_RPM(msm8660, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
405DEFINE_CLK_RPM(msm8660, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
406DEFINE_CLK_RPM(msm8660, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
407DEFINE_CLK_RPM(msm8660, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
408DEFINE_CLK_RPM(msm8660, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
409DEFINE_CLK_RPM(msm8660, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
410DEFINE_CLK_RPM(msm8660, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
411DEFINE_CLK_RPM(msm8660, smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK);
412DEFINE_CLK_RPM(msm8660, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
413DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, pll4_a_clk, QCOM_RPM_PLL_4, 540672000);
414
415static struct clk_rpm *msm8660_clks[] = {
416 [RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk,
417 [RPM_APPS_FABRIC_A_CLK] = &msm8660_afab_a_clk,
418 [RPM_SYS_FABRIC_CLK] = &msm8660_sfab_clk,
419 [RPM_SYS_FABRIC_A_CLK] = &msm8660_sfab_a_clk,
420 [RPM_MM_FABRIC_CLK] = &msm8660_mmfab_clk,
421 [RPM_MM_FABRIC_A_CLK] = &msm8660_mmfab_a_clk,
422 [RPM_DAYTONA_FABRIC_CLK] = &msm8660_daytona_clk,
423 [RPM_DAYTONA_FABRIC_A_CLK] = &msm8660_daytona_a_clk,
424 [RPM_SFPB_CLK] = &msm8660_sfpb_clk,
425 [RPM_SFPB_A_CLK] = &msm8660_sfpb_a_clk,
426 [RPM_CFPB_CLK] = &msm8660_cfpb_clk,
427 [RPM_CFPB_A_CLK] = &msm8660_cfpb_a_clk,
428 [RPM_MMFPB_CLK] = &msm8660_mmfpb_clk,
429 [RPM_MMFPB_A_CLK] = &msm8660_mmfpb_a_clk,
430 [RPM_SMI_CLK] = &msm8660_smi_clk,
431 [RPM_SMI_A_CLK] = &msm8660_smi_a_clk,
432 [RPM_EBI1_CLK] = &msm8660_ebi1_clk,
433 [RPM_EBI1_A_CLK] = &msm8660_ebi1_a_clk,
434 [RPM_PLL4_CLK] = &msm8660_pll4_clk,
435};
436
437static const struct rpm_clk_desc rpm_clk_msm8660 = {
438 .clks = msm8660_clks,
439 .num_clks = ARRAY_SIZE(msm8660_clks),
440};
441
442
443DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
444DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
445DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
446DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
447DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
448DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
449DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
450DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
451DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK);
452
453static struct clk_rpm *apq8064_clks[] = {
454 [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
455 [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
456 [RPM_CFPB_CLK] = &apq8064_cfpb_clk,
457 [RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk,
458 [RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk,
459 [RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk,
460 [RPM_EBI1_CLK] = &apq8064_ebi1_clk,
461 [RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk,
462 [RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk,
463 [RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk,
464 [RPM_MMFPB_CLK] = &apq8064_mmfpb_clk,
465 [RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk,
466 [RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk,
467 [RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk,
468 [RPM_SFPB_CLK] = &apq8064_sfpb_clk,
469 [RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk,
470 [RPM_QDSS_CLK] = &apq8064_qdss_clk,
471 [RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk,
472};
473
474static const struct rpm_clk_desc rpm_clk_apq8064 = {
475 .clks = apq8064_clks,
476 .num_clks = ARRAY_SIZE(apq8064_clks),
477};
478
479static const struct of_device_id rpm_clk_match_table[] = {
480 { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
481 { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
482 { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
483 { }
484};
485MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
486
487static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec,
488 void *data)
489{
490 struct rpm_cc *rcc = data;
491 unsigned int idx = clkspec->args[0];
492
493 if (idx >= rcc->num_clks) {
494 pr_err("%s: invalid index %u\n", __func__, idx);
495 return ERR_PTR(-EINVAL);
496 }
497
498 return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
499}
500
501static int rpm_clk_probe(struct platform_device *pdev)
502{
503 struct rpm_cc *rcc;
504 int ret;
505 size_t num_clks, i;
506 struct qcom_rpm *rpm;
507 struct clk_rpm **rpm_clks;
508 const struct rpm_clk_desc *desc;
509
510 rpm = dev_get_drvdata(pdev->dev.parent);
511 if (!rpm) {
512 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
513 return -ENODEV;
514 }
515
516 desc = of_device_get_match_data(&pdev->dev);
517 if (!desc)
518 return -EINVAL;
519
520 rpm_clks = desc->clks;
521 num_clks = desc->num_clks;
522
523 rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
524 if (!rcc)
525 return -ENOMEM;
526
527 rcc->clks = rpm_clks;
528 rcc->num_clks = num_clks;
529
530 for (i = 0; i < num_clks; i++) {
531 if (!rpm_clks[i])
532 continue;
533
534 rpm_clks[i]->rpm = rpm;
535
536 ret = clk_rpm_handoff(rpm_clks[i]);
537 if (ret)
538 goto err;
539 }
540
541 for (i = 0; i < num_clks; i++) {
542 if (!rpm_clks[i])
543 continue;
544
545 ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
546 if (ret)
547 goto err;
548 }
549
550 ret = of_clk_add_hw_provider(pdev->dev.of_node, qcom_rpm_clk_hw_get,
551 rcc);
552 if (ret)
553 goto err;
554
555 return 0;
556err:
557 dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
558 return ret;
559}
560
561static int rpm_clk_remove(struct platform_device *pdev)
562{
563 of_clk_del_provider(pdev->dev.of_node);
564 return 0;
565}
566
567static struct platform_driver rpm_clk_driver = {
568 .driver = {
569 .name = "qcom-clk-rpm",
570 .of_match_table = rpm_clk_match_table,
571 },
572 .probe = rpm_clk_probe,
573 .remove = rpm_clk_remove,
574};
575
576static int __init rpm_clk_init(void)
577{
578 return platform_driver_register(&rpm_clk_driver);
579}
580core_initcall(rpm_clk_init);
581
582static void __exit rpm_clk_exit(void)
583{
584 platform_driver_unregister(&rpm_clk_driver);
585}
586module_exit(rpm_clk_exit);
587
588MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
589MODULE_LICENSE("GPL v2");
590MODULE_ALIAS("platform:qcom-clk-rpm");
591
