LXR linux/drivers/clk/sunxi/clk-sun6i-apb0-gates.c

   1/*
   2 * Copyright (C) 2014 Free Electrons
   3 *
   4 * License Terms: GNU General Public License v2
   5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
   6 *
   7 * Allwinner A31 APB0 clock gates driver
   8 *
   9 */
  10
  11#include <linux/clk-provider.h>
  12#include <linux/init.h>
  13#include <linux/of.h>
  14#include <linux/of_device.h>
  15#include <linux/platform_device.h>
  16
  17#define SUN6I_APB0_GATES_MAX_SIZE       32
  18
  19struct gates_data {
  20        DECLARE_BITMAP(mask, SUN6I_APB0_GATES_MAX_SIZE);
  21};
  22
  23static const struct gates_data sun6i_a31_apb0_gates __initconst = {
  24        .mask = {0x7F},
  25};
  26
  27static const struct gates_data sun8i_a23_apb0_gates __initconst = {
  28        .mask = {0x5D},
  29};
  30
  31static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
  32        { .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
  33        { .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
  34        { /* sentinel */ }
  35};
  36
  37static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
  38{
  39        struct device_node *np = pdev->dev.of_node;
  40        struct clk_onecell_data *clk_data;
  41        const struct of_device_id *device;
  42        const struct gates_data *data;
  43        const char *clk_parent;
  44        const char *clk_name;
  45        struct resource *r;
  46        void __iomem *reg;
  47        int ngates;
  48        int i;
  49        int j = 0;
  50
  51        if (!np)
  52                return -ENODEV;
  53
  54        device = of_match_device(sun6i_a31_apb0_gates_clk_dt_ids, &pdev->dev);
  55        if (!device)
  56                return -ENODEV;
  57        data = device->data;
  58
  59        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  60        reg = devm_ioremap_resource(&pdev->dev, r);
  61        if (IS_ERR(reg))
  62                return PTR_ERR(reg);
  63
  64        clk_parent = of_clk_get_parent_name(np, 0);
  65        if (!clk_parent)
  66                return -EINVAL;
  67
  68        clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
  69                                GFP_KERNEL);
  70        if (!clk_data)
  71                return -ENOMEM;
  72
  73        /* Worst-case size approximation and memory allocation */
  74        ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE);
  75        clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1),
  76                                      sizeof(struct clk *), GFP_KERNEL);
  77        if (!clk_data->clks)
  78                return -ENOMEM;
  79
  80        for_each_set_bit(i, data->mask, SUN6I_APB0_GATES_MAX_SIZE) {
  81                of_property_read_string_index(np, "clock-output-names",
  82                                              j, &clk_name);
  83
  84                clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
  85                                                      clk_parent, 0, reg, i,
  86                                                      0, NULL);
  87                WARN_ON(IS_ERR(clk_data->clks[i]));
  88
  89                j++;
  90        }
  91
  92        clk_data->clk_num = ngates + 1;
  93
  94        return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
  95}
  96
  97static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
  98        .driver = {
  99                .name = "sun6i-a31-apb0-gates-clk",
 100                .of_match_table = sun6i_a31_apb0_gates_clk_dt_ids,
 101        },
 102        .probe = sun6i_a31_apb0_gates_clk_probe,
 103};
 104builtin_platform_driver(sun6i_a31_apb0_gates_clk_driver);
 105