1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17#ifndef __TEGRA_CLK_H
18#define __TEGRA_CLK_H
19
20#include <linux/clk-provider.h>
21#include <linux/clkdev.h>
22
23
24
25
26
27
28
29
30struct tegra_clk_sync_source {
31 struct clk_hw hw;
32 unsigned long rate;
33 unsigned long max_rate;
34};
35
36#define to_clk_sync_source(_hw) \
37 container_of(_hw, struct tegra_clk_sync_source, hw)
38
39extern const struct clk_ops tegra_clk_sync_source_ops;
40extern int *periph_clk_enb_refcnt;
41
42struct clk *tegra_clk_register_sync_source(const char *name,
43 unsigned long fixed_rate, unsigned long max_rate);
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67struct tegra_clk_frac_div {
68 struct clk_hw hw;
69 void __iomem *reg;
70 u8 flags;
71 u8 shift;
72 u8 width;
73 u8 frac_width;
74 spinlock_t *lock;
75};
76
77#define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
78
79#define TEGRA_DIVIDER_ROUND_UP BIT(0)
80#define TEGRA_DIVIDER_FIXED BIT(1)
81#define TEGRA_DIVIDER_INT BIT(2)
82#define TEGRA_DIVIDER_UART BIT(3)
83
84extern const struct clk_ops tegra_clk_frac_div_ops;
85struct clk *tegra_clk_register_divider(const char *name,
86 const char *parent_name, void __iomem *reg,
87 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
88 u8 frac_width, spinlock_t *lock);
89struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
90 void __iomem *reg, spinlock_t *lock);
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115struct tegra_clk_pll_freq_table {
116 unsigned long input_rate;
117 unsigned long output_rate;
118 u32 n;
119 u32 m;
120 u8 p;
121 u8 cpcon;
122 u16 sdm_data;
123};
124
125
126
127
128
129
130
131struct pdiv_map {
132 u8 pdiv;
133 u8 hw_val;
134};
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149struct div_nmp {
150 u8 divn_shift;
151 u8 divn_width;
152 u8 divm_shift;
153 u8 divm_width;
154 u8 divp_shift;
155 u8 divp_width;
156 u8 override_divn_shift;
157 u8 override_divm_shift;
158 u8 override_divp_shift;
159};
160
161#define MAX_PLL_MISC_REG_COUNT 6
162
163struct tegra_clk_pll;
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247struct tegra_clk_pll_params {
248 unsigned long input_min;
249 unsigned long input_max;
250 unsigned long cf_min;
251 unsigned long cf_max;
252 unsigned long vco_min;
253 unsigned long vco_max;
254
255 u32 base_reg;
256 u32 misc_reg;
257 u32 lock_reg;
258 u32 lock_mask;
259 u32 lock_enable_bit_idx;
260 u32 iddq_reg;
261 u32 iddq_bit_idx;
262 u32 reset_reg;
263 u32 reset_bit_idx;
264 u32 sdm_din_reg;
265 u32 sdm_din_mask;
266 u32 sdm_ctrl_reg;
267 u32 sdm_ctrl_en_mask;
268 u32 ssc_ctrl_reg;
269 u32 ssc_ctrl_en_mask;
270 u32 aux_reg;
271 u32 dyn_ramp_reg;
272 u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
273 u32 pmc_divnm_reg;
274 u32 pmc_divp_reg;
275 u32 flags;
276 int stepa_shift;
277 int stepb_shift;
278 int lock_delay;
279 int max_p;
280 bool defaults_set;
281 const struct pdiv_map *pdiv_tohw;
282 struct div_nmp *div_nmp;
283 struct tegra_clk_pll_freq_table *freq_table;
284 unsigned long fixed_rate;
285 u16 mdiv_default;
286 u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv);
287 void (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
288 int (*calc_rate)(struct clk_hw *hw,
289 struct tegra_clk_pll_freq_table *cfg,
290 unsigned long rate, unsigned long parent_rate);
291 unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
292 unsigned long parent_rate);
293 void (*set_defaults)(struct tegra_clk_pll *pll);
294 int (*dyn_ramp)(struct tegra_clk_pll *pll,
295 struct tegra_clk_pll_freq_table *cfg);
296};
297
298#define TEGRA_PLL_USE_LOCK BIT(0)
299#define TEGRA_PLL_HAS_CPCON BIT(1)
300#define TEGRA_PLL_SET_LFCON BIT(2)
301#define TEGRA_PLL_SET_DCCON BIT(3)
302#define TEGRA_PLLU BIT(4)
303#define TEGRA_PLLM BIT(5)
304#define TEGRA_PLL_FIXED BIT(6)
305#define TEGRA_PLLE_CONFIGURE BIT(7)
306#define TEGRA_PLL_LOCK_MISC BIT(8)
307#define TEGRA_PLL_BYPASS BIT(9)
308#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
309#define TEGRA_MDIV_NEW BIT(11)
310#define TEGRA_PLLMB BIT(12)
311#define TEGRA_PLL_VCO_OUT BIT(13)
312
313
314
315
316
317
318
319
320
321
322struct tegra_clk_pll {
323 struct clk_hw hw;
324 void __iomem *clk_base;
325 void __iomem *pmc;
326 spinlock_t *lock;
327 struct tegra_clk_pll_params *params;
328};
329
330#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
331
332
333
334
335
336
337
338
339
340struct tegra_audio_clk_info {
341 char *name;
342 struct tegra_clk_pll_params *pll_params;
343 int clk_id;
344 char *parent;
345};
346
347extern const struct clk_ops tegra_clk_pll_ops;
348extern const struct clk_ops tegra_clk_plle_ops;
349struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
350 void __iomem *clk_base, void __iomem *pmc,
351 unsigned long flags, struct tegra_clk_pll_params *pll_params,
352 spinlock_t *lock);
353
354struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
355 void __iomem *clk_base, void __iomem *pmc,
356 unsigned long flags, struct tegra_clk_pll_params *pll_params,
357 spinlock_t *lock);
358
359struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
360 void __iomem *clk_base, void __iomem *pmc,
361 unsigned long flags,
362 struct tegra_clk_pll_params *pll_params,
363 spinlock_t *lock);
364
365struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
366 void __iomem *clk_base, void __iomem *pmc,
367 unsigned long flags,
368 struct tegra_clk_pll_params *pll_params,
369 spinlock_t *lock);
370
371struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
372 void __iomem *clk_base, void __iomem *pmc,
373 unsigned long flags,
374 struct tegra_clk_pll_params *pll_params,
375 spinlock_t *lock);
376
377struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
378 void __iomem *clk_base, void __iomem *pmc,
379 unsigned long flags,
380 struct tegra_clk_pll_params *pll_params,
381 spinlock_t *lock, unsigned long parent_rate);
382
383struct clk *tegra_clk_register_pllre_tegra210(const char *name,
384 const char *parent_name, void __iomem *clk_base,
385 void __iomem *pmc, unsigned long flags,
386 struct tegra_clk_pll_params *pll_params,
387 spinlock_t *lock, unsigned long parent_rate);
388
389struct clk *tegra_clk_register_plle_tegra114(const char *name,
390 const char *parent_name,
391 void __iomem *clk_base, unsigned long flags,
392 struct tegra_clk_pll_params *pll_params,
393 spinlock_t *lock);
394
395struct clk *tegra_clk_register_plle_tegra210(const char *name,
396 const char *parent_name,
397 void __iomem *clk_base, unsigned long flags,
398 struct tegra_clk_pll_params *pll_params,
399 spinlock_t *lock);
400
401struct clk *tegra_clk_register_pllc_tegra210(const char *name,
402 const char *parent_name, void __iomem *clk_base,
403 void __iomem *pmc, unsigned long flags,
404 struct tegra_clk_pll_params *pll_params,
405 spinlock_t *lock);
406
407struct clk *tegra_clk_register_pllss_tegra210(const char *name,
408 const char *parent_name, void __iomem *clk_base,
409 unsigned long flags,
410 struct tegra_clk_pll_params *pll_params,
411 spinlock_t *lock);
412
413struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
414 void __iomem *clk_base, unsigned long flags,
415 struct tegra_clk_pll_params *pll_params,
416 spinlock_t *lock);
417
418struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
419 void __iomem *clk_base, void __iomem *pmc,
420 unsigned long flags,
421 struct tegra_clk_pll_params *pll_params,
422 spinlock_t *lock);
423
424struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
425 void __iomem *clk_base, unsigned long flags,
426 struct tegra_clk_pll_params *pll_params,
427 spinlock_t *lock);
428
429struct clk *tegra_clk_register_pllu_tegra114(const char *name,
430 const char *parent_name,
431 void __iomem *clk_base, unsigned long flags,
432 struct tegra_clk_pll_params *pll_params,
433 spinlock_t *lock);
434
435struct clk *tegra_clk_register_pllu_tegra210(const char *name,
436 const char *parent_name,
437 void __iomem *clk_base, unsigned long flags,
438 struct tegra_clk_pll_params *pll_params,
439 spinlock_t *lock);
440
441
442
443
444
445
446
447
448
449
450
451struct tegra_clk_pll_out {
452 struct clk_hw hw;
453 void __iomem *reg;
454 u8 enb_bit_idx;
455 u8 rst_bit_idx;
456 spinlock_t *lock;
457 u8 flags;
458};
459
460#define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
461
462extern const struct clk_ops tegra_clk_pll_out_ops;
463struct clk *tegra_clk_register_pll_out(const char *name,
464 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
465 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags,
466 spinlock_t *lock);
467
468
469
470
471
472
473
474
475
476
477
478struct tegra_clk_periph_regs {
479 u32 enb_reg;
480 u32 enb_set_reg;
481 u32 enb_clr_reg;
482 u32 rst_reg;
483 u32 rst_set_reg;
484 u32 rst_clr_reg;
485};
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509struct tegra_clk_periph_gate {
510 u32 magic;
511 struct clk_hw hw;
512 void __iomem *clk_base;
513 u8 flags;
514 int clk_num;
515 int *enable_refcnt;
516 const struct tegra_clk_periph_regs *regs;
517};
518
519#define to_clk_periph_gate(_hw) \
520 container_of(_hw, struct tegra_clk_periph_gate, hw)
521
522#define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
523
524#define TEGRA_PERIPH_NO_RESET BIT(0)
525#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
526#define TEGRA_PERIPH_ON_APB BIT(2)
527#define TEGRA_PERIPH_WAR_1005168 BIT(3)
528#define TEGRA_PERIPH_NO_DIV BIT(4)
529#define TEGRA_PERIPH_NO_GATE BIT(5)
530
531extern const struct clk_ops tegra_clk_periph_gate_ops;
532struct clk *tegra_clk_register_periph_gate(const char *name,
533 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
534 unsigned long flags, int clk_num, int *enable_refcnt);
535
536struct tegra_clk_periph_fixed {
537 struct clk_hw hw;
538 void __iomem *base;
539 const struct tegra_clk_periph_regs *regs;
540 unsigned int mul;
541 unsigned int div;
542 unsigned int num;
543};
544
545struct clk *tegra_clk_register_periph_fixed(const char *name,
546 const char *parent,
547 unsigned long flags,
548 void __iomem *base,
549 unsigned int mul,
550 unsigned int div,
551 unsigned int num);
552
553
554
555
556
557
558
559
560
561
562
563
564
565struct tegra_clk_periph {
566 u32 magic;
567 struct clk_hw hw;
568 struct clk_mux mux;
569 struct tegra_clk_frac_div divider;
570 struct tegra_clk_periph_gate gate;
571
572 const struct clk_ops *mux_ops;
573 const struct clk_ops *div_ops;
574 const struct clk_ops *gate_ops;
575};
576
577#define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
578
579#define TEGRA_CLK_PERIPH_MAGIC 0x18221223
580
581extern const struct clk_ops tegra_clk_periph_ops;
582struct clk *tegra_clk_register_periph(const char *name,
583 const char * const *parent_names, int num_parents,
584 struct tegra_clk_periph *periph, void __iomem *clk_base,
585 u32 offset, unsigned long flags);
586struct clk *tegra_clk_register_periph_nodiv(const char *name,
587 const char * const *parent_names, int num_parents,
588 struct tegra_clk_periph *periph, void __iomem *clk_base,
589 u32 offset);
590
591#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
592 _div_shift, _div_width, _div_frac_width, \
593 _div_flags, _clk_num,\
594 _gate_flags, _table, _lock) \
595 { \
596 .mux = { \
597 .flags = _mux_flags, \
598 .shift = _mux_shift, \
599 .mask = _mux_mask, \
600 .table = _table, \
601 .lock = _lock, \
602 }, \
603 .divider = { \
604 .flags = _div_flags, \
605 .shift = _div_shift, \
606 .width = _div_width, \
607 .frac_width = _div_frac_width, \
608 .lock = _lock, \
609 }, \
610 .gate = { \
611 .flags = _gate_flags, \
612 .clk_num = _clk_num, \
613 }, \
614 .mux_ops = &clk_mux_ops, \
615 .div_ops = &tegra_clk_frac_div_ops, \
616 .gate_ops = &tegra_clk_periph_gate_ops, \
617 }
618
619struct tegra_periph_init_data {
620 const char *name;
621 int clk_id;
622 union {
623 const char *const *parent_names;
624 const char *parent_name;
625 } p;
626 int num_parents;
627 struct tegra_clk_periph periph;
628 u32 offset;
629 const char *con_id;
630 const char *dev_id;
631 unsigned long flags;
632};
633
634#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
635 _mux_shift, _mux_mask, _mux_flags, _div_shift, \
636 _div_width, _div_frac_width, _div_flags, \
637 _clk_num, _gate_flags, _clk_id, _table, \
638 _flags, _lock) \
639 { \
640 .name = _name, \
641 .clk_id = _clk_id, \
642 .p.parent_names = _parent_names, \
643 .num_parents = ARRAY_SIZE(_parent_names), \
644 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
645 _mux_flags, _div_shift, \
646 _div_width, _div_frac_width, \
647 _div_flags, _clk_num, \
648 _gate_flags, _table, _lock), \
649 .offset = _offset, \
650 .con_id = _con_id, \
651 .dev_id = _dev_id, \
652 .flags = _flags \
653 }
654
655#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
656 _mux_shift, _mux_width, _mux_flags, _div_shift, \
657 _div_width, _div_frac_width, _div_flags, \
658 _clk_num, _gate_flags, _clk_id) \
659 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
660 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
661 _div_shift, _div_width, _div_frac_width, _div_flags, \
662 _clk_num, _gate_flags, _clk_id,\
663 NULL, 0, NULL)
664
665struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
666 struct tegra_periph_init_data *init);
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683struct tegra_clk_super_mux {
684 struct clk_hw hw;
685 void __iomem *reg;
686 struct tegra_clk_frac_div frac_div;
687 const struct clk_ops *div_ops;
688 u8 width;
689 u8 flags;
690 u8 div2_index;
691 u8 pllx_index;
692 spinlock_t *lock;
693};
694
695#define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
696
697#define TEGRA_DIVIDER_2 BIT(0)
698
699extern const struct clk_ops tegra_clk_super_ops;
700struct clk *tegra_clk_register_super_mux(const char *name,
701 const char **parent_names, u8 num_parents,
702 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
703 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
704struct clk *tegra_clk_register_super_clk(const char *name,
705 const char * const *parent_names, u8 num_parents,
706 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
707 spinlock_t *lock);
708
709
710
711
712
713
714
715struct tegra_clk_init_table {
716 unsigned int clk_id;
717 unsigned int parent_id;
718 unsigned long rate;
719 int state;
720};
721
722
723
724
725
726
727struct tegra_clk_duplicate {
728 int clk_id;
729 struct clk_lookup lookup;
730};
731
732#define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \
733 { \
734 .clk_id = _clk_id, \
735 .lookup = { \
736 .dev_id = _dev, \
737 .con_id = _con, \
738 }, \
739 }
740
741struct tegra_clk {
742 int dt_id;
743 bool present;
744};
745
746struct tegra_devclk {
747 int dt_id;
748 char *dev_id;
749 char *con_id;
750};
751
752void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long),
753 int (*deassert)(unsigned long));
754
755void tegra_init_from_table(struct tegra_clk_init_table *tbl,
756 struct clk *clks[], int clk_max);
757
758void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
759 struct clk *clks[], int clk_max);
760
761const struct tegra_clk_periph_regs *get_reg_bank(int clkid);
762struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
763
764struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
765
766void tegra_add_of_provider(struct device_node *np);
767void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
768
769void tegra_audio_clk_init(void __iomem *clk_base,
770 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
771 struct tegra_audio_clk_info *audio_info,
772 unsigned int num_plls);
773
774void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
775 struct tegra_clk *tegra_clks,
776 struct tegra_clk_pll_params *pll_params);
777
778void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
779void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
780int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
781 unsigned long *input_freqs, unsigned int num,
782 unsigned int clk_m_div, unsigned long *osc_freq,
783 unsigned long *pll_ref_freq);
784void tegra_super_clk_gen4_init(void __iomem *clk_base,
785 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
786 struct tegra_clk_pll_params *pll_params);
787void tegra_super_clk_gen5_init(void __iomem *clk_base,
788 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
789 struct tegra_clk_pll_params *pll_params);
790
791#ifdef CONFIG_TEGRA_CLK_EMC
792struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
793 spinlock_t *lock);
794#else
795static inline struct clk *tegra_clk_register_emc(void __iomem *base,
796 struct device_node *np,
797 spinlock_t *lock)
798{
799 return NULL;
800}
801#endif
802
803void tegra114_clock_tune_cpu_trimmers_high(void);
804void tegra114_clock_tune_cpu_trimmers_low(void);
805void tegra114_clock_tune_cpu_trimmers_init(void);
806void tegra114_clock_assert_dfll_dvco_reset(void);
807void tegra114_clock_deassert_dfll_dvco_reset(void);
808
809typedef void (*tegra_clk_apply_init_table_func)(void);
810extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
811int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
812u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
813int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
814
815#endif
816