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13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/kernel.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/ktime.h>
19#include <linux/hrtimer.h>
20#include <linux/tick.h>
21#include <linux/slab.h>
22#include <linux/sched/cpufreq.h>
23#include <linux/list.h>
24#include <linux/cpu.h>
25#include <linux/cpufreq.h>
26#include <linux/sysfs.h>
27#include <linux/types.h>
28#include <linux/fs.h>
29#include <linux/debugfs.h>
30#include <linux/acpi.h>
31#include <linux/vmalloc.h>
32#include <trace/events/power.h>
33
34#include <asm/div64.h>
35#include <asm/msr.h>
36#include <asm/cpu_device_id.h>
37#include <asm/cpufeature.h>
38#include <asm/intel-family.h>
39
40#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41
42#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
43#define INTEL_CPUFREQ_TRANSITION_DELAY 500
44
45#ifdef CONFIG_ACPI
46#include <acpi/processor.h>
47#include <acpi/cppc_acpi.h>
48#endif
49
50#define FRAC_BITS 8
51#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
52#define fp_toint(X) ((X) >> FRAC_BITS)
53
54#define EXT_BITS 6
55#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
56#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
57#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
58
59static inline int32_t mul_fp(int32_t x, int32_t y)
60{
61 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
62}
63
64static inline int32_t div_fp(s64 x, s64 y)
65{
66 return div64_s64((int64_t)x << FRAC_BITS, y);
67}
68
69static inline int ceiling_fp(int32_t x)
70{
71 int mask, ret;
72
73 ret = fp_toint(x);
74 mask = (1 << FRAC_BITS) - 1;
75 if (x & mask)
76 ret += 1;
77 return ret;
78}
79
80static inline int32_t percent_fp(int percent)
81{
82 return div_fp(percent, 100);
83}
84
85static inline u64 mul_ext_fp(u64 x, u64 y)
86{
87 return (x * y) >> EXT_FRAC_BITS;
88}
89
90static inline u64 div_ext_fp(u64 x, u64 y)
91{
92 return div64_u64(x << EXT_FRAC_BITS, y);
93}
94
95static inline int32_t percent_ext_fp(int percent)
96{
97 return div_ext_fp(percent, 100);
98}
99
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117
118struct sample {
119 int32_t core_avg_perf;
120 int32_t busy_scaled;
121 u64 aperf;
122 u64 mperf;
123 u64 tsc;
124 u64 time;
125};
126
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142
143struct pstate_data {
144 int current_pstate;
145 int min_pstate;
146 int max_pstate;
147 int max_pstate_physical;
148 int scaling;
149 int turbo_pstate;
150 unsigned int max_freq;
151 unsigned int turbo_freq;
152};
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166
167struct vid_data {
168 int min;
169 int max;
170 int turbo;
171 int32_t ratio;
172};
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185
186struct global_params {
187 bool no_turbo;
188 bool turbo_disabled;
189 int max_perf_pct;
190 int min_perf_pct;
191};
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228struct cpudata {
229 int cpu;
230
231 unsigned int policy;
232 struct update_util_data update_util;
233 bool update_util_set;
234
235 struct pstate_data pstate;
236 struct vid_data vid;
237
238 u64 last_update;
239 u64 last_sample_time;
240 u64 aperf_mperf_shift;
241 u64 prev_aperf;
242 u64 prev_mperf;
243 u64 prev_tsc;
244 u64 prev_cummulative_iowait;
245 struct sample sample;
246 int32_t min_perf_ratio;
247 int32_t max_perf_ratio;
248#ifdef CONFIG_ACPI
249 struct acpi_processor_performance acpi_perf_data;
250 bool valid_pss_table;
251#endif
252 unsigned int iowait_boost;
253 s16 epp_powersave;
254 s16 epp_policy;
255 s16 epp_default;
256 s16 epp_saved;
257};
258
259static struct cpudata **all_cpu_data;
260
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273
274struct pstate_funcs {
275 int (*get_max)(void);
276 int (*get_max_physical)(void);
277 int (*get_min)(void);
278 int (*get_turbo)(void);
279 int (*get_scaling)(void);
280 int (*get_aperf_mperf_shift)(void);
281 u64 (*get_val)(struct cpudata*, int pstate);
282 void (*get_vid)(struct cpudata *);
283};
284
285static struct pstate_funcs pstate_funcs __read_mostly;
286
287static int hwp_active __read_mostly;
288static bool per_cpu_limits __read_mostly;
289
290static struct cpufreq_driver *intel_pstate_driver __read_mostly;
291
292#ifdef CONFIG_ACPI
293static bool acpi_ppc;
294#endif
295
296static struct global_params global;
297
298static DEFINE_MUTEX(intel_pstate_driver_lock);
299static DEFINE_MUTEX(intel_pstate_limits_lock);
300
301#ifdef CONFIG_ACPI
302
303static bool intel_pstate_get_ppc_enable_status(void)
304{
305 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
306 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
307 return true;
308
309 return acpi_ppc;
310}
311
312#ifdef CONFIG_ACPI_CPPC_LIB
313
314
315static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
316{
317 sched_set_itmt_support();
318}
319
320static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
321
322static void intel_pstate_set_itmt_prio(int cpu)
323{
324 struct cppc_perf_caps cppc_perf;
325 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
326 int ret;
327
328 ret = cppc_get_perf_caps(cpu, &cppc_perf);
329 if (ret)
330 return;
331
332
333
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335
336
337 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
338
339 if (max_highest_perf <= min_highest_perf) {
340 if (cppc_perf.highest_perf > max_highest_perf)
341 max_highest_perf = cppc_perf.highest_perf;
342
343 if (cppc_perf.highest_perf < min_highest_perf)
344 min_highest_perf = cppc_perf.highest_perf;
345
346 if (max_highest_perf > min_highest_perf) {
347
348
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353 schedule_work(&sched_itmt_work);
354 }
355 }
356}
357#else
358static void intel_pstate_set_itmt_prio(int cpu)
359{
360}
361#endif
362
363static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
364{
365 struct cpudata *cpu;
366 int ret;
367 int i;
368
369 if (hwp_active) {
370 intel_pstate_set_itmt_prio(policy->cpu);
371 return;
372 }
373
374 if (!intel_pstate_get_ppc_enable_status())
375 return;
376
377 cpu = all_cpu_data[policy->cpu];
378
379 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
380 policy->cpu);
381 if (ret)
382 return;
383
384
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387
388
389 if (cpu->acpi_perf_data.control_register.space_id !=
390 ACPI_ADR_SPACE_FIXED_HARDWARE)
391 goto err;
392
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394
395
396
397 if (cpu->acpi_perf_data.state_count < 2)
398 goto err;
399
400 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
401 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
402 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
403 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
404 (u32) cpu->acpi_perf_data.states[i].core_frequency,
405 (u32) cpu->acpi_perf_data.states[i].power,
406 (u32) cpu->acpi_perf_data.states[i].control);
407 }
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418
419
420 if (!global.turbo_disabled)
421 cpu->acpi_perf_data.states[0].core_frequency =
422 policy->cpuinfo.max_freq / 1000;
423 cpu->valid_pss_table = true;
424 pr_debug("_PPC limits will be enforced\n");
425
426 return;
427
428 err:
429 cpu->valid_pss_table = false;
430 acpi_processor_unregister_performance(policy->cpu);
431}
432
433static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
434{
435 struct cpudata *cpu;
436
437 cpu = all_cpu_data[policy->cpu];
438 if (!cpu->valid_pss_table)
439 return;
440
441 acpi_processor_unregister_performance(policy->cpu);
442}
443#else
444static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
445{
446}
447
448static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
449{
450}
451#endif
452
453static inline void update_turbo_state(void)
454{
455 u64 misc_en;
456 struct cpudata *cpu;
457
458 cpu = all_cpu_data[0];
459 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
460 global.turbo_disabled =
461 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
462 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
463}
464
465static int min_perf_pct_min(void)
466{
467 struct cpudata *cpu = all_cpu_data[0];
468 int turbo_pstate = cpu->pstate.turbo_pstate;
469
470 return turbo_pstate ?
471 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
472}
473
474static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
475{
476 u64 epb;
477 int ret;
478
479 if (!static_cpu_has(X86_FEATURE_EPB))
480 return -ENXIO;
481
482 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
483 if (ret)
484 return (s16)ret;
485
486 return (s16)(epb & 0x0f);
487}
488
489static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
490{
491 s16 epp;
492
493 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
494
495
496
497
498 if (!hwp_req_data) {
499 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
500 &hwp_req_data);
501 if (epp)
502 return epp;
503 }
504 epp = (hwp_req_data >> 24) & 0xff;
505 } else {
506
507 epp = intel_pstate_get_epb(cpu_data);
508 }
509
510 return epp;
511}
512
513static int intel_pstate_set_epb(int cpu, s16 pref)
514{
515 u64 epb;
516 int ret;
517
518 if (!static_cpu_has(X86_FEATURE_EPB))
519 return -ENXIO;
520
521 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
522 if (ret)
523 return ret;
524
525 epb = (epb & ~0x0f) | pref;
526 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
527
528 return 0;
529}
530
531
532
533
534
535
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540
541
542static const char * const energy_perf_strings[] = {
543 "default",
544 "performance",
545 "balance_performance",
546 "balance_power",
547 "power",
548 NULL
549};
550static const unsigned int epp_values[] = {
551 HWP_EPP_PERFORMANCE,
552 HWP_EPP_BALANCE_PERFORMANCE,
553 HWP_EPP_BALANCE_POWERSAVE,
554 HWP_EPP_POWERSAVE
555};
556
557static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
558{
559 s16 epp;
560 int index = -EINVAL;
561
562 epp = intel_pstate_get_epp(cpu_data, 0);
563 if (epp < 0)
564 return epp;
565
566 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
567 if (epp == HWP_EPP_PERFORMANCE)
568 return 1;
569 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
570 return 2;
571 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
572 return 3;
573 else
574 return 4;
575 } else if (static_cpu_has(X86_FEATURE_EPB)) {
576
577
578
579
580
581
582
583
584
585
586 index = (epp >> 2) + 1;
587 }
588
589 return index;
590}
591
592static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
593 int pref_index)
594{
595 int epp = -EINVAL;
596 int ret;
597
598 if (!pref_index)
599 epp = cpu_data->epp_default;
600
601 mutex_lock(&intel_pstate_limits_lock);
602
603 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
604 u64 value;
605
606 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
607 if (ret)
608 goto return_pref;
609
610 value &= ~GENMASK_ULL(31, 24);
611
612 if (epp == -EINVAL)
613 epp = epp_values[pref_index - 1];
614
615 value |= (u64)epp << 24;
616 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
617 } else {
618 if (epp == -EINVAL)
619 epp = (pref_index - 1) << 2;
620 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
621 }
622return_pref:
623 mutex_unlock(&intel_pstate_limits_lock);
624
625 return ret;
626}
627
628static ssize_t show_energy_performance_available_preferences(
629 struct cpufreq_policy *policy, char *buf)
630{
631 int i = 0;
632 int ret = 0;
633
634 while (energy_perf_strings[i] != NULL)
635 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
636
637 ret += sprintf(&buf[ret], "\n");
638
639 return ret;
640}
641
642cpufreq_freq_attr_ro(energy_performance_available_preferences);
643
644static ssize_t store_energy_performance_preference(
645 struct cpufreq_policy *policy, const char *buf, size_t count)
646{
647 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
648 char str_preference[21];
649 int ret, i = 0;
650
651 ret = sscanf(buf, "%20s", str_preference);
652 if (ret != 1)
653 return -EINVAL;
654
655 while (energy_perf_strings[i] != NULL) {
656 if (!strcmp(str_preference, energy_perf_strings[i])) {
657 intel_pstate_set_energy_pref_index(cpu_data, i);
658 return count;
659 }
660 ++i;
661 }
662
663 return -EINVAL;
664}
665
666static ssize_t show_energy_performance_preference(
667 struct cpufreq_policy *policy, char *buf)
668{
669 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
670 int preference;
671
672 preference = intel_pstate_get_energy_pref_index(cpu_data);
673 if (preference < 0)
674 return preference;
675
676 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
677}
678
679cpufreq_freq_attr_rw(energy_performance_preference);
680
681static struct freq_attr *hwp_cpufreq_attrs[] = {
682 &energy_performance_preference,
683 &energy_performance_available_preferences,
684 NULL,
685};
686
687static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
688 int *current_max)
689{
690 u64 cap;
691
692 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
693 if (global.no_turbo)
694 *current_max = HWP_GUARANTEED_PERF(cap);
695 else
696 *current_max = HWP_HIGHEST_PERF(cap);
697
698 *phy_max = HWP_HIGHEST_PERF(cap);
699}
700
701static void intel_pstate_hwp_set(unsigned int cpu)
702{
703 struct cpudata *cpu_data = all_cpu_data[cpu];
704 int max, min;
705 u64 value;
706 s16 epp;
707
708 max = cpu_data->max_perf_ratio;
709 min = cpu_data->min_perf_ratio;
710
711 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
712 min = max;
713
714 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
715
716 value &= ~HWP_MIN_PERF(~0L);
717 value |= HWP_MIN_PERF(min);
718
719 value &= ~HWP_MAX_PERF(~0L);
720 value |= HWP_MAX_PERF(max);
721
722 if (cpu_data->epp_policy == cpu_data->policy)
723 goto skip_epp;
724
725 cpu_data->epp_policy = cpu_data->policy;
726
727 if (cpu_data->epp_saved >= 0) {
728 epp = cpu_data->epp_saved;
729 cpu_data->epp_saved = -EINVAL;
730 goto update_epp;
731 }
732
733 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
734 epp = intel_pstate_get_epp(cpu_data, value);
735 cpu_data->epp_powersave = epp;
736
737 if (epp < 0)
738 goto skip_epp;
739
740 epp = 0;
741 } else {
742
743 if (cpu_data->epp_powersave < 0)
744 goto skip_epp;
745
746
747
748
749
750
751
752
753 epp = intel_pstate_get_epp(cpu_data, value);
754 if (epp)
755 goto skip_epp;
756
757 epp = cpu_data->epp_powersave;
758 }
759update_epp:
760 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
761 value &= ~GENMASK_ULL(31, 24);
762 value |= (u64)epp << 24;
763 } else {
764 intel_pstate_set_epb(cpu, epp);
765 }
766skip_epp:
767 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
768}
769
770static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
771{
772 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
773
774 if (!hwp_active)
775 return 0;
776
777 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
778
779 return 0;
780}
781
782static void intel_pstate_hwp_enable(struct cpudata *cpudata);
783
784static int intel_pstate_resume(struct cpufreq_policy *policy)
785{
786 if (!hwp_active)
787 return 0;
788
789 mutex_lock(&intel_pstate_limits_lock);
790
791 if (policy->cpu == 0)
792 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
793
794 all_cpu_data[policy->cpu]->epp_policy = 0;
795 intel_pstate_hwp_set(policy->cpu);
796
797 mutex_unlock(&intel_pstate_limits_lock);
798
799 return 0;
800}
801
802static void intel_pstate_update_policies(void)
803{
804 int cpu;
805
806 for_each_possible_cpu(cpu)
807 cpufreq_update_policy(cpu);
808}
809
810
811#define show_one(file_name, object) \
812 static ssize_t show_##file_name \
813 (struct kobject *kobj, struct attribute *attr, char *buf) \
814 { \
815 return sprintf(buf, "%u\n", global.object); \
816 }
817
818static ssize_t intel_pstate_show_status(char *buf);
819static int intel_pstate_update_status(const char *buf, size_t size);
820
821static ssize_t show_status(struct kobject *kobj,
822 struct attribute *attr, char *buf)
823{
824 ssize_t ret;
825
826 mutex_lock(&intel_pstate_driver_lock);
827 ret = intel_pstate_show_status(buf);
828 mutex_unlock(&intel_pstate_driver_lock);
829
830 return ret;
831}
832
833static ssize_t store_status(struct kobject *a, struct attribute *b,
834 const char *buf, size_t count)
835{
836 char *p = memchr(buf, '\n', count);
837 int ret;
838
839 mutex_lock(&intel_pstate_driver_lock);
840 ret = intel_pstate_update_status(buf, p ? p - buf : count);
841 mutex_unlock(&intel_pstate_driver_lock);
842
843 return ret < 0 ? ret : count;
844}
845
846static ssize_t show_turbo_pct(struct kobject *kobj,
847 struct attribute *attr, char *buf)
848{
849 struct cpudata *cpu;
850 int total, no_turbo, turbo_pct;
851 uint32_t turbo_fp;
852
853 mutex_lock(&intel_pstate_driver_lock);
854
855 if (!intel_pstate_driver) {
856 mutex_unlock(&intel_pstate_driver_lock);
857 return -EAGAIN;
858 }
859
860 cpu = all_cpu_data[0];
861
862 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
863 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
864 turbo_fp = div_fp(no_turbo, total);
865 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
866
867 mutex_unlock(&intel_pstate_driver_lock);
868
869 return sprintf(buf, "%u\n", turbo_pct);
870}
871
872static ssize_t show_num_pstates(struct kobject *kobj,
873 struct attribute *attr, char *buf)
874{
875 struct cpudata *cpu;
876 int total;
877
878 mutex_lock(&intel_pstate_driver_lock);
879
880 if (!intel_pstate_driver) {
881 mutex_unlock(&intel_pstate_driver_lock);
882 return -EAGAIN;
883 }
884
885 cpu = all_cpu_data[0];
886 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
887
888 mutex_unlock(&intel_pstate_driver_lock);
889
890 return sprintf(buf, "%u\n", total);
891}
892
893static ssize_t show_no_turbo(struct kobject *kobj,
894 struct attribute *attr, char *buf)
895{
896 ssize_t ret;
897
898 mutex_lock(&intel_pstate_driver_lock);
899
900 if (!intel_pstate_driver) {
901 mutex_unlock(&intel_pstate_driver_lock);
902 return -EAGAIN;
903 }
904
905 update_turbo_state();
906 if (global.turbo_disabled)
907 ret = sprintf(buf, "%u\n", global.turbo_disabled);
908 else
909 ret = sprintf(buf, "%u\n", global.no_turbo);
910
911 mutex_unlock(&intel_pstate_driver_lock);
912
913 return ret;
914}
915
916static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
917 const char *buf, size_t count)
918{
919 unsigned int input;
920 int ret;
921
922 ret = sscanf(buf, "%u", &input);
923 if (ret != 1)
924 return -EINVAL;
925
926 mutex_lock(&intel_pstate_driver_lock);
927
928 if (!intel_pstate_driver) {
929 mutex_unlock(&intel_pstate_driver_lock);
930 return -EAGAIN;
931 }
932
933 mutex_lock(&intel_pstate_limits_lock);
934
935 update_turbo_state();
936 if (global.turbo_disabled) {
937 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
938 mutex_unlock(&intel_pstate_limits_lock);
939 mutex_unlock(&intel_pstate_driver_lock);
940 return -EPERM;
941 }
942
943 global.no_turbo = clamp_t(int, input, 0, 1);
944
945 if (global.no_turbo) {
946 struct cpudata *cpu = all_cpu_data[0];
947 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
948
949
950 if (global.min_perf_pct > pct)
951 global.min_perf_pct = pct;
952 }
953
954 mutex_unlock(&intel_pstate_limits_lock);
955
956 intel_pstate_update_policies();
957
958 mutex_unlock(&intel_pstate_driver_lock);
959
960 return count;
961}
962
963static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
964 const char *buf, size_t count)
965{
966 unsigned int input;
967 int ret;
968
969 ret = sscanf(buf, "%u", &input);
970 if (ret != 1)
971 return -EINVAL;
972
973 mutex_lock(&intel_pstate_driver_lock);
974
975 if (!intel_pstate_driver) {
976 mutex_unlock(&intel_pstate_driver_lock);
977 return -EAGAIN;
978 }
979
980 mutex_lock(&intel_pstate_limits_lock);
981
982 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
983
984 mutex_unlock(&intel_pstate_limits_lock);
985
986 intel_pstate_update_policies();
987
988 mutex_unlock(&intel_pstate_driver_lock);
989
990 return count;
991}
992
993static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
994 const char *buf, size_t count)
995{
996 unsigned int input;
997 int ret;
998
999 ret = sscanf(buf, "%u", &input);
1000 if (ret != 1)
1001 return -EINVAL;
1002
1003 mutex_lock(&intel_pstate_driver_lock);
1004
1005 if (!intel_pstate_driver) {
1006 mutex_unlock(&intel_pstate_driver_lock);
1007 return -EAGAIN;
1008 }
1009
1010 mutex_lock(&intel_pstate_limits_lock);
1011
1012 global.min_perf_pct = clamp_t(int, input,
1013 min_perf_pct_min(), global.max_perf_pct);
1014
1015 mutex_unlock(&intel_pstate_limits_lock);
1016
1017 intel_pstate_update_policies();
1018
1019 mutex_unlock(&intel_pstate_driver_lock);
1020
1021 return count;
1022}
1023
1024show_one(max_perf_pct, max_perf_pct);
1025show_one(min_perf_pct, min_perf_pct);
1026
1027define_one_global_rw(status);
1028define_one_global_rw(no_turbo);
1029define_one_global_rw(max_perf_pct);
1030define_one_global_rw(min_perf_pct);
1031define_one_global_ro(turbo_pct);
1032define_one_global_ro(num_pstates);
1033
1034static struct attribute *intel_pstate_attributes[] = {
1035 &status.attr,
1036 &no_turbo.attr,
1037 &turbo_pct.attr,
1038 &num_pstates.attr,
1039 NULL
1040};
1041
1042static const struct attribute_group intel_pstate_attr_group = {
1043 .attrs = intel_pstate_attributes,
1044};
1045
1046static void __init intel_pstate_sysfs_expose_params(void)
1047{
1048 struct kobject *intel_pstate_kobject;
1049 int rc;
1050
1051 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1052 &cpu_subsys.dev_root->kobj);
1053 if (WARN_ON(!intel_pstate_kobject))
1054 return;
1055
1056 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1057 if (WARN_ON(rc))
1058 return;
1059
1060
1061
1062
1063
1064 if (per_cpu_limits)
1065 return;
1066
1067 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1068 WARN_ON(rc);
1069
1070 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1071 WARN_ON(rc);
1072
1073}
1074
1075
1076static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1077{
1078
1079 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1080 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1081
1082 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1083 cpudata->epp_policy = 0;
1084 if (cpudata->epp_default == -EINVAL)
1085 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1086}
1087
1088#define MSR_IA32_POWER_CTL_BIT_EE 19
1089
1090
1091static void intel_pstate_disable_ee(int cpu)
1092{
1093 u64 power_ctl;
1094 int ret;
1095
1096 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1097 if (ret)
1098 return;
1099
1100 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1101 pr_info("Disabling energy efficiency optimization\n");
1102 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1103 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1104 }
1105}
1106
1107static int atom_get_min_pstate(void)
1108{
1109 u64 value;
1110
1111 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1112 return (value >> 8) & 0x7F;
1113}
1114
1115static int atom_get_max_pstate(void)
1116{
1117 u64 value;
1118
1119 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1120 return (value >> 16) & 0x7F;
1121}
1122
1123static int atom_get_turbo_pstate(void)
1124{
1125 u64 value;
1126
1127 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1128 return value & 0x7F;
1129}
1130
1131static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1132{
1133 u64 val;
1134 int32_t vid_fp;
1135 u32 vid;
1136
1137 val = (u64)pstate << 8;
1138 if (global.no_turbo && !global.turbo_disabled)
1139 val |= (u64)1 << 32;
1140
1141 vid_fp = cpudata->vid.min + mul_fp(
1142 int_tofp(pstate - cpudata->pstate.min_pstate),
1143 cpudata->vid.ratio);
1144
1145 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1146 vid = ceiling_fp(vid_fp);
1147
1148 if (pstate > cpudata->pstate.max_pstate)
1149 vid = cpudata->vid.turbo;
1150
1151 return val | vid;
1152}
1153
1154static int silvermont_get_scaling(void)
1155{
1156 u64 value;
1157 int i;
1158
1159 static int silvermont_freq_table[] = {
1160 83300, 100000, 133300, 116700, 80000};
1161
1162 rdmsrl(MSR_FSB_FREQ, value);
1163 i = value & 0x7;
1164 WARN_ON(i > 4);
1165
1166 return silvermont_freq_table[i];
1167}
1168
1169static int airmont_get_scaling(void)
1170{
1171 u64 value;
1172 int i;
1173
1174 static int airmont_freq_table[] = {
1175 83300, 100000, 133300, 116700, 80000,
1176 93300, 90000, 88900, 87500};
1177
1178 rdmsrl(MSR_FSB_FREQ, value);
1179 i = value & 0xF;
1180 WARN_ON(i > 8);
1181
1182 return airmont_freq_table[i];
1183}
1184
1185static void atom_get_vid(struct cpudata *cpudata)
1186{
1187 u64 value;
1188
1189 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1190 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1191 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1192 cpudata->vid.ratio = div_fp(
1193 cpudata->vid.max - cpudata->vid.min,
1194 int_tofp(cpudata->pstate.max_pstate -
1195 cpudata->pstate.min_pstate));
1196
1197 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1198 cpudata->vid.turbo = value & 0x7f;
1199}
1200
1201static int core_get_min_pstate(void)
1202{
1203 u64 value;
1204
1205 rdmsrl(MSR_PLATFORM_INFO, value);
1206 return (value >> 40) & 0xFF;
1207}
1208
1209static int core_get_max_pstate_physical(void)
1210{
1211 u64 value;
1212
1213 rdmsrl(MSR_PLATFORM_INFO, value);
1214 return (value >> 8) & 0xFF;
1215}
1216
1217static int core_get_tdp_ratio(u64 plat_info)
1218{
1219
1220 if (plat_info & 0x600000000) {
1221 u64 tdp_ctrl;
1222 u64 tdp_ratio;
1223 int tdp_msr;
1224 int err;
1225
1226
1227 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1228 if (err)
1229 return err;
1230
1231
1232 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1233 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1234 if (err)
1235 return err;
1236
1237
1238 if (tdp_ctrl & 0x03)
1239 tdp_ratio >>= 16;
1240
1241 tdp_ratio &= 0xff;
1242 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1243
1244 return (int)tdp_ratio;
1245 }
1246
1247 return -ENXIO;
1248}
1249
1250static int core_get_max_pstate(void)
1251{
1252 u64 tar;
1253 u64 plat_info;
1254 int max_pstate;
1255 int tdp_ratio;
1256 int err;
1257
1258 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1259 max_pstate = (plat_info >> 8) & 0xFF;
1260
1261 tdp_ratio = core_get_tdp_ratio(plat_info);
1262 if (tdp_ratio <= 0)
1263 return max_pstate;
1264
1265 if (hwp_active) {
1266
1267 return tdp_ratio;
1268 }
1269
1270 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1271 if (!err) {
1272 int tar_levels;
1273
1274
1275 tar_levels = tar & 0xff;
1276 if (tdp_ratio - 1 == tar_levels) {
1277 max_pstate = tar_levels;
1278 pr_debug("max_pstate=TAC %x\n", max_pstate);
1279 }
1280 }
1281
1282 return max_pstate;
1283}
1284
1285static int core_get_turbo_pstate(void)
1286{
1287 u64 value;
1288 int nont, ret;
1289
1290 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1291 nont = core_get_max_pstate();
1292 ret = (value) & 255;
1293 if (ret <= nont)
1294 ret = nont;
1295 return ret;
1296}
1297
1298static inline int core_get_scaling(void)
1299{
1300 return 100000;
1301}
1302
1303static u64 core_get_val(struct cpudata *cpudata, int pstate)
1304{
1305 u64 val;
1306
1307 val = (u64)pstate << 8;
1308 if (global.no_turbo && !global.turbo_disabled)
1309 val |= (u64)1 << 32;
1310
1311 return val;
1312}
1313
1314static int knl_get_aperf_mperf_shift(void)
1315{
1316 return 10;
1317}
1318
1319static int knl_get_turbo_pstate(void)
1320{
1321 u64 value;
1322 int nont, ret;
1323
1324 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1325 nont = core_get_max_pstate();
1326 ret = (((value) >> 8) & 0xFF);
1327 if (ret <= nont)
1328 ret = nont;
1329 return ret;
1330}
1331
1332static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1333{
1334 return global.no_turbo || global.turbo_disabled ?
1335 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1336}
1337
1338static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1339{
1340 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1341 cpu->pstate.current_pstate = pstate;
1342
1343
1344
1345
1346
1347 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1348 pstate_funcs.get_val(cpu, pstate));
1349}
1350
1351static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1352{
1353 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1354}
1355
1356static void intel_pstate_max_within_limits(struct cpudata *cpu)
1357{
1358 int pstate;
1359
1360 update_turbo_state();
1361 pstate = intel_pstate_get_base_pstate(cpu);
1362 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1363 intel_pstate_set_pstate(cpu, pstate);
1364}
1365
1366static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1367{
1368 cpu->pstate.min_pstate = pstate_funcs.get_min();
1369 cpu->pstate.max_pstate = pstate_funcs.get_max();
1370 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1371 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1372 cpu->pstate.scaling = pstate_funcs.get_scaling();
1373 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1374 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1375
1376 if (pstate_funcs.get_aperf_mperf_shift)
1377 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1378
1379 if (pstate_funcs.get_vid)
1380 pstate_funcs.get_vid(cpu);
1381
1382 intel_pstate_set_min_pstate(cpu);
1383}
1384
1385static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1386{
1387 struct sample *sample = &cpu->sample;
1388
1389 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1390}
1391
1392static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1393{
1394 u64 aperf, mperf;
1395 unsigned long flags;
1396 u64 tsc;
1397
1398 local_irq_save(flags);
1399 rdmsrl(MSR_IA32_APERF, aperf);
1400 rdmsrl(MSR_IA32_MPERF, mperf);
1401 tsc = rdtsc();
1402 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1403 local_irq_restore(flags);
1404 return false;
1405 }
1406 local_irq_restore(flags);
1407
1408 cpu->last_sample_time = cpu->sample.time;
1409 cpu->sample.time = time;
1410 cpu->sample.aperf = aperf;
1411 cpu->sample.mperf = mperf;
1412 cpu->sample.tsc = tsc;
1413 cpu->sample.aperf -= cpu->prev_aperf;
1414 cpu->sample.mperf -= cpu->prev_mperf;
1415 cpu->sample.tsc -= cpu->prev_tsc;
1416
1417 cpu->prev_aperf = aperf;
1418 cpu->prev_mperf = mperf;
1419 cpu->prev_tsc = tsc;
1420
1421
1422
1423
1424
1425
1426
1427 if (cpu->last_sample_time) {
1428 intel_pstate_calc_avg_perf(cpu);
1429 return true;
1430 }
1431 return false;
1432}
1433
1434static inline int32_t get_avg_frequency(struct cpudata *cpu)
1435{
1436 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1437}
1438
1439static inline int32_t get_avg_pstate(struct cpudata *cpu)
1440{
1441 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1442 cpu->sample.core_avg_perf);
1443}
1444
1445static inline int32_t get_target_pstate(struct cpudata *cpu)
1446{
1447 struct sample *sample = &cpu->sample;
1448 int32_t busy_frac, boost;
1449 int target, avg_pstate;
1450
1451 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1452 sample->tsc);
1453
1454 boost = cpu->iowait_boost;
1455 cpu->iowait_boost >>= 1;
1456
1457 if (busy_frac < boost)
1458 busy_frac = boost;
1459
1460 sample->busy_scaled = busy_frac * 100;
1461
1462 target = global.no_turbo || global.turbo_disabled ?
1463 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1464 target += target >> 2;
1465 target = mul_fp(target, busy_frac);
1466 if (target < cpu->pstate.min_pstate)
1467 target = cpu->pstate.min_pstate;
1468
1469
1470
1471
1472
1473
1474
1475
1476 avg_pstate = get_avg_pstate(cpu);
1477 if (avg_pstate > target)
1478 target += (avg_pstate - target) >> 1;
1479
1480 return target;
1481}
1482
1483static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1484{
1485 int max_pstate = intel_pstate_get_base_pstate(cpu);
1486 int min_pstate;
1487
1488 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1489 max_pstate = max(min_pstate, cpu->max_perf_ratio);
1490 return clamp_t(int, pstate, min_pstate, max_pstate);
1491}
1492
1493static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1494{
1495 if (pstate == cpu->pstate.current_pstate)
1496 return;
1497
1498 cpu->pstate.current_pstate = pstate;
1499 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1500}
1501
1502static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1503{
1504 int from = cpu->pstate.current_pstate;
1505 struct sample *sample;
1506 int target_pstate;
1507
1508 update_turbo_state();
1509
1510 target_pstate = get_target_pstate(cpu);
1511 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1512 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1513 intel_pstate_update_pstate(cpu, target_pstate);
1514
1515 sample = &cpu->sample;
1516 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1517 fp_toint(sample->busy_scaled),
1518 from,
1519 cpu->pstate.current_pstate,
1520 sample->mperf,
1521 sample->aperf,
1522 sample->tsc,
1523 get_avg_frequency(cpu),
1524 fp_toint(cpu->iowait_boost * 100));
1525}
1526
1527static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1528 unsigned int flags)
1529{
1530 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1531 u64 delta_ns;
1532
1533
1534 if (smp_processor_id() != cpu->cpu)
1535 return;
1536
1537 if (flags & SCHED_CPUFREQ_IOWAIT) {
1538 cpu->iowait_boost = int_tofp(1);
1539 cpu->last_update = time;
1540
1541
1542
1543
1544 if (fp_toint(cpu->sample.busy_scaled) == 100)
1545 return;
1546
1547 goto set_pstate;
1548 } else if (cpu->iowait_boost) {
1549
1550 delta_ns = time - cpu->last_update;
1551 if (delta_ns > TICK_NSEC)
1552 cpu->iowait_boost = 0;
1553 }
1554 cpu->last_update = time;
1555 delta_ns = time - cpu->sample.time;
1556 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1557 return;
1558
1559set_pstate:
1560 if (intel_pstate_sample(cpu, time))
1561 intel_pstate_adjust_pstate(cpu);
1562}
1563
1564static struct pstate_funcs core_funcs = {
1565 .get_max = core_get_max_pstate,
1566 .get_max_physical = core_get_max_pstate_physical,
1567 .get_min = core_get_min_pstate,
1568 .get_turbo = core_get_turbo_pstate,
1569 .get_scaling = core_get_scaling,
1570 .get_val = core_get_val,
1571};
1572
1573static const struct pstate_funcs silvermont_funcs = {
1574 .get_max = atom_get_max_pstate,
1575 .get_max_physical = atom_get_max_pstate,
1576 .get_min = atom_get_min_pstate,
1577 .get_turbo = atom_get_turbo_pstate,
1578 .get_val = atom_get_val,
1579 .get_scaling = silvermont_get_scaling,
1580 .get_vid = atom_get_vid,
1581};
1582
1583static const struct pstate_funcs airmont_funcs = {
1584 .get_max = atom_get_max_pstate,
1585 .get_max_physical = atom_get_max_pstate,
1586 .get_min = atom_get_min_pstate,
1587 .get_turbo = atom_get_turbo_pstate,
1588 .get_val = atom_get_val,
1589 .get_scaling = airmont_get_scaling,
1590 .get_vid = atom_get_vid,
1591};
1592
1593static const struct pstate_funcs knl_funcs = {
1594 .get_max = core_get_max_pstate,
1595 .get_max_physical = core_get_max_pstate_physical,
1596 .get_min = core_get_min_pstate,
1597 .get_turbo = knl_get_turbo_pstate,
1598 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1599 .get_scaling = core_get_scaling,
1600 .get_val = core_get_val,
1601};
1602
1603#define ICPU(model, policy) \
1604 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1605 (unsigned long)&policy }
1606
1607static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1608 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1609 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1610 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
1611 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1612 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1613 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1614 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1615 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1616 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1617 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1618 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1619 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1620 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1621 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1622 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1623 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1624 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1625 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1626 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
1627 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, core_funcs),
1628 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1629 {}
1630};
1631MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1632
1633static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1634 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1635 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1636 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1637 {}
1638};
1639
1640static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1641 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1642 {}
1643};
1644
1645static int intel_pstate_init_cpu(unsigned int cpunum)
1646{
1647 struct cpudata *cpu;
1648
1649 cpu = all_cpu_data[cpunum];
1650
1651 if (!cpu) {
1652 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1653 if (!cpu)
1654 return -ENOMEM;
1655
1656 all_cpu_data[cpunum] = cpu;
1657
1658 cpu->epp_default = -EINVAL;
1659 cpu->epp_powersave = -EINVAL;
1660 cpu->epp_saved = -EINVAL;
1661 }
1662
1663 cpu = all_cpu_data[cpunum];
1664
1665 cpu->cpu = cpunum;
1666
1667 if (hwp_active) {
1668 const struct x86_cpu_id *id;
1669
1670 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1671 if (id)
1672 intel_pstate_disable_ee(cpunum);
1673
1674 intel_pstate_hwp_enable(cpu);
1675 }
1676
1677 intel_pstate_get_cpu_pstates(cpu);
1678
1679 pr_debug("controlling: cpu %d\n", cpunum);
1680
1681 return 0;
1682}
1683
1684static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1685{
1686 struct cpudata *cpu = all_cpu_data[cpu_num];
1687
1688 if (hwp_active)
1689 return;
1690
1691 if (cpu->update_util_set)
1692 return;
1693
1694
1695 cpu->sample.time = 0;
1696 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1697 intel_pstate_update_util);
1698 cpu->update_util_set = true;
1699}
1700
1701static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1702{
1703 struct cpudata *cpu_data = all_cpu_data[cpu];
1704
1705 if (!cpu_data->update_util_set)
1706 return;
1707
1708 cpufreq_remove_update_util_hook(cpu);
1709 cpu_data->update_util_set = false;
1710 synchronize_sched();
1711}
1712
1713static int intel_pstate_get_max_freq(struct cpudata *cpu)
1714{
1715 return global.turbo_disabled || global.no_turbo ?
1716 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1717}
1718
1719static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1720 struct cpudata *cpu)
1721{
1722 int max_freq = intel_pstate_get_max_freq(cpu);
1723 int32_t max_policy_perf, min_policy_perf;
1724 int max_state, turbo_max;
1725
1726
1727
1728
1729
1730
1731 if (hwp_active) {
1732 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1733 } else {
1734 max_state = intel_pstate_get_base_pstate(cpu);
1735 turbo_max = cpu->pstate.turbo_pstate;
1736 }
1737
1738 max_policy_perf = max_state * policy->max / max_freq;
1739 if (policy->max == policy->min) {
1740 min_policy_perf = max_policy_perf;
1741 } else {
1742 min_policy_perf = max_state * policy->min / max_freq;
1743 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1744 0, max_policy_perf);
1745 }
1746
1747 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1748 policy->cpu, max_state,
1749 min_policy_perf, max_policy_perf);
1750
1751
1752 if (per_cpu_limits) {
1753 cpu->min_perf_ratio = min_policy_perf;
1754 cpu->max_perf_ratio = max_policy_perf;
1755 } else {
1756 int32_t global_min, global_max;
1757
1758
1759 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1760 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
1761 global_min = clamp_t(int32_t, global_min, 0, global_max);
1762
1763 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1764 global_min, global_max);
1765
1766 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1767 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
1768 cpu->max_perf_ratio = min(max_policy_perf, global_max);
1769 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
1770
1771
1772 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
1773 cpu->max_perf_ratio);
1774
1775 }
1776 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
1777 cpu->max_perf_ratio,
1778 cpu->min_perf_ratio);
1779}
1780
1781static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1782{
1783 struct cpudata *cpu;
1784
1785 if (!policy->cpuinfo.max_freq)
1786 return -ENODEV;
1787
1788 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1789 policy->cpuinfo.max_freq, policy->max);
1790
1791 cpu = all_cpu_data[policy->cpu];
1792 cpu->policy = policy->policy;
1793
1794 mutex_lock(&intel_pstate_limits_lock);
1795
1796 intel_pstate_update_perf_limits(policy, cpu);
1797
1798 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1799
1800
1801
1802
1803 intel_pstate_clear_update_util_hook(policy->cpu);
1804 intel_pstate_max_within_limits(cpu);
1805 } else {
1806 intel_pstate_set_update_util_hook(policy->cpu);
1807 }
1808
1809 if (hwp_active)
1810 intel_pstate_hwp_set(policy->cpu);
1811
1812 mutex_unlock(&intel_pstate_limits_lock);
1813
1814 return 0;
1815}
1816
1817static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
1818 struct cpudata *cpu)
1819{
1820 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1821 policy->max < policy->cpuinfo.max_freq &&
1822 policy->max > cpu->pstate.max_freq) {
1823 pr_debug("policy->max > max non turbo frequency\n");
1824 policy->max = policy->cpuinfo.max_freq;
1825 }
1826}
1827
1828static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1829{
1830 struct cpudata *cpu = all_cpu_data[policy->cpu];
1831
1832 update_turbo_state();
1833 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1834 intel_pstate_get_max_freq(cpu));
1835
1836 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1837 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1838 return -EINVAL;
1839
1840 intel_pstate_adjust_policy_max(policy, cpu);
1841
1842 return 0;
1843}
1844
1845static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
1846{
1847 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
1848}
1849
1850static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
1851{
1852 pr_debug("CPU %d exiting\n", policy->cpu);
1853
1854 intel_pstate_clear_update_util_hook(policy->cpu);
1855 if (hwp_active)
1856 intel_pstate_hwp_save_state(policy);
1857 else
1858 intel_cpufreq_stop_cpu(policy);
1859}
1860
1861static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
1862{
1863 intel_pstate_exit_perf_limits(policy);
1864
1865 policy->fast_switch_possible = false;
1866
1867 return 0;
1868}
1869
1870static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
1871{
1872 struct cpudata *cpu;
1873 int rc;
1874
1875 rc = intel_pstate_init_cpu(policy->cpu);
1876 if (rc)
1877 return rc;
1878
1879 cpu = all_cpu_data[policy->cpu];
1880
1881 cpu->max_perf_ratio = 0xFF;
1882 cpu->min_perf_ratio = 0;
1883
1884 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1885 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1886
1887
1888 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
1889 update_turbo_state();
1890 policy->cpuinfo.max_freq = global.turbo_disabled ?
1891 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1892 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
1893
1894 intel_pstate_init_acpi_perf_limits(policy);
1895
1896 policy->fast_switch_possible = true;
1897
1898 return 0;
1899}
1900
1901static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
1902{
1903 int ret = __intel_pstate_cpu_init(policy);
1904
1905 if (ret)
1906 return ret;
1907
1908 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
1909 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1910 else
1911 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1912
1913 return 0;
1914}
1915
1916static struct cpufreq_driver intel_pstate = {
1917 .flags = CPUFREQ_CONST_LOOPS,
1918 .verify = intel_pstate_verify_policy,
1919 .setpolicy = intel_pstate_set_policy,
1920 .suspend = intel_pstate_hwp_save_state,
1921 .resume = intel_pstate_resume,
1922 .init = intel_pstate_cpu_init,
1923 .exit = intel_pstate_cpu_exit,
1924 .stop_cpu = intel_pstate_stop_cpu,
1925 .name = "intel_pstate",
1926};
1927
1928static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
1929{
1930 struct cpudata *cpu = all_cpu_data[policy->cpu];
1931
1932 update_turbo_state();
1933 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1934 intel_pstate_get_max_freq(cpu));
1935
1936 intel_pstate_adjust_policy_max(policy, cpu);
1937
1938 intel_pstate_update_perf_limits(policy, cpu);
1939
1940 return 0;
1941}
1942
1943static int intel_cpufreq_target(struct cpufreq_policy *policy,
1944 unsigned int target_freq,
1945 unsigned int relation)
1946{
1947 struct cpudata *cpu = all_cpu_data[policy->cpu];
1948 struct cpufreq_freqs freqs;
1949 int target_pstate;
1950
1951 update_turbo_state();
1952
1953 freqs.old = policy->cur;
1954 freqs.new = target_freq;
1955
1956 cpufreq_freq_transition_begin(policy, &freqs);
1957 switch (relation) {
1958 case CPUFREQ_RELATION_L:
1959 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
1960 break;
1961 case CPUFREQ_RELATION_H:
1962 target_pstate = freqs.new / cpu->pstate.scaling;
1963 break;
1964 default:
1965 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
1966 break;
1967 }
1968 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1969 if (target_pstate != cpu->pstate.current_pstate) {
1970 cpu->pstate.current_pstate = target_pstate;
1971 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
1972 pstate_funcs.get_val(cpu, target_pstate));
1973 }
1974 freqs.new = target_pstate * cpu->pstate.scaling;
1975 cpufreq_freq_transition_end(policy, &freqs, false);
1976
1977 return 0;
1978}
1979
1980static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
1981 unsigned int target_freq)
1982{
1983 struct cpudata *cpu = all_cpu_data[policy->cpu];
1984 int target_pstate;
1985
1986 update_turbo_state();
1987
1988 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
1989 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1990 intel_pstate_update_pstate(cpu, target_pstate);
1991 return target_pstate * cpu->pstate.scaling;
1992}
1993
1994static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
1995{
1996 int ret = __intel_pstate_cpu_init(policy);
1997
1998 if (ret)
1999 return ret;
2000
2001 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2002 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2003
2004 policy->cur = policy->cpuinfo.min_freq;
2005
2006 return 0;
2007}
2008
2009static struct cpufreq_driver intel_cpufreq = {
2010 .flags = CPUFREQ_CONST_LOOPS,
2011 .verify = intel_cpufreq_verify_policy,
2012 .target = intel_cpufreq_target,
2013 .fast_switch = intel_cpufreq_fast_switch,
2014 .init = intel_cpufreq_cpu_init,
2015 .exit = intel_pstate_cpu_exit,
2016 .stop_cpu = intel_cpufreq_stop_cpu,
2017 .name = "intel_cpufreq",
2018};
2019
2020static struct cpufreq_driver *default_driver = &intel_pstate;
2021
2022static void intel_pstate_driver_cleanup(void)
2023{
2024 unsigned int cpu;
2025
2026 get_online_cpus();
2027 for_each_online_cpu(cpu) {
2028 if (all_cpu_data[cpu]) {
2029 if (intel_pstate_driver == &intel_pstate)
2030 intel_pstate_clear_update_util_hook(cpu);
2031
2032 kfree(all_cpu_data[cpu]);
2033 all_cpu_data[cpu] = NULL;
2034 }
2035 }
2036 put_online_cpus();
2037 intel_pstate_driver = NULL;
2038}
2039
2040static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2041{
2042 int ret;
2043
2044 memset(&global, 0, sizeof(global));
2045 global.max_perf_pct = 100;
2046
2047 intel_pstate_driver = driver;
2048 ret = cpufreq_register_driver(intel_pstate_driver);
2049 if (ret) {
2050 intel_pstate_driver_cleanup();
2051 return ret;
2052 }
2053
2054 global.min_perf_pct = min_perf_pct_min();
2055
2056 return 0;
2057}
2058
2059static int intel_pstate_unregister_driver(void)
2060{
2061 if (hwp_active)
2062 return -EBUSY;
2063
2064 cpufreq_unregister_driver(intel_pstate_driver);
2065 intel_pstate_driver_cleanup();
2066
2067 return 0;
2068}
2069
2070static ssize_t intel_pstate_show_status(char *buf)
2071{
2072 if (!intel_pstate_driver)
2073 return sprintf(buf, "off\n");
2074
2075 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2076 "active" : "passive");
2077}
2078
2079static int intel_pstate_update_status(const char *buf, size_t size)
2080{
2081 int ret;
2082
2083 if (size == 3 && !strncmp(buf, "off", size))
2084 return intel_pstate_driver ?
2085 intel_pstate_unregister_driver() : -EINVAL;
2086
2087 if (size == 6 && !strncmp(buf, "active", size)) {
2088 if (intel_pstate_driver) {
2089 if (intel_pstate_driver == &intel_pstate)
2090 return 0;
2091
2092 ret = intel_pstate_unregister_driver();
2093 if (ret)
2094 return ret;
2095 }
2096
2097 return intel_pstate_register_driver(&intel_pstate);
2098 }
2099
2100 if (size == 7 && !strncmp(buf, "passive", size)) {
2101 if (intel_pstate_driver) {
2102 if (intel_pstate_driver == &intel_cpufreq)
2103 return 0;
2104
2105 ret = intel_pstate_unregister_driver();
2106 if (ret)
2107 return ret;
2108 }
2109
2110 return intel_pstate_register_driver(&intel_cpufreq);
2111 }
2112
2113 return -EINVAL;
2114}
2115
2116static int no_load __initdata;
2117static int no_hwp __initdata;
2118static int hwp_only __initdata;
2119static unsigned int force_load __initdata;
2120
2121static int __init intel_pstate_msrs_not_valid(void)
2122{
2123 if (!pstate_funcs.get_max() ||
2124 !pstate_funcs.get_min() ||
2125 !pstate_funcs.get_turbo())
2126 return -ENODEV;
2127
2128 return 0;
2129}
2130
2131static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2132{
2133 pstate_funcs.get_max = funcs->get_max;
2134 pstate_funcs.get_max_physical = funcs->get_max_physical;
2135 pstate_funcs.get_min = funcs->get_min;
2136 pstate_funcs.get_turbo = funcs->get_turbo;
2137 pstate_funcs.get_scaling = funcs->get_scaling;
2138 pstate_funcs.get_val = funcs->get_val;
2139 pstate_funcs.get_vid = funcs->get_vid;
2140 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2141}
2142
2143#ifdef CONFIG_ACPI
2144
2145static bool __init intel_pstate_no_acpi_pss(void)
2146{
2147 int i;
2148
2149 for_each_possible_cpu(i) {
2150 acpi_status status;
2151 union acpi_object *pss;
2152 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2153 struct acpi_processor *pr = per_cpu(processors, i);
2154
2155 if (!pr)
2156 continue;
2157
2158 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2159 if (ACPI_FAILURE(status))
2160 continue;
2161
2162 pss = buffer.pointer;
2163 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2164 kfree(pss);
2165 return false;
2166 }
2167
2168 kfree(pss);
2169 }
2170
2171 return true;
2172}
2173
2174static bool __init intel_pstate_has_acpi_ppc(void)
2175{
2176 int i;
2177
2178 for_each_possible_cpu(i) {
2179 struct acpi_processor *pr = per_cpu(processors, i);
2180
2181 if (!pr)
2182 continue;
2183 if (acpi_has_method(pr->handle, "_PPC"))
2184 return true;
2185 }
2186 return false;
2187}
2188
2189enum {
2190 PSS,
2191 PPC,
2192};
2193
2194
2195static struct acpi_platform_list plat_info[] __initdata = {
2196 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2197 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2198 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2199 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2200 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2201 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2202 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2203 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2204 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2205 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2206 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2207 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2208 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2209 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2210 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2211 { }
2212};
2213
2214static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2215{
2216 const struct x86_cpu_id *id;
2217 u64 misc_pwr;
2218 int idx;
2219
2220 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2221 if (id) {
2222 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2223 if ( misc_pwr & (1 << 8))
2224 return true;
2225 }
2226
2227 idx = acpi_match_platform_list(plat_info);
2228 if (idx < 0)
2229 return false;
2230
2231 switch (plat_info[idx].data) {
2232 case PSS:
2233 return intel_pstate_no_acpi_pss();
2234 case PPC:
2235 return intel_pstate_has_acpi_ppc() && !force_load;
2236 }
2237
2238 return false;
2239}
2240
2241static void intel_pstate_request_control_from_smm(void)
2242{
2243
2244
2245
2246
2247 if (acpi_ppc)
2248 acpi_processor_pstate_control();
2249}
2250#else
2251static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2252static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2253static inline void intel_pstate_request_control_from_smm(void) {}
2254#endif
2255
2256static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2257 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2258 {}
2259};
2260
2261static int __init intel_pstate_init(void)
2262{
2263 int rc;
2264
2265 if (no_load)
2266 return -ENODEV;
2267
2268 if (x86_match_cpu(hwp_support_ids)) {
2269 copy_cpu_funcs(&core_funcs);
2270 if (!no_hwp) {
2271 hwp_active++;
2272 intel_pstate.attr = hwp_cpufreq_attrs;
2273 goto hwp_cpu_matched;
2274 }
2275 } else {
2276 const struct x86_cpu_id *id;
2277
2278 id = x86_match_cpu(intel_pstate_cpu_ids);
2279 if (!id)
2280 return -ENODEV;
2281
2282 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2283 }
2284
2285 if (intel_pstate_msrs_not_valid())
2286 return -ENODEV;
2287
2288hwp_cpu_matched:
2289
2290
2291
2292
2293 if (intel_pstate_platform_pwr_mgmt_exists())
2294 return -ENODEV;
2295
2296 if (!hwp_active && hwp_only)
2297 return -ENOTSUPP;
2298
2299 pr_info("Intel P-state driver initializing\n");
2300
2301 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2302 if (!all_cpu_data)
2303 return -ENOMEM;
2304
2305 intel_pstate_request_control_from_smm();
2306
2307 intel_pstate_sysfs_expose_params();
2308
2309 mutex_lock(&intel_pstate_driver_lock);
2310 rc = intel_pstate_register_driver(default_driver);
2311 mutex_unlock(&intel_pstate_driver_lock);
2312 if (rc)
2313 return rc;
2314
2315 if (hwp_active)
2316 pr_info("HWP enabled\n");
2317
2318 return 0;
2319}
2320device_initcall(intel_pstate_init);
2321
2322static int __init intel_pstate_setup(char *str)
2323{
2324 if (!str)
2325 return -EINVAL;
2326
2327 if (!strcmp(str, "disable")) {
2328 no_load = 1;
2329 } else if (!strcmp(str, "passive")) {
2330 pr_info("Passive mode enabled\n");
2331 default_driver = &intel_cpufreq;
2332 no_hwp = 1;
2333 }
2334 if (!strcmp(str, "no_hwp")) {
2335 pr_info("HWP disabled\n");
2336 no_hwp = 1;
2337 }
2338 if (!strcmp(str, "force"))
2339 force_load = 1;
2340 if (!strcmp(str, "hwp_only"))
2341 hwp_only = 1;
2342 if (!strcmp(str, "per_cpu_perf_limits"))
2343 per_cpu_limits = true;
2344
2345#ifdef CONFIG_ACPI
2346 if (!strcmp(str, "support_acpi_ppc"))
2347 acpi_ppc = true;
2348#endif
2349
2350 return 0;
2351}
2352early_param("intel_pstate", intel_pstate_setup);
2353
2354MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2355MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2356MODULE_LICENSE("GPL");
2357