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14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
19#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/amba/bus.h>
25#include <linux/scatterlist.h>
26#include <linux/of.h>
27#include <linux/of_dma.h>
28#include <linux/err.h>
29#include <linux/pm_runtime.h>
30
31#include "dmaengine.h"
32#define PL330_MAX_CHAN 8
33#define PL330_MAX_IRQS 32
34#define PL330_MAX_PERI 32
35#define PL330_MAX_BURST 16
36
37#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
38
39enum pl330_cachectrl {
40 CCTRL0,
41 CCTRL1,
42 CCTRL2,
43 CCTRL3,
44 INVALID1,
45 INVALID2,
46 CCTRL6,
47 CCTRL7,
48};
49
50enum pl330_byteswap {
51 SWAP_NO,
52 SWAP_2,
53 SWAP_4,
54 SWAP_8,
55 SWAP_16,
56};
57
58
59#define DS 0x0
60#define DS_ST_STOP 0x0
61#define DS_ST_EXEC 0x1
62#define DS_ST_CMISS 0x2
63#define DS_ST_UPDTPC 0x3
64#define DS_ST_WFE 0x4
65#define DS_ST_ATBRR 0x5
66#define DS_ST_QBUSY 0x6
67#define DS_ST_WFP 0x7
68#define DS_ST_KILL 0x8
69#define DS_ST_CMPLT 0x9
70#define DS_ST_FLTCMP 0xe
71#define DS_ST_FAULT 0xf
72
73#define DPC 0x4
74#define INTEN 0x20
75#define ES 0x24
76#define INTSTATUS 0x28
77#define INTCLR 0x2c
78#define FSM 0x30
79#define FSC 0x34
80#define FTM 0x38
81
82#define _FTC 0x40
83#define FTC(n) (_FTC + (n)*0x4)
84
85#define _CS 0x100
86#define CS(n) (_CS + (n)*0x8)
87#define CS_CNS (1 << 21)
88
89#define _CPC 0x104
90#define CPC(n) (_CPC + (n)*0x8)
91
92#define _SA 0x400
93#define SA(n) (_SA + (n)*0x20)
94
95#define _DA 0x404
96#define DA(n) (_DA + (n)*0x20)
97
98#define _CC 0x408
99#define CC(n) (_CC + (n)*0x20)
100
101#define CC_SRCINC (1 << 0)
102#define CC_DSTINC (1 << 14)
103#define CC_SRCPRI (1 << 8)
104#define CC_DSTPRI (1 << 22)
105#define CC_SRCNS (1 << 9)
106#define CC_DSTNS (1 << 23)
107#define CC_SRCIA (1 << 10)
108#define CC_DSTIA (1 << 24)
109#define CC_SRCBRSTLEN_SHFT 4
110#define CC_DSTBRSTLEN_SHFT 18
111#define CC_SRCBRSTSIZE_SHFT 1
112#define CC_DSTBRSTSIZE_SHFT 15
113#define CC_SRCCCTRL_SHFT 11
114#define CC_SRCCCTRL_MASK 0x7
115#define CC_DSTCCTRL_SHFT 25
116#define CC_DRCCCTRL_MASK 0x7
117#define CC_SWAP_SHFT 28
118
119#define _LC0 0x40c
120#define LC0(n) (_LC0 + (n)*0x20)
121
122#define _LC1 0x410
123#define LC1(n) (_LC1 + (n)*0x20)
124
125#define DBGSTATUS 0xd00
126#define DBG_BUSY (1 << 0)
127
128#define DBGCMD 0xd04
129#define DBGINST0 0xd08
130#define DBGINST1 0xd0c
131
132#define CR0 0xe00
133#define CR1 0xe04
134#define CR2 0xe08
135#define CR3 0xe0c
136#define CR4 0xe10
137#define CRD 0xe14
138
139#define PERIPH_ID 0xfe0
140#define PERIPH_REV_SHIFT 20
141#define PERIPH_REV_MASK 0xf
142#define PERIPH_REV_R0P0 0
143#define PERIPH_REV_R1P0 1
144#define PERIPH_REV_R1P1 2
145
146#define CR0_PERIPH_REQ_SET (1 << 0)
147#define CR0_BOOT_EN_SET (1 << 1)
148#define CR0_BOOT_MAN_NS (1 << 2)
149#define CR0_NUM_CHANS_SHIFT 4
150#define CR0_NUM_CHANS_MASK 0x7
151#define CR0_NUM_PERIPH_SHIFT 12
152#define CR0_NUM_PERIPH_MASK 0x1f
153#define CR0_NUM_EVENTS_SHIFT 17
154#define CR0_NUM_EVENTS_MASK 0x1f
155
156#define CR1_ICACHE_LEN_SHIFT 0
157#define CR1_ICACHE_LEN_MASK 0x7
158#define CR1_NUM_ICACHELINES_SHIFT 4
159#define CR1_NUM_ICACHELINES_MASK 0xf
160
161#define CRD_DATA_WIDTH_SHIFT 0
162#define CRD_DATA_WIDTH_MASK 0x7
163#define CRD_WR_CAP_SHIFT 4
164#define CRD_WR_CAP_MASK 0x7
165#define CRD_WR_Q_DEP_SHIFT 8
166#define CRD_WR_Q_DEP_MASK 0xf
167#define CRD_RD_CAP_SHIFT 12
168#define CRD_RD_CAP_MASK 0x7
169#define CRD_RD_Q_DEP_SHIFT 16
170#define CRD_RD_Q_DEP_MASK 0xf
171#define CRD_DATA_BUFF_SHIFT 20
172#define CRD_DATA_BUFF_MASK 0x3ff
173
174#define PART 0x330
175#define DESIGNER 0x41
176#define REVISION 0x0
177#define INTEG_CFG 0x0
178#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
179
180#define PL330_STATE_STOPPED (1 << 0)
181#define PL330_STATE_EXECUTING (1 << 1)
182#define PL330_STATE_WFE (1 << 2)
183#define PL330_STATE_FAULTING (1 << 3)
184#define PL330_STATE_COMPLETING (1 << 4)
185#define PL330_STATE_WFP (1 << 5)
186#define PL330_STATE_KILLING (1 << 6)
187#define PL330_STATE_FAULT_COMPLETING (1 << 7)
188#define PL330_STATE_CACHEMISS (1 << 8)
189#define PL330_STATE_UPDTPC (1 << 9)
190#define PL330_STATE_ATBARRIER (1 << 10)
191#define PL330_STATE_QUEUEBUSY (1 << 11)
192#define PL330_STATE_INVALID (1 << 15)
193
194#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
195 | PL330_STATE_WFE | PL330_STATE_FAULTING)
196
197#define CMD_DMAADDH 0x54
198#define CMD_DMAEND 0x00
199#define CMD_DMAFLUSHP 0x35
200#define CMD_DMAGO 0xa0
201#define CMD_DMALD 0x04
202#define CMD_DMALDP 0x25
203#define CMD_DMALP 0x20
204#define CMD_DMALPEND 0x28
205#define CMD_DMAKILL 0x01
206#define CMD_DMAMOV 0xbc
207#define CMD_DMANOP 0x18
208#define CMD_DMARMB 0x12
209#define CMD_DMASEV 0x34
210#define CMD_DMAST 0x08
211#define CMD_DMASTP 0x29
212#define CMD_DMASTZ 0x0c
213#define CMD_DMAWFE 0x36
214#define CMD_DMAWFP 0x30
215#define CMD_DMAWMB 0x13
216
217#define SZ_DMAADDH 3
218#define SZ_DMAEND 1
219#define SZ_DMAFLUSHP 2
220#define SZ_DMALD 1
221#define SZ_DMALDP 2
222#define SZ_DMALP 2
223#define SZ_DMALPEND 2
224#define SZ_DMAKILL 1
225#define SZ_DMAMOV 6
226#define SZ_DMANOP 1
227#define SZ_DMARMB 1
228#define SZ_DMASEV 2
229#define SZ_DMAST 1
230#define SZ_DMASTP 2
231#define SZ_DMASTZ 1
232#define SZ_DMAWFE 2
233#define SZ_DMAWFP 2
234#define SZ_DMAWMB 1
235#define SZ_DMAGO 6
236
237#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
238#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
239
240#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
241#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
242
243
244
245
246
247
248
249#define MCODE_BUFF_PER_REQ 256
250
251
252#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
253
254#ifdef PL330_DEBUG_MCGEN
255static unsigned cmd_line;
256#define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
258 printk(x); \
259 cmd_line += off; \
260 } while (0)
261#define PL330_DBGMC_START(addr) (cmd_line = addr)
262#else
263#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264#define PL330_DBGMC_START(addr) do {} while (0)
265#endif
266
267
268
269#define NR_DEFAULT_DESC 16
270
271
272#define PL330_AUTOSUSPEND_DELAY 20
273
274
275struct pl330_config {
276 u32 periph_id;
277#define DMAC_MODE_NS (1 << 0)
278 unsigned int mode;
279 unsigned int data_bus_width:10;
280 unsigned int data_buf_dep:11;
281 unsigned int num_chan:4;
282 unsigned int num_peri:6;
283 u32 peri_ns;
284 unsigned int num_events:6;
285 u32 irq_ns;
286};
287
288
289
290
291
292
293
294
295
296struct pl330_reqcfg {
297
298 unsigned dst_inc:1;
299 unsigned src_inc:1;
300
301
302
303
304
305 bool nonsecure;
306 bool privileged;
307 bool insnaccess;
308 unsigned brst_len:5;
309 unsigned brst_size:3;
310
311 enum pl330_cachectrl dcctl;
312 enum pl330_cachectrl scctl;
313 enum pl330_byteswap swap;
314 struct pl330_config *pcfg;
315};
316
317
318
319
320
321struct pl330_xfer {
322 u32 src_addr;
323 u32 dst_addr;
324
325 u32 bytes;
326};
327
328
329enum pl330_op_err {
330
331 PL330_ERR_NONE,
332
333 PL330_ERR_ABORT,
334
335 PL330_ERR_FAIL,
336};
337
338enum dmamov_dst {
339 SAR = 0,
340 CCR,
341 DAR,
342};
343
344enum pl330_dst {
345 SRC = 0,
346 DST,
347};
348
349enum pl330_cond {
350 SINGLE,
351 BURST,
352 ALWAYS,
353};
354
355struct dma_pl330_desc;
356
357struct _pl330_req {
358 u32 mc_bus;
359 void *mc_cpu;
360 struct dma_pl330_desc *desc;
361};
362
363
364struct _pl330_tbd {
365 bool reset_dmac;
366 bool reset_mngr;
367 u8 reset_chan;
368};
369
370
371struct pl330_thread {
372 u8 id;
373 int ev;
374
375 bool free;
376
377 struct pl330_dmac *dmac;
378
379 struct _pl330_req req[2];
380
381 unsigned lstenq;
382
383 int req_running;
384};
385
386enum pl330_dmac_state {
387 UNINIT,
388 INIT,
389 DYING,
390};
391
392enum desc_status {
393
394 FREE,
395
396
397
398
399 PREP,
400
401
402
403
404
405 BUSY,
406
407
408
409
410 DONE,
411};
412
413struct dma_pl330_chan {
414
415 struct tasklet_struct task;
416
417
418 struct dma_chan chan;
419
420
421 struct list_head submitted_list;
422
423 struct list_head work_list;
424
425 struct list_head completed_list;
426
427
428
429
430
431
432 struct pl330_dmac *dmac;
433
434
435 spinlock_t lock;
436
437
438
439
440
441 struct pl330_thread *thread;
442
443
444 int burst_sz;
445 int burst_len;
446 phys_addr_t fifo_addr;
447
448 dma_addr_t fifo_dma;
449 enum dma_data_direction dir;
450
451
452 bool cyclic;
453
454
455 bool active;
456};
457
458struct pl330_dmac {
459
460 struct dma_device ddma;
461
462
463 struct device_dma_parameters dma_parms;
464
465
466 struct list_head desc_pool;
467
468 spinlock_t pool_lock;
469
470
471 unsigned mcbufsz;
472
473 void __iomem *base;
474
475 struct pl330_config pcfg;
476
477 spinlock_t lock;
478
479 int events[32];
480
481 dma_addr_t mcode_bus;
482
483 void *mcode_cpu;
484
485 struct pl330_thread *channels;
486
487 struct pl330_thread *manager;
488
489 struct tasklet_struct tasks;
490 struct _pl330_tbd dmac_tbd;
491
492 enum pl330_dmac_state state;
493
494 struct list_head req_done;
495
496
497 unsigned int num_peripherals;
498 struct dma_pl330_chan *peripherals;
499 int quirks;
500};
501
502static struct pl330_of_quirks {
503 char *quirk;
504 int id;
505} of_quirks[] = {
506 {
507 .quirk = "arm,pl330-broken-no-flushp",
508 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
509 }
510};
511
512struct dma_pl330_desc {
513
514 struct list_head node;
515
516
517 struct dma_async_tx_descriptor txd;
518
519
520 struct pl330_xfer px;
521
522 struct pl330_reqcfg rqcfg;
523
524 enum desc_status status;
525
526 int bytes_requested;
527 bool last;
528
529
530 struct dma_pl330_chan *pchan;
531
532 enum dma_transfer_direction rqtype;
533
534 unsigned peri:5;
535
536 struct list_head rqd;
537};
538
539struct _xfer_spec {
540 u32 ccr;
541 struct dma_pl330_desc *desc;
542};
543
544static inline bool _queue_full(struct pl330_thread *thrd)
545{
546 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
547}
548
549static inline bool is_manager(struct pl330_thread *thrd)
550{
551 return thrd->dmac->manager == thrd;
552}
553
554
555static inline bool _manager_ns(struct pl330_thread *thrd)
556{
557 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
558}
559
560static inline u32 get_revision(u32 periph_id)
561{
562 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
563}
564
565static inline u32 _emit_END(unsigned dry_run, u8 buf[])
566{
567 if (dry_run)
568 return SZ_DMAEND;
569
570 buf[0] = CMD_DMAEND;
571
572 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
573
574 return SZ_DMAEND;
575}
576
577static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
578{
579 if (dry_run)
580 return SZ_DMAFLUSHP;
581
582 buf[0] = CMD_DMAFLUSHP;
583
584 peri &= 0x1f;
585 peri <<= 3;
586 buf[1] = peri;
587
588 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
589
590 return SZ_DMAFLUSHP;
591}
592
593static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
594{
595 if (dry_run)
596 return SZ_DMALD;
597
598 buf[0] = CMD_DMALD;
599
600 if (cond == SINGLE)
601 buf[0] |= (0 << 1) | (1 << 0);
602 else if (cond == BURST)
603 buf[0] |= (1 << 1) | (1 << 0);
604
605 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
606 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
607
608 return SZ_DMALD;
609}
610
611static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
612 enum pl330_cond cond, u8 peri)
613{
614 if (dry_run)
615 return SZ_DMALDP;
616
617 buf[0] = CMD_DMALDP;
618
619 if (cond == BURST)
620 buf[0] |= (1 << 1);
621
622 peri &= 0x1f;
623 peri <<= 3;
624 buf[1] = peri;
625
626 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
627 cond == SINGLE ? 'S' : 'B', peri >> 3);
628
629 return SZ_DMALDP;
630}
631
632static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
633 unsigned loop, u8 cnt)
634{
635 if (dry_run)
636 return SZ_DMALP;
637
638 buf[0] = CMD_DMALP;
639
640 if (loop)
641 buf[0] |= (1 << 1);
642
643 cnt--;
644 buf[1] = cnt;
645
646 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
647
648 return SZ_DMALP;
649}
650
651struct _arg_LPEND {
652 enum pl330_cond cond;
653 bool forever;
654 unsigned loop;
655 u8 bjump;
656};
657
658static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
659 const struct _arg_LPEND *arg)
660{
661 enum pl330_cond cond = arg->cond;
662 bool forever = arg->forever;
663 unsigned loop = arg->loop;
664 u8 bjump = arg->bjump;
665
666 if (dry_run)
667 return SZ_DMALPEND;
668
669 buf[0] = CMD_DMALPEND;
670
671 if (loop)
672 buf[0] |= (1 << 2);
673
674 if (!forever)
675 buf[0] |= (1 << 4);
676
677 if (cond == SINGLE)
678 buf[0] |= (0 << 1) | (1 << 0);
679 else if (cond == BURST)
680 buf[0] |= (1 << 1) | (1 << 0);
681
682 buf[1] = bjump;
683
684 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
685 forever ? "FE" : "END",
686 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
687 loop ? '1' : '0',
688 bjump);
689
690 return SZ_DMALPEND;
691}
692
693static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
694{
695 if (dry_run)
696 return SZ_DMAKILL;
697
698 buf[0] = CMD_DMAKILL;
699
700 return SZ_DMAKILL;
701}
702
703static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
704 enum dmamov_dst dst, u32 val)
705{
706 if (dry_run)
707 return SZ_DMAMOV;
708
709 buf[0] = CMD_DMAMOV;
710 buf[1] = dst;
711 buf[2] = val;
712 buf[3] = val >> 8;
713 buf[4] = val >> 16;
714 buf[5] = val >> 24;
715
716 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
717 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
718
719 return SZ_DMAMOV;
720}
721
722static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
723{
724 if (dry_run)
725 return SZ_DMARMB;
726
727 buf[0] = CMD_DMARMB;
728
729 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
730
731 return SZ_DMARMB;
732}
733
734static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
735{
736 if (dry_run)
737 return SZ_DMASEV;
738
739 buf[0] = CMD_DMASEV;
740
741 ev &= 0x1f;
742 ev <<= 3;
743 buf[1] = ev;
744
745 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
746
747 return SZ_DMASEV;
748}
749
750static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
751{
752 if (dry_run)
753 return SZ_DMAST;
754
755 buf[0] = CMD_DMAST;
756
757 if (cond == SINGLE)
758 buf[0] |= (0 << 1) | (1 << 0);
759 else if (cond == BURST)
760 buf[0] |= (1 << 1) | (1 << 0);
761
762 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
763 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
764
765 return SZ_DMAST;
766}
767
768static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
769 enum pl330_cond cond, u8 peri)
770{
771 if (dry_run)
772 return SZ_DMASTP;
773
774 buf[0] = CMD_DMASTP;
775
776 if (cond == BURST)
777 buf[0] |= (1 << 1);
778
779 peri &= 0x1f;
780 peri <<= 3;
781 buf[1] = peri;
782
783 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
784 cond == SINGLE ? 'S' : 'B', peri >> 3);
785
786 return SZ_DMASTP;
787}
788
789static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
790 enum pl330_cond cond, u8 peri)
791{
792 if (dry_run)
793 return SZ_DMAWFP;
794
795 buf[0] = CMD_DMAWFP;
796
797 if (cond == SINGLE)
798 buf[0] |= (0 << 1) | (0 << 0);
799 else if (cond == BURST)
800 buf[0] |= (1 << 1) | (0 << 0);
801 else
802 buf[0] |= (0 << 1) | (1 << 0);
803
804 peri &= 0x1f;
805 peri <<= 3;
806 buf[1] = peri;
807
808 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
809 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
810
811 return SZ_DMAWFP;
812}
813
814static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
815{
816 if (dry_run)
817 return SZ_DMAWMB;
818
819 buf[0] = CMD_DMAWMB;
820
821 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
822
823 return SZ_DMAWMB;
824}
825
826struct _arg_GO {
827 u8 chan;
828 u32 addr;
829 unsigned ns;
830};
831
832static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
833 const struct _arg_GO *arg)
834{
835 u8 chan = arg->chan;
836 u32 addr = arg->addr;
837 unsigned ns = arg->ns;
838
839 if (dry_run)
840 return SZ_DMAGO;
841
842 buf[0] = CMD_DMAGO;
843 buf[0] |= (ns << 1);
844 buf[1] = chan & 0x7;
845 buf[2] = addr;
846 buf[3] = addr >> 8;
847 buf[4] = addr >> 16;
848 buf[5] = addr >> 24;
849
850 return SZ_DMAGO;
851}
852
853#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
854
855
856static bool _until_dmac_idle(struct pl330_thread *thrd)
857{
858 void __iomem *regs = thrd->dmac->base;
859 unsigned long loops = msecs_to_loops(5);
860
861 do {
862
863 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
864 break;
865
866 cpu_relax();
867 } while (--loops);
868
869 if (!loops)
870 return true;
871
872 return false;
873}
874
875static inline void _execute_DBGINSN(struct pl330_thread *thrd,
876 u8 insn[], bool as_manager)
877{
878 void __iomem *regs = thrd->dmac->base;
879 u32 val;
880
881 val = (insn[0] << 16) | (insn[1] << 24);
882 if (!as_manager) {
883 val |= (1 << 0);
884 val |= (thrd->id << 8);
885 }
886 writel(val, regs + DBGINST0);
887
888 val = le32_to_cpu(*((__le32 *)&insn[2]));
889 writel(val, regs + DBGINST1);
890
891
892 if (_until_dmac_idle(thrd)) {
893 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
894 return;
895 }
896
897
898 writel(0, regs + DBGCMD);
899}
900
901static inline u32 _state(struct pl330_thread *thrd)
902{
903 void __iomem *regs = thrd->dmac->base;
904 u32 val;
905
906 if (is_manager(thrd))
907 val = readl(regs + DS) & 0xf;
908 else
909 val = readl(regs + CS(thrd->id)) & 0xf;
910
911 switch (val) {
912 case DS_ST_STOP:
913 return PL330_STATE_STOPPED;
914 case DS_ST_EXEC:
915 return PL330_STATE_EXECUTING;
916 case DS_ST_CMISS:
917 return PL330_STATE_CACHEMISS;
918 case DS_ST_UPDTPC:
919 return PL330_STATE_UPDTPC;
920 case DS_ST_WFE:
921 return PL330_STATE_WFE;
922 case DS_ST_FAULT:
923 return PL330_STATE_FAULTING;
924 case DS_ST_ATBRR:
925 if (is_manager(thrd))
926 return PL330_STATE_INVALID;
927 else
928 return PL330_STATE_ATBARRIER;
929 case DS_ST_QBUSY:
930 if (is_manager(thrd))
931 return PL330_STATE_INVALID;
932 else
933 return PL330_STATE_QUEUEBUSY;
934 case DS_ST_WFP:
935 if (is_manager(thrd))
936 return PL330_STATE_INVALID;
937 else
938 return PL330_STATE_WFP;
939 case DS_ST_KILL:
940 if (is_manager(thrd))
941 return PL330_STATE_INVALID;
942 else
943 return PL330_STATE_KILLING;
944 case DS_ST_CMPLT:
945 if (is_manager(thrd))
946 return PL330_STATE_INVALID;
947 else
948 return PL330_STATE_COMPLETING;
949 case DS_ST_FLTCMP:
950 if (is_manager(thrd))
951 return PL330_STATE_INVALID;
952 else
953 return PL330_STATE_FAULT_COMPLETING;
954 default:
955 return PL330_STATE_INVALID;
956 }
957}
958
959static void _stop(struct pl330_thread *thrd)
960{
961 void __iomem *regs = thrd->dmac->base;
962 u8 insn[6] = {0, 0, 0, 0, 0, 0};
963
964 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
965 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
966
967
968 if (_state(thrd) == PL330_STATE_COMPLETING
969 || _state(thrd) == PL330_STATE_KILLING
970 || _state(thrd) == PL330_STATE_STOPPED)
971 return;
972
973 _emit_KILL(0, insn);
974
975
976 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
977
978 _execute_DBGINSN(thrd, insn, is_manager(thrd));
979}
980
981
982static bool _trigger(struct pl330_thread *thrd)
983{
984 void __iomem *regs = thrd->dmac->base;
985 struct _pl330_req *req;
986 struct dma_pl330_desc *desc;
987 struct _arg_GO go;
988 unsigned ns;
989 u8 insn[6] = {0, 0, 0, 0, 0, 0};
990 int idx;
991
992
993 if (_state(thrd) != PL330_STATE_STOPPED)
994 return true;
995
996 idx = 1 - thrd->lstenq;
997 if (thrd->req[idx].desc != NULL) {
998 req = &thrd->req[idx];
999 } else {
1000 idx = thrd->lstenq;
1001 if (thrd->req[idx].desc != NULL)
1002 req = &thrd->req[idx];
1003 else
1004 req = NULL;
1005 }
1006
1007
1008 if (!req)
1009 return true;
1010
1011
1012 if (idx == thrd->req_running)
1013 return true;
1014
1015 desc = req->desc;
1016
1017 ns = desc->rqcfg.nonsecure ? 1 : 0;
1018
1019
1020 if (_manager_ns(thrd) && !ns)
1021 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1022 __func__, __LINE__);
1023
1024 go.chan = thrd->id;
1025 go.addr = req->mc_bus;
1026 go.ns = ns;
1027 _emit_GO(0, insn, &go);
1028
1029
1030 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1031
1032
1033 _execute_DBGINSN(thrd, insn, true);
1034
1035 thrd->req_running = idx;
1036
1037 return true;
1038}
1039
1040static bool _start(struct pl330_thread *thrd)
1041{
1042 switch (_state(thrd)) {
1043 case PL330_STATE_FAULT_COMPLETING:
1044 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1045
1046 if (_state(thrd) == PL330_STATE_KILLING)
1047 UNTIL(thrd, PL330_STATE_STOPPED)
1048
1049 case PL330_STATE_FAULTING:
1050 _stop(thrd);
1051
1052 case PL330_STATE_KILLING:
1053 case PL330_STATE_COMPLETING:
1054 UNTIL(thrd, PL330_STATE_STOPPED)
1055
1056 case PL330_STATE_STOPPED:
1057 return _trigger(thrd);
1058
1059 case PL330_STATE_WFP:
1060 case PL330_STATE_QUEUEBUSY:
1061 case PL330_STATE_ATBARRIER:
1062 case PL330_STATE_UPDTPC:
1063 case PL330_STATE_CACHEMISS:
1064 case PL330_STATE_EXECUTING:
1065 return true;
1066
1067 case PL330_STATE_WFE:
1068 default:
1069 return false;
1070 }
1071}
1072
1073static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1074 const struct _xfer_spec *pxs, int cyc)
1075{
1076 int off = 0;
1077 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1078
1079
1080 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1081 while (cyc--) {
1082 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1083 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1084 }
1085 } else {
1086 while (cyc--) {
1087 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1088 off += _emit_RMB(dry_run, &buf[off]);
1089 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1090 off += _emit_WMB(dry_run, &buf[off]);
1091 }
1092 }
1093
1094 return off;
1095}
1096
1097static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run,
1098 u8 buf[], const struct _xfer_spec *pxs,
1099 int cyc)
1100{
1101 int off = 0;
1102 enum pl330_cond cond;
1103
1104 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1105 cond = BURST;
1106 else
1107 cond = SINGLE;
1108
1109 while (cyc--) {
1110 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1111 off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri);
1112 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1113
1114 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1115 off += _emit_FLUSHP(dry_run, &buf[off],
1116 pxs->desc->peri);
1117 }
1118
1119 return off;
1120}
1121
1122static inline int _ldst_memtodev(struct pl330_dmac *pl330,
1123 unsigned dry_run, u8 buf[],
1124 const struct _xfer_spec *pxs, int cyc)
1125{
1126 int off = 0;
1127 enum pl330_cond cond;
1128
1129 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1130 cond = BURST;
1131 else
1132 cond = SINGLE;
1133
1134 while (cyc--) {
1135 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1136 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1137 off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri);
1138
1139 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1140 off += _emit_FLUSHP(dry_run, &buf[off],
1141 pxs->desc->peri);
1142 }
1143
1144 return off;
1145}
1146
1147static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1148 const struct _xfer_spec *pxs, int cyc)
1149{
1150 int off = 0;
1151
1152 switch (pxs->desc->rqtype) {
1153 case DMA_MEM_TO_DEV:
1154 off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc);
1155 break;
1156 case DMA_DEV_TO_MEM:
1157 off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc);
1158 break;
1159 case DMA_MEM_TO_MEM:
1160 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1161 break;
1162 default:
1163 off += 0x40000000;
1164 break;
1165 }
1166
1167 return off;
1168}
1169
1170
1171static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1172 unsigned long *bursts, const struct _xfer_spec *pxs)
1173{
1174 int cyc, cycmax, szlp, szlpend, szbrst, off;
1175 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1176 struct _arg_LPEND lpend;
1177
1178 if (*bursts == 1)
1179 return _bursts(pl330, dry_run, buf, pxs, 1);
1180
1181
1182 if (*bursts >= 256*256) {
1183 lcnt1 = 256;
1184 lcnt0 = 256;
1185 cyc = *bursts / lcnt1 / lcnt0;
1186 } else if (*bursts > 256) {
1187 lcnt1 = 256;
1188 lcnt0 = *bursts / lcnt1;
1189 cyc = 1;
1190 } else {
1191 lcnt1 = *bursts;
1192 lcnt0 = 0;
1193 cyc = 1;
1194 }
1195
1196 szlp = _emit_LP(1, buf, 0, 0);
1197 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1198
1199 lpend.cond = ALWAYS;
1200 lpend.forever = false;
1201 lpend.loop = 0;
1202 lpend.bjump = 0;
1203 szlpend = _emit_LPEND(1, buf, &lpend);
1204
1205 if (lcnt0) {
1206 szlp *= 2;
1207 szlpend *= 2;
1208 }
1209
1210
1211
1212
1213
1214
1215 cycmax = (255 - (szlp + szlpend)) / szbrst;
1216
1217 cyc = (cycmax < cyc) ? cycmax : cyc;
1218
1219 off = 0;
1220
1221 if (lcnt0) {
1222 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1223 ljmp0 = off;
1224 }
1225
1226 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1227 ljmp1 = off;
1228
1229 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1230
1231 lpend.cond = ALWAYS;
1232 lpend.forever = false;
1233 lpend.loop = 1;
1234 lpend.bjump = off - ljmp1;
1235 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1236
1237 if (lcnt0) {
1238 lpend.cond = ALWAYS;
1239 lpend.forever = false;
1240 lpend.loop = 0;
1241 lpend.bjump = off - ljmp0;
1242 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1243 }
1244
1245 *bursts = lcnt1 * cyc;
1246 if (lcnt0)
1247 *bursts *= lcnt0;
1248
1249 return off;
1250}
1251
1252static inline int _setup_loops(struct pl330_dmac *pl330,
1253 unsigned dry_run, u8 buf[],
1254 const struct _xfer_spec *pxs)
1255{
1256 struct pl330_xfer *x = &pxs->desc->px;
1257 u32 ccr = pxs->ccr;
1258 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1259 int off = 0;
1260
1261 while (bursts) {
1262 c = bursts;
1263 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1264 bursts -= c;
1265 }
1266
1267 return off;
1268}
1269
1270static inline int _setup_xfer(struct pl330_dmac *pl330,
1271 unsigned dry_run, u8 buf[],
1272 const struct _xfer_spec *pxs)
1273{
1274 struct pl330_xfer *x = &pxs->desc->px;
1275 int off = 0;
1276
1277
1278 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1279
1280 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1281
1282
1283 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1284
1285 return off;
1286}
1287
1288
1289
1290
1291
1292static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1293 struct pl330_thread *thrd, unsigned index,
1294 struct _xfer_spec *pxs)
1295{
1296 struct _pl330_req *req = &thrd->req[index];
1297 struct pl330_xfer *x;
1298 u8 *buf = req->mc_cpu;
1299 int off = 0;
1300
1301 PL330_DBGMC_START(req->mc_bus);
1302
1303
1304 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1305
1306 x = &pxs->desc->px;
1307
1308 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1309 return -EINVAL;
1310
1311 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1312
1313
1314 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1315
1316 off += _emit_END(dry_run, &buf[off]);
1317
1318 return off;
1319}
1320
1321static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1322{
1323 u32 ccr = 0;
1324
1325 if (rqc->src_inc)
1326 ccr |= CC_SRCINC;
1327
1328 if (rqc->dst_inc)
1329 ccr |= CC_DSTINC;
1330
1331
1332 if (rqc->privileged)
1333 ccr |= CC_SRCPRI | CC_DSTPRI;
1334 if (rqc->nonsecure)
1335 ccr |= CC_SRCNS | CC_DSTNS;
1336 if (rqc->insnaccess)
1337 ccr |= CC_SRCIA | CC_DSTIA;
1338
1339 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1340 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1341
1342 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1343 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1344
1345 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1346 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1347
1348 ccr |= (rqc->swap << CC_SWAP_SHFT);
1349
1350 return ccr;
1351}
1352
1353
1354
1355
1356
1357
1358static int pl330_submit_req(struct pl330_thread *thrd,
1359 struct dma_pl330_desc *desc)
1360{
1361 struct pl330_dmac *pl330 = thrd->dmac;
1362 struct _xfer_spec xs;
1363 unsigned long flags;
1364 unsigned idx;
1365 u32 ccr;
1366 int ret = 0;
1367
1368 if (pl330->state == DYING
1369 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1370 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1371 __func__, __LINE__);
1372 return -EAGAIN;
1373 }
1374
1375
1376 if (desc->rqtype != DMA_MEM_TO_MEM &&
1377 desc->peri >= pl330->pcfg.num_peri) {
1378 dev_info(thrd->dmac->ddma.dev,
1379 "%s:%d Invalid peripheral(%u)!\n",
1380 __func__, __LINE__, desc->peri);
1381 return -EINVAL;
1382 }
1383
1384 spin_lock_irqsave(&pl330->lock, flags);
1385
1386 if (_queue_full(thrd)) {
1387 ret = -EAGAIN;
1388 goto xfer_exit;
1389 }
1390
1391
1392 if (!_manager_ns(thrd))
1393 desc->rqcfg.nonsecure = 0;
1394 else
1395 desc->rqcfg.nonsecure = 1;
1396
1397 ccr = _prepare_ccr(&desc->rqcfg);
1398
1399 idx = thrd->req[0].desc == NULL ? 0 : 1;
1400
1401 xs.ccr = ccr;
1402 xs.desc = desc;
1403
1404
1405 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1406 if (ret < 0)
1407 goto xfer_exit;
1408
1409 if (ret > pl330->mcbufsz / 2) {
1410 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1411 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1412 ret = -ENOMEM;
1413 goto xfer_exit;
1414 }
1415
1416
1417 thrd->lstenq = idx;
1418 thrd->req[idx].desc = desc;
1419 _setup_req(pl330, 0, thrd, idx, &xs);
1420
1421 ret = 0;
1422
1423xfer_exit:
1424 spin_unlock_irqrestore(&pl330->lock, flags);
1425
1426 return ret;
1427}
1428
1429static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1430{
1431 struct dma_pl330_chan *pch;
1432 unsigned long flags;
1433
1434 if (!desc)
1435 return;
1436
1437 pch = desc->pchan;
1438
1439
1440 if (!pch)
1441 return;
1442
1443 spin_lock_irqsave(&pch->lock, flags);
1444
1445 desc->status = DONE;
1446
1447 spin_unlock_irqrestore(&pch->lock, flags);
1448
1449 tasklet_schedule(&pch->task);
1450}
1451
1452static void pl330_dotask(unsigned long data)
1453{
1454 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1455 unsigned long flags;
1456 int i;
1457
1458 spin_lock_irqsave(&pl330->lock, flags);
1459
1460
1461 if (pl330->dmac_tbd.reset_dmac) {
1462 pl330->state = DYING;
1463
1464 pl330->dmac_tbd.reset_mngr = true;
1465
1466 pl330->dmac_tbd.reset_dmac = false;
1467 }
1468
1469 if (pl330->dmac_tbd.reset_mngr) {
1470 _stop(pl330->manager);
1471
1472 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1473
1474 pl330->dmac_tbd.reset_mngr = false;
1475 }
1476
1477 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1478
1479 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1480 struct pl330_thread *thrd = &pl330->channels[i];
1481 void __iomem *regs = pl330->base;
1482 enum pl330_op_err err;
1483
1484 _stop(thrd);
1485
1486 if (readl(regs + FSC) & (1 << thrd->id))
1487 err = PL330_ERR_FAIL;
1488 else
1489 err = PL330_ERR_ABORT;
1490
1491 spin_unlock_irqrestore(&pl330->lock, flags);
1492 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1493 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1494 spin_lock_irqsave(&pl330->lock, flags);
1495
1496 thrd->req[0].desc = NULL;
1497 thrd->req[1].desc = NULL;
1498 thrd->req_running = -1;
1499
1500
1501 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1502 }
1503 }
1504
1505 spin_unlock_irqrestore(&pl330->lock, flags);
1506
1507 return;
1508}
1509
1510
1511static int pl330_update(struct pl330_dmac *pl330)
1512{
1513 struct dma_pl330_desc *descdone, *tmp;
1514 unsigned long flags;
1515 void __iomem *regs;
1516 u32 val;
1517 int id, ev, ret = 0;
1518
1519 regs = pl330->base;
1520
1521 spin_lock_irqsave(&pl330->lock, flags);
1522
1523 val = readl(regs + FSM) & 0x1;
1524 if (val)
1525 pl330->dmac_tbd.reset_mngr = true;
1526 else
1527 pl330->dmac_tbd.reset_mngr = false;
1528
1529 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1530 pl330->dmac_tbd.reset_chan |= val;
1531 if (val) {
1532 int i = 0;
1533 while (i < pl330->pcfg.num_chan) {
1534 if (val & (1 << i)) {
1535 dev_info(pl330->ddma.dev,
1536 "Reset Channel-%d\t CS-%x FTC-%x\n",
1537 i, readl(regs + CS(i)),
1538 readl(regs + FTC(i)));
1539 _stop(&pl330->channels[i]);
1540 }
1541 i++;
1542 }
1543 }
1544
1545
1546 val = readl(regs + ES);
1547 if (pl330->pcfg.num_events < 32
1548 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1549 pl330->dmac_tbd.reset_dmac = true;
1550 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1551 __LINE__);
1552 ret = 1;
1553 goto updt_exit;
1554 }
1555
1556 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1557 if (val & (1 << ev)) {
1558 struct pl330_thread *thrd;
1559 u32 inten = readl(regs + INTEN);
1560 int active;
1561
1562
1563 if (inten & (1 << ev))
1564 writel(1 << ev, regs + INTCLR);
1565
1566 ret = 1;
1567
1568 id = pl330->events[ev];
1569
1570 thrd = &pl330->channels[id];
1571
1572 active = thrd->req_running;
1573 if (active == -1)
1574 continue;
1575
1576
1577 descdone = thrd->req[active].desc;
1578 thrd->req[active].desc = NULL;
1579
1580 thrd->req_running = -1;
1581
1582
1583 _start(thrd);
1584
1585
1586 list_add_tail(&descdone->rqd, &pl330->req_done);
1587 }
1588 }
1589
1590
1591 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1592 list_del(&descdone->rqd);
1593 spin_unlock_irqrestore(&pl330->lock, flags);
1594 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1595 spin_lock_irqsave(&pl330->lock, flags);
1596 }
1597
1598updt_exit:
1599 spin_unlock_irqrestore(&pl330->lock, flags);
1600
1601 if (pl330->dmac_tbd.reset_dmac
1602 || pl330->dmac_tbd.reset_mngr
1603 || pl330->dmac_tbd.reset_chan) {
1604 ret = 1;
1605 tasklet_schedule(&pl330->tasks);
1606 }
1607
1608 return ret;
1609}
1610
1611
1612static inline int _alloc_event(struct pl330_thread *thrd)
1613{
1614 struct pl330_dmac *pl330 = thrd->dmac;
1615 int ev;
1616
1617 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1618 if (pl330->events[ev] == -1) {
1619 pl330->events[ev] = thrd->id;
1620 return ev;
1621 }
1622
1623 return -1;
1624}
1625
1626static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1627{
1628 return pl330->pcfg.irq_ns & (1 << i);
1629}
1630
1631
1632
1633
1634static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1635{
1636 struct pl330_thread *thrd = NULL;
1637 int chans, i;
1638
1639 if (pl330->state == DYING)
1640 return NULL;
1641
1642 chans = pl330->pcfg.num_chan;
1643
1644 for (i = 0; i < chans; i++) {
1645 thrd = &pl330->channels[i];
1646 if ((thrd->free) && (!_manager_ns(thrd) ||
1647 _chan_ns(pl330, i))) {
1648 thrd->ev = _alloc_event(thrd);
1649 if (thrd->ev >= 0) {
1650 thrd->free = false;
1651 thrd->lstenq = 1;
1652 thrd->req[0].desc = NULL;
1653 thrd->req[1].desc = NULL;
1654 thrd->req_running = -1;
1655 break;
1656 }
1657 }
1658 thrd = NULL;
1659 }
1660
1661 return thrd;
1662}
1663
1664
1665static inline void _free_event(struct pl330_thread *thrd, int ev)
1666{
1667 struct pl330_dmac *pl330 = thrd->dmac;
1668
1669
1670 if (ev >= 0 && ev < pl330->pcfg.num_events
1671 && pl330->events[ev] == thrd->id)
1672 pl330->events[ev] = -1;
1673}
1674
1675static void pl330_release_channel(struct pl330_thread *thrd)
1676{
1677 struct pl330_dmac *pl330;
1678
1679 if (!thrd || thrd->free)
1680 return;
1681
1682 _stop(thrd);
1683
1684 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1685 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1686
1687 pl330 = thrd->dmac;
1688
1689 _free_event(thrd, thrd->ev);
1690 thrd->free = true;
1691}
1692
1693
1694
1695
1696static void read_dmac_config(struct pl330_dmac *pl330)
1697{
1698 void __iomem *regs = pl330->base;
1699 u32 val;
1700
1701 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1702 val &= CRD_DATA_WIDTH_MASK;
1703 pl330->pcfg.data_bus_width = 8 * (1 << val);
1704
1705 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1706 val &= CRD_DATA_BUFF_MASK;
1707 pl330->pcfg.data_buf_dep = val + 1;
1708
1709 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1710 val &= CR0_NUM_CHANS_MASK;
1711 val += 1;
1712 pl330->pcfg.num_chan = val;
1713
1714 val = readl(regs + CR0);
1715 if (val & CR0_PERIPH_REQ_SET) {
1716 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1717 val += 1;
1718 pl330->pcfg.num_peri = val;
1719 pl330->pcfg.peri_ns = readl(regs + CR4);
1720 } else {
1721 pl330->pcfg.num_peri = 0;
1722 }
1723
1724 val = readl(regs + CR0);
1725 if (val & CR0_BOOT_MAN_NS)
1726 pl330->pcfg.mode |= DMAC_MODE_NS;
1727 else
1728 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1729
1730 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1731 val &= CR0_NUM_EVENTS_MASK;
1732 val += 1;
1733 pl330->pcfg.num_events = val;
1734
1735 pl330->pcfg.irq_ns = readl(regs + CR3);
1736}
1737
1738static inline void _reset_thread(struct pl330_thread *thrd)
1739{
1740 struct pl330_dmac *pl330 = thrd->dmac;
1741
1742 thrd->req[0].mc_cpu = pl330->mcode_cpu
1743 + (thrd->id * pl330->mcbufsz);
1744 thrd->req[0].mc_bus = pl330->mcode_bus
1745 + (thrd->id * pl330->mcbufsz);
1746 thrd->req[0].desc = NULL;
1747
1748 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1749 + pl330->mcbufsz / 2;
1750 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1751 + pl330->mcbufsz / 2;
1752 thrd->req[1].desc = NULL;
1753
1754 thrd->req_running = -1;
1755}
1756
1757static int dmac_alloc_threads(struct pl330_dmac *pl330)
1758{
1759 int chans = pl330->pcfg.num_chan;
1760 struct pl330_thread *thrd;
1761 int i;
1762
1763
1764 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1765 GFP_KERNEL);
1766 if (!pl330->channels)
1767 return -ENOMEM;
1768
1769
1770 for (i = 0; i < chans; i++) {
1771 thrd = &pl330->channels[i];
1772 thrd->id = i;
1773 thrd->dmac = pl330;
1774 _reset_thread(thrd);
1775 thrd->free = true;
1776 }
1777
1778
1779 thrd = &pl330->channels[chans];
1780 thrd->id = chans;
1781 thrd->dmac = pl330;
1782 thrd->free = false;
1783 pl330->manager = thrd;
1784
1785 return 0;
1786}
1787
1788static int dmac_alloc_resources(struct pl330_dmac *pl330)
1789{
1790 int chans = pl330->pcfg.num_chan;
1791 int ret;
1792
1793
1794
1795
1796
1797 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1798 chans * pl330->mcbufsz,
1799 &pl330->mcode_bus, GFP_KERNEL,
1800 DMA_ATTR_PRIVILEGED);
1801 if (!pl330->mcode_cpu) {
1802 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1803 __func__, __LINE__);
1804 return -ENOMEM;
1805 }
1806
1807 ret = dmac_alloc_threads(pl330);
1808 if (ret) {
1809 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1810 __func__, __LINE__);
1811 dma_free_coherent(pl330->ddma.dev,
1812 chans * pl330->mcbufsz,
1813 pl330->mcode_cpu, pl330->mcode_bus);
1814 return ret;
1815 }
1816
1817 return 0;
1818}
1819
1820static int pl330_add(struct pl330_dmac *pl330)
1821{
1822 int i, ret;
1823
1824
1825 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1826 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1827 pl330->pcfg.periph_id);
1828 return -EINVAL;
1829 }
1830
1831
1832 read_dmac_config(pl330);
1833
1834 if (pl330->pcfg.num_events == 0) {
1835 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1836 __func__, __LINE__);
1837 return -EINVAL;
1838 }
1839
1840 spin_lock_init(&pl330->lock);
1841
1842 INIT_LIST_HEAD(&pl330->req_done);
1843
1844
1845 if (!pl330->mcbufsz)
1846 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1847
1848
1849 for (i = 0; i < pl330->pcfg.num_events; i++)
1850 pl330->events[i] = -1;
1851
1852
1853 ret = dmac_alloc_resources(pl330);
1854 if (ret) {
1855 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1856 return ret;
1857 }
1858
1859 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1860
1861 pl330->state = INIT;
1862
1863 return 0;
1864}
1865
1866static int dmac_free_threads(struct pl330_dmac *pl330)
1867{
1868 struct pl330_thread *thrd;
1869 int i;
1870
1871
1872 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1873 thrd = &pl330->channels[i];
1874 pl330_release_channel(thrd);
1875 }
1876
1877
1878 kfree(pl330->channels);
1879
1880 return 0;
1881}
1882
1883static void pl330_del(struct pl330_dmac *pl330)
1884{
1885 pl330->state = UNINIT;
1886
1887 tasklet_kill(&pl330->tasks);
1888
1889
1890 dmac_free_threads(pl330);
1891
1892 dma_free_coherent(pl330->ddma.dev,
1893 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1894 pl330->mcode_bus);
1895}
1896
1897
1898static struct amba_driver pl330_driver;
1899
1900static inline struct dma_pl330_chan *
1901to_pchan(struct dma_chan *ch)
1902{
1903 if (!ch)
1904 return NULL;
1905
1906 return container_of(ch, struct dma_pl330_chan, chan);
1907}
1908
1909static inline struct dma_pl330_desc *
1910to_desc(struct dma_async_tx_descriptor *tx)
1911{
1912 return container_of(tx, struct dma_pl330_desc, txd);
1913}
1914
1915static inline void fill_queue(struct dma_pl330_chan *pch)
1916{
1917 struct dma_pl330_desc *desc;
1918 int ret;
1919
1920 list_for_each_entry(desc, &pch->work_list, node) {
1921
1922
1923 if (desc->status == BUSY)
1924 continue;
1925
1926 ret = pl330_submit_req(pch->thread, desc);
1927 if (!ret) {
1928 desc->status = BUSY;
1929 } else if (ret == -EAGAIN) {
1930
1931 break;
1932 } else {
1933
1934 desc->status = DONE;
1935 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
1936 __func__, __LINE__, desc->txd.cookie);
1937 tasklet_schedule(&pch->task);
1938 }
1939 }
1940}
1941
1942static void pl330_tasklet(unsigned long data)
1943{
1944 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
1945 struct dma_pl330_desc *desc, *_dt;
1946 unsigned long flags;
1947 bool power_down = false;
1948
1949 spin_lock_irqsave(&pch->lock, flags);
1950
1951
1952 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
1953 if (desc->status == DONE) {
1954 if (!pch->cyclic)
1955 dma_cookie_complete(&desc->txd);
1956 list_move_tail(&desc->node, &pch->completed_list);
1957 }
1958
1959
1960 fill_queue(pch);
1961
1962 if (list_empty(&pch->work_list)) {
1963 spin_lock(&pch->thread->dmac->lock);
1964 _stop(pch->thread);
1965 spin_unlock(&pch->thread->dmac->lock);
1966 power_down = true;
1967 pch->active = false;
1968 } else {
1969
1970 spin_lock(&pch->thread->dmac->lock);
1971 _start(pch->thread);
1972 spin_unlock(&pch->thread->dmac->lock);
1973 }
1974
1975 while (!list_empty(&pch->completed_list)) {
1976 struct dmaengine_desc_callback cb;
1977
1978 desc = list_first_entry(&pch->completed_list,
1979 struct dma_pl330_desc, node);
1980
1981 dmaengine_desc_get_callback(&desc->txd, &cb);
1982
1983 if (pch->cyclic) {
1984 desc->status = PREP;
1985 list_move_tail(&desc->node, &pch->work_list);
1986 if (power_down) {
1987 pch->active = true;
1988 spin_lock(&pch->thread->dmac->lock);
1989 _start(pch->thread);
1990 spin_unlock(&pch->thread->dmac->lock);
1991 power_down = false;
1992 }
1993 } else {
1994 desc->status = FREE;
1995 list_move_tail(&desc->node, &pch->dmac->desc_pool);
1996 }
1997
1998 dma_descriptor_unmap(&desc->txd);
1999
2000 if (dmaengine_desc_callback_valid(&cb)) {
2001 spin_unlock_irqrestore(&pch->lock, flags);
2002 dmaengine_desc_callback_invoke(&cb, NULL);
2003 spin_lock_irqsave(&pch->lock, flags);
2004 }
2005 }
2006 spin_unlock_irqrestore(&pch->lock, flags);
2007
2008
2009 if (power_down) {
2010 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2011 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2012 }
2013}
2014
2015static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2016 struct of_dma *ofdma)
2017{
2018 int count = dma_spec->args_count;
2019 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2020 unsigned int chan_id;
2021
2022 if (!pl330)
2023 return NULL;
2024
2025 if (count != 1)
2026 return NULL;
2027
2028 chan_id = dma_spec->args[0];
2029 if (chan_id >= pl330->num_peripherals)
2030 return NULL;
2031
2032 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2033}
2034
2035static int pl330_alloc_chan_resources(struct dma_chan *chan)
2036{
2037 struct dma_pl330_chan *pch = to_pchan(chan);
2038 struct pl330_dmac *pl330 = pch->dmac;
2039 unsigned long flags;
2040
2041 spin_lock_irqsave(&pl330->lock, flags);
2042
2043 dma_cookie_init(chan);
2044 pch->cyclic = false;
2045
2046 pch->thread = pl330_request_channel(pl330);
2047 if (!pch->thread) {
2048 spin_unlock_irqrestore(&pl330->lock, flags);
2049 return -ENOMEM;
2050 }
2051
2052 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2053
2054 spin_unlock_irqrestore(&pl330->lock, flags);
2055
2056 return 1;
2057}
2058
2059
2060
2061
2062
2063static enum dma_data_direction
2064pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
2065{
2066 switch (dir) {
2067 case DMA_MEM_TO_DEV:
2068 return DMA_FROM_DEVICE;
2069 case DMA_DEV_TO_MEM:
2070 return DMA_TO_DEVICE;
2071 case DMA_DEV_TO_DEV:
2072 return DMA_BIDIRECTIONAL;
2073 default:
2074 return DMA_NONE;
2075 }
2076}
2077
2078static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
2079{
2080 if (pch->dir != DMA_NONE)
2081 dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
2082 1 << pch->burst_sz, pch->dir, 0);
2083 pch->dir = DMA_NONE;
2084}
2085
2086
2087static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
2088 enum dma_transfer_direction dir)
2089{
2090 struct device *dev = pch->chan.device->dev;
2091 enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
2092
2093
2094 if (pch->dir == dma_dir)
2095 return true;
2096
2097 pl330_unprep_slave_fifo(pch);
2098 pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
2099 1 << pch->burst_sz, dma_dir, 0);
2100 if (dma_mapping_error(dev, pch->fifo_dma))
2101 return false;
2102
2103 pch->dir = dma_dir;
2104 return true;
2105}
2106
2107static int pl330_config(struct dma_chan *chan,
2108 struct dma_slave_config *slave_config)
2109{
2110 struct dma_pl330_chan *pch = to_pchan(chan);
2111
2112 pl330_unprep_slave_fifo(pch);
2113 if (slave_config->direction == DMA_MEM_TO_DEV) {
2114 if (slave_config->dst_addr)
2115 pch->fifo_addr = slave_config->dst_addr;
2116 if (slave_config->dst_addr_width)
2117 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2118 if (slave_config->dst_maxburst)
2119 pch->burst_len = slave_config->dst_maxburst;
2120 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2121 if (slave_config->src_addr)
2122 pch->fifo_addr = slave_config->src_addr;
2123 if (slave_config->src_addr_width)
2124 pch->burst_sz = __ffs(slave_config->src_addr_width);
2125 if (slave_config->src_maxburst)
2126 pch->burst_len = slave_config->src_maxburst;
2127 }
2128
2129 return 0;
2130}
2131
2132static int pl330_terminate_all(struct dma_chan *chan)
2133{
2134 struct dma_pl330_chan *pch = to_pchan(chan);
2135 struct dma_pl330_desc *desc;
2136 unsigned long flags;
2137 struct pl330_dmac *pl330 = pch->dmac;
2138 LIST_HEAD(list);
2139 bool power_down = false;
2140
2141 pm_runtime_get_sync(pl330->ddma.dev);
2142 spin_lock_irqsave(&pch->lock, flags);
2143 spin_lock(&pl330->lock);
2144 _stop(pch->thread);
2145 spin_unlock(&pl330->lock);
2146
2147 pch->thread->req[0].desc = NULL;
2148 pch->thread->req[1].desc = NULL;
2149 pch->thread->req_running = -1;
2150 power_down = pch->active;
2151 pch->active = false;
2152
2153
2154 list_for_each_entry(desc, &pch->submitted_list, node) {
2155 desc->status = FREE;
2156 dma_cookie_complete(&desc->txd);
2157 }
2158
2159 list_for_each_entry(desc, &pch->work_list , node) {
2160 desc->status = FREE;
2161 dma_cookie_complete(&desc->txd);
2162 }
2163
2164 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2165 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2166 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2167 spin_unlock_irqrestore(&pch->lock, flags);
2168 pm_runtime_mark_last_busy(pl330->ddma.dev);
2169 if (power_down)
2170 pm_runtime_put_autosuspend(pl330->ddma.dev);
2171 pm_runtime_put_autosuspend(pl330->ddma.dev);
2172
2173 return 0;
2174}
2175
2176
2177
2178
2179
2180
2181
2182
2183static int pl330_pause(struct dma_chan *chan)
2184{
2185 struct dma_pl330_chan *pch = to_pchan(chan);
2186 struct pl330_dmac *pl330 = pch->dmac;
2187 unsigned long flags;
2188
2189 pm_runtime_get_sync(pl330->ddma.dev);
2190 spin_lock_irqsave(&pch->lock, flags);
2191
2192 spin_lock(&pl330->lock);
2193 _stop(pch->thread);
2194 spin_unlock(&pl330->lock);
2195
2196 spin_unlock_irqrestore(&pch->lock, flags);
2197 pm_runtime_mark_last_busy(pl330->ddma.dev);
2198 pm_runtime_put_autosuspend(pl330->ddma.dev);
2199
2200 return 0;
2201}
2202
2203static void pl330_free_chan_resources(struct dma_chan *chan)
2204{
2205 struct dma_pl330_chan *pch = to_pchan(chan);
2206 struct pl330_dmac *pl330 = pch->dmac;
2207 unsigned long flags;
2208
2209 tasklet_kill(&pch->task);
2210
2211 pm_runtime_get_sync(pch->dmac->ddma.dev);
2212 spin_lock_irqsave(&pl330->lock, flags);
2213
2214 pl330_release_channel(pch->thread);
2215 pch->thread = NULL;
2216
2217 if (pch->cyclic)
2218 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2219
2220 spin_unlock_irqrestore(&pl330->lock, flags);
2221 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2222 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2223 pl330_unprep_slave_fifo(pch);
2224}
2225
2226static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2227 struct dma_pl330_desc *desc)
2228{
2229 struct pl330_thread *thrd = pch->thread;
2230 struct pl330_dmac *pl330 = pch->dmac;
2231 void __iomem *regs = thrd->dmac->base;
2232 u32 val, addr;
2233
2234 pm_runtime_get_sync(pl330->ddma.dev);
2235 val = addr = 0;
2236 if (desc->rqcfg.src_inc) {
2237 val = readl(regs + SA(thrd->id));
2238 addr = desc->px.src_addr;
2239 } else {
2240 val = readl(regs + DA(thrd->id));
2241 addr = desc->px.dst_addr;
2242 }
2243 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2244 pm_runtime_put_autosuspend(pl330->ddma.dev);
2245
2246
2247 if (!val)
2248 return 0;
2249
2250 return val - addr;
2251}
2252
2253static enum dma_status
2254pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2255 struct dma_tx_state *txstate)
2256{
2257 enum dma_status ret;
2258 unsigned long flags;
2259 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2260 struct dma_pl330_chan *pch = to_pchan(chan);
2261 unsigned int transferred, residual = 0;
2262
2263 ret = dma_cookie_status(chan, cookie, txstate);
2264
2265 if (!txstate)
2266 return ret;
2267
2268 if (ret == DMA_COMPLETE)
2269 goto out;
2270
2271 spin_lock_irqsave(&pch->lock, flags);
2272 spin_lock(&pch->thread->dmac->lock);
2273
2274 if (pch->thread->req_running != -1)
2275 running = pch->thread->req[pch->thread->req_running].desc;
2276
2277 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2278
2279
2280 list_for_each_entry(desc, &pch->work_list, node) {
2281 if (desc->status == DONE)
2282 transferred = desc->bytes_requested;
2283 else if (running && desc == running)
2284 transferred =
2285 pl330_get_current_xferred_count(pch, desc);
2286 else if (desc->status == BUSY)
2287
2288
2289
2290
2291 if (desc == last_enq)
2292 transferred = 0;
2293 else
2294 transferred = desc->bytes_requested;
2295 else
2296 transferred = 0;
2297 residual += desc->bytes_requested - transferred;
2298 if (desc->txd.cookie == cookie) {
2299 switch (desc->status) {
2300 case DONE:
2301 ret = DMA_COMPLETE;
2302 break;
2303 case PREP:
2304 case BUSY:
2305 ret = DMA_IN_PROGRESS;
2306 break;
2307 default:
2308 WARN_ON(1);
2309 }
2310 break;
2311 }
2312 if (desc->last)
2313 residual = 0;
2314 }
2315 spin_unlock(&pch->thread->dmac->lock);
2316 spin_unlock_irqrestore(&pch->lock, flags);
2317
2318out:
2319 dma_set_residue(txstate, residual);
2320
2321 return ret;
2322}
2323
2324static void pl330_issue_pending(struct dma_chan *chan)
2325{
2326 struct dma_pl330_chan *pch = to_pchan(chan);
2327 unsigned long flags;
2328
2329 spin_lock_irqsave(&pch->lock, flags);
2330 if (list_empty(&pch->work_list)) {
2331
2332
2333
2334
2335
2336 WARN_ON(list_empty(&pch->submitted_list));
2337 pch->active = true;
2338 pm_runtime_get_sync(pch->dmac->ddma.dev);
2339 }
2340 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2341 spin_unlock_irqrestore(&pch->lock, flags);
2342
2343 pl330_tasklet((unsigned long)pch);
2344}
2345
2346
2347
2348
2349
2350
2351static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2352{
2353 struct dma_pl330_desc *desc, *last = to_desc(tx);
2354 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2355 dma_cookie_t cookie;
2356 unsigned long flags;
2357
2358 spin_lock_irqsave(&pch->lock, flags);
2359
2360
2361 while (!list_empty(&last->node)) {
2362 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2363 if (pch->cyclic) {
2364 desc->txd.callback = last->txd.callback;
2365 desc->txd.callback_param = last->txd.callback_param;
2366 }
2367 desc->last = false;
2368
2369 dma_cookie_assign(&desc->txd);
2370
2371 list_move_tail(&desc->node, &pch->submitted_list);
2372 }
2373
2374 last->last = true;
2375 cookie = dma_cookie_assign(&last->txd);
2376 list_add_tail(&last->node, &pch->submitted_list);
2377 spin_unlock_irqrestore(&pch->lock, flags);
2378
2379 return cookie;
2380}
2381
2382static inline void _init_desc(struct dma_pl330_desc *desc)
2383{
2384 desc->rqcfg.swap = SWAP_NO;
2385 desc->rqcfg.scctl = CCTRL0;
2386 desc->rqcfg.dcctl = CCTRL0;
2387 desc->txd.tx_submit = pl330_tx_submit;
2388
2389 INIT_LIST_HEAD(&desc->node);
2390}
2391
2392
2393static int add_desc(struct list_head *pool, spinlock_t *lock,
2394 gfp_t flg, int count)
2395{
2396 struct dma_pl330_desc *desc;
2397 unsigned long flags;
2398 int i;
2399
2400 desc = kcalloc(count, sizeof(*desc), flg);
2401 if (!desc)
2402 return 0;
2403
2404 spin_lock_irqsave(lock, flags);
2405
2406 for (i = 0; i < count; i++) {
2407 _init_desc(&desc[i]);
2408 list_add_tail(&desc[i].node, pool);
2409 }
2410
2411 spin_unlock_irqrestore(lock, flags);
2412
2413 return count;
2414}
2415
2416static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
2417 spinlock_t *lock)
2418{
2419 struct dma_pl330_desc *desc = NULL;
2420 unsigned long flags;
2421
2422 spin_lock_irqsave(lock, flags);
2423
2424 if (!list_empty(pool)) {
2425 desc = list_entry(pool->next,
2426 struct dma_pl330_desc, node);
2427
2428 list_del_init(&desc->node);
2429
2430 desc->status = PREP;
2431 desc->txd.callback = NULL;
2432 }
2433
2434 spin_unlock_irqrestore(lock, flags);
2435
2436 return desc;
2437}
2438
2439static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2440{
2441 struct pl330_dmac *pl330 = pch->dmac;
2442 u8 *peri_id = pch->chan.private;
2443 struct dma_pl330_desc *desc;
2444
2445
2446 desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
2447
2448
2449 if (!desc) {
2450 DEFINE_SPINLOCK(lock);
2451 LIST_HEAD(pool);
2452
2453 if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
2454 return NULL;
2455
2456 desc = pluck_desc(&pool, &lock);
2457 WARN_ON(!desc || !list_empty(&pool));
2458 }
2459
2460
2461 desc->pchan = pch;
2462 desc->txd.cookie = 0;
2463 async_tx_ack(&desc->txd);
2464
2465 desc->peri = peri_id ? pch->chan.chan_id : 0;
2466 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2467
2468 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2469
2470 return desc;
2471}
2472
2473static inline void fill_px(struct pl330_xfer *px,
2474 dma_addr_t dst, dma_addr_t src, size_t len)
2475{
2476 px->bytes = len;
2477 px->dst_addr = dst;
2478 px->src_addr = src;
2479}
2480
2481static struct dma_pl330_desc *
2482__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2483 dma_addr_t src, size_t len)
2484{
2485 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2486
2487 if (!desc) {
2488 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2489 __func__, __LINE__);
2490 return NULL;
2491 }
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503 fill_px(&desc->px, dst, src, len);
2504
2505 return desc;
2506}
2507
2508
2509static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2510{
2511 struct dma_pl330_chan *pch = desc->pchan;
2512 struct pl330_dmac *pl330 = pch->dmac;
2513 int burst_len;
2514
2515 burst_len = pl330->pcfg.data_bus_width / 8;
2516 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2517 burst_len >>= desc->rqcfg.brst_size;
2518
2519
2520 if (burst_len > 16)
2521 burst_len = 16;
2522
2523 while (burst_len > 1) {
2524 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2525 break;
2526 burst_len--;
2527 }
2528
2529 return burst_len;
2530}
2531
2532static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2533 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2534 size_t period_len, enum dma_transfer_direction direction,
2535 unsigned long flags)
2536{
2537 struct dma_pl330_desc *desc = NULL, *first = NULL;
2538 struct dma_pl330_chan *pch = to_pchan(chan);
2539 struct pl330_dmac *pl330 = pch->dmac;
2540 unsigned int i;
2541 dma_addr_t dst;
2542 dma_addr_t src;
2543
2544 if (len % period_len != 0)
2545 return NULL;
2546
2547 if (!is_slave_direction(direction)) {
2548 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2549 __func__, __LINE__);
2550 return NULL;
2551 }
2552
2553 if (!pl330_prep_slave_fifo(pch, direction))
2554 return NULL;
2555
2556 for (i = 0; i < len / period_len; i++) {
2557 desc = pl330_get_desc(pch);
2558 if (!desc) {
2559 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2560 __func__, __LINE__);
2561
2562 if (!first)
2563 return NULL;
2564
2565 spin_lock_irqsave(&pl330->pool_lock, flags);
2566
2567 while (!list_empty(&first->node)) {
2568 desc = list_entry(first->node.next,
2569 struct dma_pl330_desc, node);
2570 list_move_tail(&desc->node, &pl330->desc_pool);
2571 }
2572
2573 list_move_tail(&first->node, &pl330->desc_pool);
2574
2575 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2576
2577 return NULL;
2578 }
2579
2580 switch (direction) {
2581 case DMA_MEM_TO_DEV:
2582 desc->rqcfg.src_inc = 1;
2583 desc->rqcfg.dst_inc = 0;
2584 src = dma_addr;
2585 dst = pch->fifo_dma;
2586 break;
2587 case DMA_DEV_TO_MEM:
2588 desc->rqcfg.src_inc = 0;
2589 desc->rqcfg.dst_inc = 1;
2590 src = pch->fifo_dma;
2591 dst = dma_addr;
2592 break;
2593 default:
2594 break;
2595 }
2596
2597 desc->rqtype = direction;
2598 desc->rqcfg.brst_size = pch->burst_sz;
2599 desc->rqcfg.brst_len = 1;
2600 desc->bytes_requested = period_len;
2601 fill_px(&desc->px, dst, src, period_len);
2602
2603 if (!first)
2604 first = desc;
2605 else
2606 list_add_tail(&desc->node, &first->node);
2607
2608 dma_addr += period_len;
2609 }
2610
2611 if (!desc)
2612 return NULL;
2613
2614 pch->cyclic = true;
2615 desc->txd.flags = flags;
2616
2617 return &desc->txd;
2618}
2619
2620static struct dma_async_tx_descriptor *
2621pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2622 dma_addr_t src, size_t len, unsigned long flags)
2623{
2624 struct dma_pl330_desc *desc;
2625 struct dma_pl330_chan *pch = to_pchan(chan);
2626 struct pl330_dmac *pl330;
2627 int burst;
2628
2629 if (unlikely(!pch || !len))
2630 return NULL;
2631
2632 pl330 = pch->dmac;
2633
2634 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2635 if (!desc)
2636 return NULL;
2637
2638 desc->rqcfg.src_inc = 1;
2639 desc->rqcfg.dst_inc = 1;
2640 desc->rqtype = DMA_MEM_TO_MEM;
2641
2642
2643 burst = pl330->pcfg.data_bus_width / 8;
2644
2645
2646
2647
2648
2649
2650 while ((src | dst | len) & (burst - 1))
2651 burst /= 2;
2652
2653 desc->rqcfg.brst_size = 0;
2654 while (burst != (1 << desc->rqcfg.brst_size))
2655 desc->rqcfg.brst_size++;
2656
2657
2658
2659
2660
2661 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2662 desc->rqcfg.brst_len = 1;
2663
2664 desc->rqcfg.brst_len = get_burst_len(desc, len);
2665 desc->bytes_requested = len;
2666
2667 desc->txd.flags = flags;
2668
2669 return &desc->txd;
2670}
2671
2672static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2673 struct dma_pl330_desc *first)
2674{
2675 unsigned long flags;
2676 struct dma_pl330_desc *desc;
2677
2678 if (!first)
2679 return;
2680
2681 spin_lock_irqsave(&pl330->pool_lock, flags);
2682
2683 while (!list_empty(&first->node)) {
2684 desc = list_entry(first->node.next,
2685 struct dma_pl330_desc, node);
2686 list_move_tail(&desc->node, &pl330->desc_pool);
2687 }
2688
2689 list_move_tail(&first->node, &pl330->desc_pool);
2690
2691 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2692}
2693
2694static struct dma_async_tx_descriptor *
2695pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2696 unsigned int sg_len, enum dma_transfer_direction direction,
2697 unsigned long flg, void *context)
2698{
2699 struct dma_pl330_desc *first, *desc = NULL;
2700 struct dma_pl330_chan *pch = to_pchan(chan);
2701 struct scatterlist *sg;
2702 int i;
2703
2704 if (unlikely(!pch || !sgl || !sg_len))
2705 return NULL;
2706
2707 if (!pl330_prep_slave_fifo(pch, direction))
2708 return NULL;
2709
2710 first = NULL;
2711
2712 for_each_sg(sgl, sg, sg_len, i) {
2713
2714 desc = pl330_get_desc(pch);
2715 if (!desc) {
2716 struct pl330_dmac *pl330 = pch->dmac;
2717
2718 dev_err(pch->dmac->ddma.dev,
2719 "%s:%d Unable to fetch desc\n",
2720 __func__, __LINE__);
2721 __pl330_giveback_desc(pl330, first);
2722
2723 return NULL;
2724 }
2725
2726 if (!first)
2727 first = desc;
2728 else
2729 list_add_tail(&desc->node, &first->node);
2730
2731 if (direction == DMA_MEM_TO_DEV) {
2732 desc->rqcfg.src_inc = 1;
2733 desc->rqcfg.dst_inc = 0;
2734 fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
2735 sg_dma_len(sg));
2736 } else {
2737 desc->rqcfg.src_inc = 0;
2738 desc->rqcfg.dst_inc = 1;
2739 fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
2740 sg_dma_len(sg));
2741 }
2742
2743 desc->rqcfg.brst_size = pch->burst_sz;
2744 desc->rqcfg.brst_len = 1;
2745 desc->rqtype = direction;
2746 desc->bytes_requested = sg_dma_len(sg);
2747 }
2748
2749
2750 desc->txd.flags = flg;
2751 return &desc->txd;
2752}
2753
2754static irqreturn_t pl330_irq_handler(int irq, void *data)
2755{
2756 if (pl330_update(data))
2757 return IRQ_HANDLED;
2758 else
2759 return IRQ_NONE;
2760}
2761
2762#define PL330_DMA_BUSWIDTHS \
2763 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2764 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2765 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2766 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2767 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2768
2769
2770
2771
2772
2773
2774
2775static int __maybe_unused pl330_suspend(struct device *dev)
2776{
2777 struct amba_device *pcdev = to_amba_device(dev);
2778
2779 pm_runtime_disable(dev);
2780
2781 if (!pm_runtime_status_suspended(dev)) {
2782
2783 amba_pclk_disable(pcdev);
2784 }
2785 amba_pclk_unprepare(pcdev);
2786
2787 return 0;
2788}
2789
2790static int __maybe_unused pl330_resume(struct device *dev)
2791{
2792 struct amba_device *pcdev = to_amba_device(dev);
2793 int ret;
2794
2795 ret = amba_pclk_prepare(pcdev);
2796 if (ret)
2797 return ret;
2798
2799 if (!pm_runtime_status_suspended(dev))
2800 ret = amba_pclk_enable(pcdev);
2801
2802 pm_runtime_enable(dev);
2803
2804 return ret;
2805}
2806
2807static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2808
2809static int
2810pl330_probe(struct amba_device *adev, const struct amba_id *id)
2811{
2812 struct pl330_config *pcfg;
2813 struct pl330_dmac *pl330;
2814 struct dma_pl330_chan *pch, *_p;
2815 struct dma_device *pd;
2816 struct resource *res;
2817 int i, ret, irq;
2818 int num_chan;
2819 struct device_node *np = adev->dev.of_node;
2820
2821 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2822 if (ret)
2823 return ret;
2824
2825
2826 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2827 if (!pl330)
2828 return -ENOMEM;
2829
2830 pd = &pl330->ddma;
2831 pd->dev = &adev->dev;
2832
2833 pl330->mcbufsz = 0;
2834
2835
2836 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2837 if (of_property_read_bool(np, of_quirks[i].quirk))
2838 pl330->quirks |= of_quirks[i].id;
2839
2840 res = &adev->res;
2841 pl330->base = devm_ioremap_resource(&adev->dev, res);
2842 if (IS_ERR(pl330->base))
2843 return PTR_ERR(pl330->base);
2844
2845 amba_set_drvdata(adev, pl330);
2846
2847 for (i = 0; i < AMBA_NR_IRQS; i++) {
2848 irq = adev->irq[i];
2849 if (irq) {
2850 ret = devm_request_irq(&adev->dev, irq,
2851 pl330_irq_handler, 0,
2852 dev_name(&adev->dev), pl330);
2853 if (ret)
2854 return ret;
2855 } else {
2856 break;
2857 }
2858 }
2859
2860 pcfg = &pl330->pcfg;
2861
2862 pcfg->periph_id = adev->periphid;
2863 ret = pl330_add(pl330);
2864 if (ret)
2865 return ret;
2866
2867 INIT_LIST_HEAD(&pl330->desc_pool);
2868 spin_lock_init(&pl330->pool_lock);
2869
2870
2871 if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
2872 GFP_KERNEL, NR_DEFAULT_DESC))
2873 dev_warn(&adev->dev, "unable to allocate desc\n");
2874
2875 INIT_LIST_HEAD(&pd->channels);
2876
2877
2878 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2879
2880 pl330->num_peripherals = num_chan;
2881
2882 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2883 if (!pl330->peripherals) {
2884 ret = -ENOMEM;
2885 goto probe_err2;
2886 }
2887
2888 for (i = 0; i < num_chan; i++) {
2889 pch = &pl330->peripherals[i];
2890
2891 pch->chan.private = adev->dev.of_node;
2892 INIT_LIST_HEAD(&pch->submitted_list);
2893 INIT_LIST_HEAD(&pch->work_list);
2894 INIT_LIST_HEAD(&pch->completed_list);
2895 spin_lock_init(&pch->lock);
2896 pch->thread = NULL;
2897 pch->chan.device = pd;
2898 pch->dmac = pl330;
2899 pch->dir = DMA_NONE;
2900
2901
2902 list_add_tail(&pch->chan.device_node, &pd->channels);
2903 }
2904
2905 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2906 if (pcfg->num_peri) {
2907 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2908 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2909 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2910 }
2911
2912 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2913 pd->device_free_chan_resources = pl330_free_chan_resources;
2914 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2915 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2916 pd->device_tx_status = pl330_tx_status;
2917 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2918 pd->device_config = pl330_config;
2919 pd->device_pause = pl330_pause;
2920 pd->device_terminate_all = pl330_terminate_all;
2921 pd->device_issue_pending = pl330_issue_pending;
2922 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2923 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2924 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2925 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2926 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
2927 1 : PL330_MAX_BURST);
2928
2929 ret = dma_async_device_register(pd);
2930 if (ret) {
2931 dev_err(&adev->dev, "unable to register DMAC\n");
2932 goto probe_err3;
2933 }
2934
2935 if (adev->dev.of_node) {
2936 ret = of_dma_controller_register(adev->dev.of_node,
2937 of_dma_pl330_xlate, pl330);
2938 if (ret) {
2939 dev_err(&adev->dev,
2940 "unable to register DMA to the generic DT DMA helpers\n");
2941 }
2942 }
2943
2944 adev->dev.dma_parms = &pl330->dma_parms;
2945
2946
2947
2948
2949
2950 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2951 if (ret)
2952 dev_err(&adev->dev, "unable to set the seg size\n");
2953
2954
2955 dev_info(&adev->dev,
2956 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
2957 dev_info(&adev->dev,
2958 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2959 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2960 pcfg->num_peri, pcfg->num_events);
2961
2962 pm_runtime_irq_safe(&adev->dev);
2963 pm_runtime_use_autosuspend(&adev->dev);
2964 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2965 pm_runtime_mark_last_busy(&adev->dev);
2966 pm_runtime_put_autosuspend(&adev->dev);
2967
2968 return 0;
2969probe_err3:
2970
2971 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2972 chan.device_node) {
2973
2974
2975 list_del(&pch->chan.device_node);
2976
2977
2978 if (pch->thread) {
2979 pl330_terminate_all(&pch->chan);
2980 pl330_free_chan_resources(&pch->chan);
2981 }
2982 }
2983probe_err2:
2984 pl330_del(pl330);
2985
2986 return ret;
2987}
2988
2989static int pl330_remove(struct amba_device *adev)
2990{
2991 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
2992 struct dma_pl330_chan *pch, *_p;
2993 int i, irq;
2994
2995 pm_runtime_get_noresume(pl330->ddma.dev);
2996
2997 if (adev->dev.of_node)
2998 of_dma_controller_free(adev->dev.of_node);
2999
3000 for (i = 0; i < AMBA_NR_IRQS; i++) {
3001 irq = adev->irq[i];
3002 if (irq)
3003 devm_free_irq(&adev->dev, irq, pl330);
3004 }
3005
3006 dma_async_device_unregister(&pl330->ddma);
3007
3008
3009 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3010 chan.device_node) {
3011
3012
3013 list_del(&pch->chan.device_node);
3014
3015
3016 if (pch->thread) {
3017 pl330_terminate_all(&pch->chan);
3018 pl330_free_chan_resources(&pch->chan);
3019 }
3020 }
3021
3022 pl330_del(pl330);
3023
3024 return 0;
3025}
3026
3027static const struct amba_id pl330_ids[] = {
3028 {
3029 .id = 0x00041330,
3030 .mask = 0x000fffff,
3031 },
3032 { 0, 0 },
3033};
3034
3035MODULE_DEVICE_TABLE(amba, pl330_ids);
3036
3037static struct amba_driver pl330_driver = {
3038 .drv = {
3039 .owner = THIS_MODULE,
3040 .name = "dma-pl330",
3041 .pm = &pl330_pm,
3042 },
3043 .id_table = pl330_ids,
3044 .probe = pl330_probe,
3045 .remove = pl330_remove,
3046};
3047
3048module_amba_driver(pl330_driver);
3049
3050MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3051MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3052MODULE_LICENSE("GPL");
3053