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23#include "amdgpu.h"
24#include "mmhub_v1_0.h"
25
26#include "mmhub/mmhub_1_0_offset.h"
27#include "mmhub/mmhub_1_0_sh_mask.h"
28#include "mmhub/mmhub_1_0_default.h"
29#include "athub/athub_1_0_offset.h"
30#include "athub/athub_1_0_sh_mask.h"
31#include "vega10_enum.h"
32
33#include "soc15_common.h"
34
35#define mmDAGB0_CNTL_MISC2_RV 0x008f
36#define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
37
38u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
39{
40 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
41
42 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
43 base <<= 24;
44
45 return base;
46}
47
48static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
49{
50 uint64_t value;
51
52 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
53 value = adev->gart.table_addr - adev->mc.vram_start +
54 adev->vm_manager.vram_base_offset;
55 value &= 0x0000FFFFFFFFF000ULL;
56 value |= 0x1;
57
58 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
59 lower_32_bits(value));
60
61 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
62 upper_32_bits(value));
63}
64
65static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
66{
67 mmhub_v1_0_init_gart_pt_regs(adev);
68
69 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
70 (u32)(adev->mc.gart_start >> 12));
71 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
72 (u32)(adev->mc.gart_start >> 44));
73
74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
75 (u32)(adev->mc.gart_end >> 12));
76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
77 (u32)(adev->mc.gart_end >> 44));
78}
79
80static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
81{
82 uint64_t value;
83 uint32_t tmp;
84
85
86 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
87 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
88 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF);
89
90
91 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
92 adev->mc.vram_start >> 18);
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
94 adev->mc.vram_end >> 18);
95
96
97 value = adev->vram_scratch.gpu_addr - adev->mc.vram_start +
98 adev->vm_manager.vram_base_offset;
99 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
100 (u32)(value >> 12));
101 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
102 (u32)(value >> 44));
103
104
105 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
106 (u32)(adev->dummy_page.addr >> 12));
107 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
108 (u32)((u64)adev->dummy_page.addr >> 44));
109
110 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
111 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
112 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
113 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
114}
115
116static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
117{
118 uint32_t tmp;
119
120
121 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
122
123 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
124 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
125 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
126 ENABLE_ADVANCED_DRIVER_MODEL, 1);
127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
128 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
129 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
130 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
131 MTYPE, MTYPE_UC);
132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
133
134 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
135}
136
137static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
138{
139 uint32_t tmp;
140
141
142 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
143 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
144 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
145
146 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
147 0);
148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
149 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
150 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
151 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
152
153 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
154 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
155 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
156 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
157
158 if (adev->mc.translate_further) {
159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
160 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
161 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
162 } else {
163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
164 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
165 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
166 }
167
168 tmp = mmVM_L2_CNTL4_DEFAULT;
169 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
171 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
172}
173
174static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
175{
176 uint32_t tmp;
177
178 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
179 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
180 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
181 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
182}
183
184static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
185{
186 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
187 0XFFFFFFFF);
188 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
189 0x0000000F);
190
191 WREG32_SOC15(MMHUB, 0,
192 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
193 WREG32_SOC15(MMHUB, 0,
194 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
195
196 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
197 0);
198 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
199 0);
200}
201
202static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
203{
204 unsigned num_level, block_size;
205 uint32_t tmp;
206 int i;
207
208 num_level = adev->vm_manager.num_level;
209 block_size = adev->vm_manager.block_size;
210 if (adev->mc.translate_further)
211 num_level -= 1;
212 else
213 block_size -= 9;
214
215 for (i = 0; i <= 14; i++) {
216 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
217 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
218 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
219 num_level);
220 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
221 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
222 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
223 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
224 1);
225 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
226 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
227 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
228 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
229 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
230 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
231 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
232 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
233 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
234 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
235 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
236 PAGE_TABLE_BLOCK_SIZE,
237 block_size);
238
239 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
240 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
241 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
242 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
243 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
244 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
245 lower_32_bits(adev->vm_manager.max_pfn - 1));
246 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
247 upper_32_bits(adev->vm_manager.max_pfn - 1));
248 }
249}
250
251static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
252{
253 unsigned i;
254
255 for (i = 0; i < 18; ++i) {
256 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
257 2 * i, 0xffffffff);
258 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
259 2 * i, 0x1f);
260 }
261}
262
263struct pctl_data {
264 uint32_t index;
265 uint32_t data;
266};
267
268static const struct pctl_data pctl0_data[] = {
269 {0x0, 0x7a640},
270 {0x9, 0x2a64a},
271 {0xd, 0x2a680},
272 {0x11, 0x6a684},
273 {0x19, 0xea68e},
274 {0x29, 0xa69e},
275 {0x2b, 0x34a6c0},
276 {0x61, 0x83a707},
277 {0xe6, 0x8a7a4},
278 {0xf0, 0x1a7b8},
279 {0xf3, 0xfa7cc},
280 {0x104, 0x17a7dd},
281 {0x11d, 0xa7dc},
282 {0x11f, 0x12a7f5},
283 {0x133, 0xa808},
284 {0x135, 0x12a810},
285 {0x149, 0x7a82c}
286};
287#define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data))
288
289#define PCTL0_RENG_EXEC_END_PTR 0x151
290#define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640
291#define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
292
293static const struct pctl_data pctl1_data[] = {
294 {0x0, 0x39a000},
295 {0x3b, 0x44a040},
296 {0x81, 0x2a08d},
297 {0x85, 0x6ba094},
298 {0xf2, 0x18a100},
299 {0x10c, 0x4a132},
300 {0x112, 0xca141},
301 {0x120, 0x2fa158},
302 {0x151, 0x17a1d0},
303 {0x16a, 0x1a1e9},
304 {0x16d, 0x13a1ec},
305 {0x182, 0x7a201},
306 {0x18b, 0x3a20a},
307 {0x190, 0x7a580},
308 {0x199, 0xa590},
309 {0x19b, 0x4a594},
310 {0x1a1, 0x1a59c},
311 {0x1a4, 0x7a82c},
312 {0x1ad, 0xfa7cc},
313 {0x1be, 0x17a7dd},
314 {0x1d7, 0x12a810},
315 {0x1eb, 0x4000a7e1},
316 {0x1ec, 0x5000a7f5},
317 {0x1ed, 0x4000a7e2},
318 {0x1ee, 0x5000a7dc},
319 {0x1ef, 0x4000a7e3},
320 {0x1f0, 0x5000a7f6},
321 {0x1f1, 0x5000a7e4}
322};
323#define PCTL1_DATA_LEN (ARRAY_SIZE(pctl1_data))
324
325#define PCTL1_RENG_EXEC_END_PTR 0x1f1
326#define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000
327#define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d
328#define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE 0xa580
329#define PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT 0xa59d
330#define PCTL1_STCTRL_REG_SAVE_RANGE2_BASE 0xa82c
331#define PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT 0xa833
332
333static void mmhub_v1_0_power_gating_write_save_ranges(struct amdgpu_device *adev)
334{
335 uint32_t tmp = 0;
336
337
338 tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
339 STCTRL_REGISTER_SAVE_BASE,
340 PCTL0_STCTRL_REG_SAVE_RANGE0_BASE);
341 tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
342 STCTRL_REGISTER_SAVE_LIMIT,
343 PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT);
344 WREG32_SOC15(MMHUB, 0, mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0, tmp);
345
346
347 tmp = 0;
348 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
349 STCTRL_REGISTER_SAVE_BASE,
350 PCTL1_STCTRL_REG_SAVE_RANGE0_BASE);
351 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
352 STCTRL_REGISTER_SAVE_LIMIT,
353 PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT);
354 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0, tmp);
355
356
357 tmp = 0;
358 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
359 STCTRL_REGISTER_SAVE_BASE,
360 PCTL1_STCTRL_REG_SAVE_RANGE1_BASE);
361 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
362 STCTRL_REGISTER_SAVE_LIMIT,
363 PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT);
364 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1, tmp);
365
366
367 tmp = 0;
368 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2,
369 STCTRL_REGISTER_SAVE_BASE,
370 PCTL1_STCTRL_REG_SAVE_RANGE2_BASE);
371 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2,
372 STCTRL_REGISTER_SAVE_LIMIT,
373 PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT);
374 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2, tmp);
375}
376
377void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev)
378{
379 uint32_t pctl0_misc = 0;
380 uint32_t pctl0_reng_execute = 0;
381 uint32_t pctl1_misc = 0;
382 uint32_t pctl1_reng_execute = 0;
383 int i = 0;
384
385 if (amdgpu_sriov_vf(adev))
386 return;
387
388 pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC);
389 pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
390 pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC);
391 pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
392
393
394 pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
395 WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
396
397
398 for (i = 0; i < PCTL0_DATA_LEN; i++) {
399 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_INDEX,
400 pctl0_data[i].index);
401 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_DATA,
402 pctl0_data[i].data);
403 }
404
405
406 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
407 PCTL0_RENG_EXECUTE,
408 RENG_EXECUTE_END_PTR,
409 PCTL0_RENG_EXEC_END_PTR);
410 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
411
412
413 pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
414 WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
415
416
417 for (i = 0; i < PCTL1_DATA_LEN; i++) {
418 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_INDEX,
419 pctl1_data[i].index);
420 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_DATA,
421 pctl1_data[i].data);
422 }
423
424
425 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
426 PCTL1_RENG_EXECUTE,
427 RENG_EXECUTE_END_PTR,
428 PCTL1_RENG_EXEC_END_PTR);
429 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
430
431 mmhub_v1_0_power_gating_write_save_ranges(adev);
432
433
434 pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
435 WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
436 pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
437 WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
438}
439
440void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
441 bool enable)
442{
443 uint32_t pctl0_reng_execute = 0;
444 uint32_t pctl1_reng_execute = 0;
445
446 if (amdgpu_sriov_vf(adev))
447 return;
448
449 pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
450 pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
451
452 if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
453 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
454 PCTL0_RENG_EXECUTE,
455 RENG_EXECUTE_ON_PWR_UP, 1);
456 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
457 PCTL0_RENG_EXECUTE,
458 RENG_EXECUTE_ON_REG_UPDATE, 1);
459 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
460
461 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
462 PCTL1_RENG_EXECUTE,
463 RENG_EXECUTE_ON_PWR_UP, 1);
464 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
465 PCTL1_RENG_EXECUTE,
466 RENG_EXECUTE_ON_REG_UPDATE, 1);
467 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
468
469 } else {
470 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
471 PCTL0_RENG_EXECUTE,
472 RENG_EXECUTE_ON_PWR_UP, 0);
473 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
474 PCTL0_RENG_EXECUTE,
475 RENG_EXECUTE_ON_REG_UPDATE, 0);
476 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
477
478 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
479 PCTL1_RENG_EXECUTE,
480 RENG_EXECUTE_ON_PWR_UP, 0);
481 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
482 PCTL1_RENG_EXECUTE,
483 RENG_EXECUTE_ON_REG_UPDATE, 0);
484 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
485 }
486}
487
488int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
489{
490 if (amdgpu_sriov_vf(adev)) {
491
492
493
494
495
496 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,
497 adev->mc.vram_start >> 24);
498 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,
499 adev->mc.vram_end >> 24);
500 }
501
502
503 mmhub_v1_0_init_gart_aperture_regs(adev);
504 mmhub_v1_0_init_system_aperture_regs(adev);
505 mmhub_v1_0_init_tlb_regs(adev);
506 mmhub_v1_0_init_cache_regs(adev);
507
508 mmhub_v1_0_enable_system_domain(adev);
509 mmhub_v1_0_disable_identity_aperture(adev);
510 mmhub_v1_0_setup_vmid_config(adev);
511 mmhub_v1_0_program_invalidation(adev);
512
513 return 0;
514}
515
516void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
517{
518 u32 tmp;
519 u32 i;
520
521
522 for (i = 0; i < 16; i++)
523 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
524
525
526 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
527 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
528 tmp = REG_SET_FIELD(tmp,
529 MC_VM_MX_L1_TLB_CNTL,
530 ENABLE_ADVANCED_DRIVER_MODEL,
531 0);
532 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
533
534
535 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
536 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
537 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
538 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);
539}
540
541
542
543
544
545
546
547void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
548{
549 u32 tmp;
550 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
551 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
552 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
553 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
554 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
555 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
556 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
557 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
558 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
559 tmp = REG_SET_FIELD(tmp,
560 VM_L2_PROTECTION_FAULT_CNTL,
561 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
562 value);
563 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
564 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
565 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
566 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
567 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
568 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
569 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
570 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
571 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
572 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
573 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
574 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
575 if (!value) {
576 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
577 CRASH_ON_NO_RETRY_FAULT, 1);
578 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
579 CRASH_ON_RETRY_FAULT, 1);
580 }
581
582 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
583}
584
585void mmhub_v1_0_init(struct amdgpu_device *adev)
586{
587 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
588
589 hub->ctx0_ptb_addr_lo32 =
590 SOC15_REG_OFFSET(MMHUB, 0,
591 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
592 hub->ctx0_ptb_addr_hi32 =
593 SOC15_REG_OFFSET(MMHUB, 0,
594 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
595 hub->vm_inv_eng0_req =
596 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
597 hub->vm_inv_eng0_ack =
598 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
599 hub->vm_context0_cntl =
600 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
601 hub->vm_l2_pro_fault_status =
602 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
603 hub->vm_l2_pro_fault_cntl =
604 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
605
606}
607
608static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
609 bool enable)
610{
611 uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
612
613 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
614
615 if (adev->asic_type != CHIP_RAVEN) {
616 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
617 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
618 } else
619 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);
620
621 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
622 data |= ATC_L2_MISC_CG__ENABLE_MASK;
623
624 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
625 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
626 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
627 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
628 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
629 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
630
631 if (adev->asic_type != CHIP_RAVEN)
632 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
633 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
634 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
635 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
636 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
637 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
638 } else {
639 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
640
641 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
642 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
643 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
644 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
645 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
646 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
647
648 if (adev->asic_type != CHIP_RAVEN)
649 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
650 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
651 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
652 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
653 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
654 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
655 }
656
657 if (def != data)
658 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
659
660 if (def1 != data1) {
661 if (adev->asic_type != CHIP_RAVEN)
662 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
663 else
664 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
665 }
666
667 if (adev->asic_type != CHIP_RAVEN && def2 != data2)
668 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
669}
670
671static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
672 bool enable)
673{
674 uint32_t def, data;
675
676 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
677
678 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
679 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
680 else
681 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
682
683 if (def != data)
684 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
685}
686
687static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
688 bool enable)
689{
690 uint32_t def, data;
691
692 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
693
694 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
695 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
696 else
697 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
698
699 if (def != data)
700 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
701}
702
703static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
704 bool enable)
705{
706 uint32_t def, data;
707
708 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
709
710 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
711 (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
712 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
713 else
714 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
715
716 if(def != data)
717 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
718}
719
720int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
721 enum amd_clockgating_state state)
722{
723 if (amdgpu_sriov_vf(adev))
724 return 0;
725
726 switch (adev->asic_type) {
727 case CHIP_VEGA10:
728 case CHIP_RAVEN:
729 mmhub_v1_0_update_medium_grain_clock_gating(adev,
730 state == AMD_CG_STATE_GATE ? true : false);
731 athub_update_medium_grain_clock_gating(adev,
732 state == AMD_CG_STATE_GATE ? true : false);
733 mmhub_v1_0_update_medium_grain_light_sleep(adev,
734 state == AMD_CG_STATE_GATE ? true : false);
735 athub_update_medium_grain_light_sleep(adev,
736 state == AMD_CG_STATE_GATE ? true : false);
737 break;
738 default:
739 break;
740 }
741
742 return 0;
743}
744
745void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
746{
747 int data;
748
749 if (amdgpu_sriov_vf(adev))
750 *flags = 0;
751
752
753 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
754 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
755 *flags |= AMD_CG_SUPPORT_MC_MGCG;
756
757
758 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
759 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
760 *flags |= AMD_CG_SUPPORT_MC_LS;
761}
762
