1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include <linux/firmware.h>
27#include "amdgpu.h"
28#include "amdgpu_psp.h"
29#include "amdgpu_ucode.h"
30#include "soc15_common.h"
31#include "psp_v10_0.h"
32
33#include "mp/mp_10_0_offset.h"
34#include "gc/gc_9_1_offset.h"
35#include "sdma0/sdma0_4_1_offset.h"
36
37MODULE_FIRMWARE("amdgpu/raven_asd.bin");
38
39static int
40psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
41{
42 switch(ucode->ucode_id) {
43 case AMDGPU_UCODE_ID_SDMA0:
44 *type = GFX_FW_TYPE_SDMA0;
45 break;
46 case AMDGPU_UCODE_ID_SDMA1:
47 *type = GFX_FW_TYPE_SDMA1;
48 break;
49 case AMDGPU_UCODE_ID_CP_CE:
50 *type = GFX_FW_TYPE_CP_CE;
51 break;
52 case AMDGPU_UCODE_ID_CP_PFP:
53 *type = GFX_FW_TYPE_CP_PFP;
54 break;
55 case AMDGPU_UCODE_ID_CP_ME:
56 *type = GFX_FW_TYPE_CP_ME;
57 break;
58 case AMDGPU_UCODE_ID_CP_MEC1:
59 *type = GFX_FW_TYPE_CP_MEC;
60 break;
61 case AMDGPU_UCODE_ID_CP_MEC1_JT:
62 *type = GFX_FW_TYPE_CP_MEC_ME1;
63 break;
64 case AMDGPU_UCODE_ID_CP_MEC2:
65 *type = GFX_FW_TYPE_CP_MEC;
66 break;
67 case AMDGPU_UCODE_ID_CP_MEC2_JT:
68 *type = GFX_FW_TYPE_CP_MEC_ME2;
69 break;
70 case AMDGPU_UCODE_ID_RLC_G:
71 *type = GFX_FW_TYPE_RLC_G;
72 break;
73 case AMDGPU_UCODE_ID_SMC:
74 *type = GFX_FW_TYPE_SMU;
75 break;
76 case AMDGPU_UCODE_ID_UVD:
77 *type = GFX_FW_TYPE_UVD;
78 break;
79 case AMDGPU_UCODE_ID_VCE:
80 *type = GFX_FW_TYPE_VCE;
81 break;
82 case AMDGPU_UCODE_ID_MAXIMUM:
83 default:
84 return -EINVAL;
85 }
86
87 return 0;
88}
89
90int psp_v10_0_init_microcode(struct psp_context *psp)
91{
92 struct amdgpu_device *adev = psp->adev;
93 const char *chip_name;
94 char fw_name[30];
95 int err = 0;
96 const struct psp_firmware_header_v1_0 *hdr;
97
98 DRM_DEBUG("\n");
99
100 switch (adev->asic_type) {
101 case CHIP_RAVEN:
102 chip_name = "raven";
103 break;
104 default: BUG();
105 }
106
107 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
108 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
109 if (err)
110 goto out;
111
112 err = amdgpu_ucode_validate(adev->psp.asd_fw);
113 if (err)
114 goto out;
115
116 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
117 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
118 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
119 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
120 adev->psp.asd_start_addr = (uint8_t *)hdr +
121 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
122
123 return 0;
124out:
125 if (err) {
126 dev_err(adev->dev,
127 "psp v10.0: Failed to load firmware \"%s\"\n",
128 fw_name);
129 release_firmware(adev->psp.asd_fw);
130 adev->psp.asd_fw = NULL;
131 }
132
133 return err;
134}
135
136int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
137{
138 int ret;
139 uint64_t fw_mem_mc_addr = ucode->mc_addr;
140
141 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
142
143 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
144 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
145 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
146 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
147
148 ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
149 if (ret)
150 DRM_ERROR("Unknown firmware type\n");
151
152 return ret;
153}
154
155int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
156{
157 int ret = 0;
158 struct psp_ring *ring;
159 struct amdgpu_device *adev = psp->adev;
160
161 ring = &psp->km_ring;
162
163 ring->ring_type = ring_type;
164
165
166 ring->ring_size = 0x1000;
167 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
168 AMDGPU_GEM_DOMAIN_VRAM,
169 &adev->firmware.rbuf,
170 &ring->ring_mem_mc_addr,
171 (void **)&ring->ring_mem);
172 if (ret) {
173 ring->ring_size = 0;
174 return ret;
175 }
176
177 return 0;
178}
179
180int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
181{
182 int ret = 0;
183 unsigned int psp_ring_reg = 0;
184 struct psp_ring *ring = &psp->km_ring;
185 struct amdgpu_device *adev = psp->adev;
186
187
188 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
189 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
190
191 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
192 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
193
194 psp_ring_reg = ring->ring_size;
195 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
196
197 psp_ring_reg = ring_type;
198 psp_ring_reg = psp_ring_reg << 16;
199 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
200
201
202 mdelay(20);
203
204
205 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
206 0x80000000, 0x8000FFFF, false);
207
208 return ret;
209}
210
211int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
212{
213 int ret = 0;
214 struct psp_ring *ring;
215 unsigned int psp_ring_reg = 0;
216 struct amdgpu_device *adev = psp->adev;
217
218 ring = &psp->km_ring;
219
220
221 psp_ring_reg = 3 << 16;
222 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
223
224
225 mdelay(20);
226
227
228 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
229 0x80000000, 0x80000000, false);
230
231 return ret;
232}
233
234int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
235{
236 int ret = 0;
237 struct psp_ring *ring = &psp->km_ring;
238 struct amdgpu_device *adev = psp->adev;
239
240 ret = psp_v10_0_ring_stop(psp, ring_type);
241 if (ret)
242 DRM_ERROR("Fail to stop psp ring\n");
243
244 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
245 &ring->ring_mem_mc_addr,
246 (void **)&ring->ring_mem);
247
248 return ret;
249}
250
251int psp_v10_0_cmd_submit(struct psp_context *psp,
252 struct amdgpu_firmware_info *ucode,
253 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
254 int index)
255{
256 unsigned int psp_write_ptr_reg = 0;
257 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
258 struct psp_ring *ring = &psp->km_ring;
259 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
260 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
261 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
262 struct amdgpu_device *adev = psp->adev;
263 uint32_t ring_size_dw = ring->ring_size / 4;
264 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
265
266
267 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
268
269
270 if ((psp_write_ptr_reg % ring_size_dw) == 0)
271 write_frame = ring_buffer_start;
272 else
273 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
274
275 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
276 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
277 ring_buffer_start, ring_buffer_end, write_frame);
278 DRM_ERROR("write_frame is pointing to address out of bounds\n");
279 return -EINVAL;
280 }
281
282
283 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
284
285
286 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
287 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
288 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
289 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
290 write_frame->fence_value = index;
291
292
293 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
294 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
295
296 return 0;
297}
298
299static int
300psp_v10_0_sram_map(struct amdgpu_device *adev,
301 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
302 unsigned int *sram_data_reg_offset,
303 enum AMDGPU_UCODE_ID ucode_id)
304{
305 int ret = 0;
306
307 switch(ucode_id) {
308
309#if 0
310 case AMDGPU_UCODE_ID_SMC:
311 *sram_offset = 0;
312 *sram_addr_reg_offset = 0;
313 *sram_data_reg_offset = 0;
314 break;
315#endif
316
317 case AMDGPU_UCODE_ID_CP_CE:
318 *sram_offset = 0x0;
319 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
320 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
321 break;
322
323 case AMDGPU_UCODE_ID_CP_PFP:
324 *sram_offset = 0x0;
325 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
326 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
327 break;
328
329 case AMDGPU_UCODE_ID_CP_ME:
330 *sram_offset = 0x0;
331 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
332 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
333 break;
334
335 case AMDGPU_UCODE_ID_CP_MEC1:
336 *sram_offset = 0x10000;
337 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
338 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
339 break;
340
341 case AMDGPU_UCODE_ID_CP_MEC2:
342 *sram_offset = 0x10000;
343 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
344 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
345 break;
346
347 case AMDGPU_UCODE_ID_RLC_G:
348 *sram_offset = 0x2000;
349 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
350 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
351 break;
352
353 case AMDGPU_UCODE_ID_SDMA0:
354 *sram_offset = 0x0;
355 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
356 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
357 break;
358
359
360#if 0
361 case AMDGPU_UCODE_ID_SDMA1:
362 *sram_offset = ;
363 *sram_addr_reg_offset = ;
364 break;
365
366 case AMDGPU_UCODE_ID_UVD:
367 *sram_offset = ;
368 *sram_addr_reg_offset = ;
369 break;
370
371 case AMDGPU_UCODE_ID_VCE:
372 *sram_offset = ;
373 *sram_addr_reg_offset = ;
374 break;
375#endif
376
377 case AMDGPU_UCODE_ID_MAXIMUM:
378 default:
379 ret = -EINVAL;
380 break;
381 }
382
383 return ret;
384}
385
386bool psp_v10_0_compare_sram_data(struct psp_context *psp,
387 struct amdgpu_firmware_info *ucode,
388 enum AMDGPU_UCODE_ID ucode_type)
389{
390 int err = 0;
391 unsigned int fw_sram_reg_val = 0;
392 unsigned int fw_sram_addr_reg_offset = 0;
393 unsigned int fw_sram_data_reg_offset = 0;
394 unsigned int ucode_size;
395 uint32_t *ucode_mem = NULL;
396 struct amdgpu_device *adev = psp->adev;
397
398 err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
399 &fw_sram_data_reg_offset, ucode_type);
400 if (err)
401 return false;
402
403 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
404
405 ucode_size = ucode->ucode_size;
406 ucode_mem = (uint32_t *)ucode->kaddr;
407 while (!ucode_size) {
408 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
409
410 if (*ucode_mem != fw_sram_reg_val)
411 return false;
412
413 ucode_mem++;
414
415 ucode_size -= 4;
416 }
417
418 return true;
419}
420
421
422int psp_v10_0_mode1_reset(struct psp_context *psp)
423{
424 DRM_INFO("psp mode 1 reset not supported now! \n");
425 return -EINVAL;
426}
427
