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26#include <linux/firmware.h>
27#include <drm/drmP.h>
28#include "amdgpu.h"
29#include "amdgpu_psp.h"
30#include "amdgpu_ucode.h"
31#include "soc15_common.h"
32#include "psp_v3_1.h"
33
34#include "mp/mp_9_0_offset.h"
35#include "mp/mp_9_0_sh_mask.h"
36#include "gc/gc_9_0_offset.h"
37#include "sdma0/sdma0_4_0_offset.h"
38#include "nbio/nbio_6_1_offset.h"
39
40MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
41MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
42
43#define smnMP1_FIRMWARE_FLAGS 0x3010028
44
45static int
46psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
47{
48 switch(ucode->ucode_id) {
49 case AMDGPU_UCODE_ID_SDMA0:
50 *type = GFX_FW_TYPE_SDMA0;
51 break;
52 case AMDGPU_UCODE_ID_SDMA1:
53 *type = GFX_FW_TYPE_SDMA1;
54 break;
55 case AMDGPU_UCODE_ID_CP_CE:
56 *type = GFX_FW_TYPE_CP_CE;
57 break;
58 case AMDGPU_UCODE_ID_CP_PFP:
59 *type = GFX_FW_TYPE_CP_PFP;
60 break;
61 case AMDGPU_UCODE_ID_CP_ME:
62 *type = GFX_FW_TYPE_CP_ME;
63 break;
64 case AMDGPU_UCODE_ID_CP_MEC1:
65 *type = GFX_FW_TYPE_CP_MEC;
66 break;
67 case AMDGPU_UCODE_ID_CP_MEC1_JT:
68 *type = GFX_FW_TYPE_CP_MEC_ME1;
69 break;
70 case AMDGPU_UCODE_ID_CP_MEC2:
71 *type = GFX_FW_TYPE_CP_MEC;
72 break;
73 case AMDGPU_UCODE_ID_CP_MEC2_JT:
74 *type = GFX_FW_TYPE_CP_MEC_ME2;
75 break;
76 case AMDGPU_UCODE_ID_RLC_G:
77 *type = GFX_FW_TYPE_RLC_G;
78 break;
79 case AMDGPU_UCODE_ID_SMC:
80 *type = GFX_FW_TYPE_SMU;
81 break;
82 case AMDGPU_UCODE_ID_UVD:
83 *type = GFX_FW_TYPE_UVD;
84 break;
85 case AMDGPU_UCODE_ID_VCE:
86 *type = GFX_FW_TYPE_VCE;
87 break;
88 case AMDGPU_UCODE_ID_MAXIMUM:
89 default:
90 return -EINVAL;
91 }
92
93 return 0;
94}
95
96int psp_v3_1_init_microcode(struct psp_context *psp)
97{
98 struct amdgpu_device *adev = psp->adev;
99 const char *chip_name;
100 char fw_name[30];
101 int err = 0;
102 const struct psp_firmware_header_v1_0 *hdr;
103
104 DRM_DEBUG("\n");
105
106 switch (adev->asic_type) {
107 case CHIP_VEGA10:
108 chip_name = "vega10";
109 break;
110 default: BUG();
111 }
112
113 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
114 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
115 if (err)
116 goto out;
117
118 err = amdgpu_ucode_validate(adev->psp.sos_fw);
119 if (err)
120 goto out;
121
122 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
123 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version);
124 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version);
125 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes);
126 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) -
127 le32_to_cpu(hdr->sos_size_bytes);
128 adev->psp.sys_start_addr = (uint8_t *)hdr +
129 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
130 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
131 le32_to_cpu(hdr->sos_offset_bytes);
132
133 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
134 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
135 if (err)
136 goto out;
137
138 err = amdgpu_ucode_validate(adev->psp.asd_fw);
139 if (err)
140 goto out;
141
142 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
143 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
144 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
145 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
146 adev->psp.asd_start_addr = (uint8_t *)hdr +
147 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
148
149 return 0;
150out:
151 if (err) {
152 dev_err(adev->dev,
153 "psp v3.1: Failed to load firmware \"%s\"\n",
154 fw_name);
155 release_firmware(adev->psp.sos_fw);
156 adev->psp.sos_fw = NULL;
157 release_firmware(adev->psp.asd_fw);
158 adev->psp.asd_fw = NULL;
159 }
160
161 return err;
162}
163
164int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
165{
166 int ret;
167 uint32_t psp_gfxdrv_command_reg = 0;
168 struct amdgpu_device *adev = psp->adev;
169 uint32_t sol_reg;
170
171
172
173
174 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
175 if (sol_reg)
176 return 0;
177
178
179 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
180 0x80000000, 0x80000000, false);
181 if (ret)
182 return ret;
183
184 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
185
186
187 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
188
189
190 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
191 (uint32_t)(psp->fw_pri_mc_addr >> 20));
192 psp_gfxdrv_command_reg = 1 << 16;
193 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
194 psp_gfxdrv_command_reg);
195
196
197 mdelay(20);
198
199 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
200 0x80000000, 0x80000000, false);
201
202 return ret;
203}
204
205int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
206{
207 int ret;
208 unsigned int psp_gfxdrv_command_reg = 0;
209 struct amdgpu_device *adev = psp->adev;
210 uint32_t sol_reg;
211
212
213
214
215 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
216 if (sol_reg)
217 return 0;
218
219
220 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
221 0x80000000, 0x80000000, false);
222 if (ret)
223 return ret;
224
225 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
226
227
228 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
229
230
231 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
232 (uint32_t)(psp->fw_pri_mc_addr >> 20));
233 psp_gfxdrv_command_reg = 2 << 16;
234 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
235 psp_gfxdrv_command_reg);
236
237
238 mdelay(20);
239 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
240 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
241 0, true);
242
243 return ret;
244}
245
246int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
247{
248 int ret;
249 uint64_t fw_mem_mc_addr = ucode->mc_addr;
250
251 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
252
253 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
254 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
255 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
256 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
257
258 ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
259 if (ret)
260 DRM_ERROR("Unknown firmware type\n");
261
262 return ret;
263}
264
265int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
266{
267 int ret = 0;
268 struct psp_ring *ring;
269 struct amdgpu_device *adev = psp->adev;
270
271 ring = &psp->km_ring;
272
273 ring->ring_type = ring_type;
274
275
276 ring->ring_size = 0x1000;
277 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
278 AMDGPU_GEM_DOMAIN_VRAM,
279 &adev->firmware.rbuf,
280 &ring->ring_mem_mc_addr,
281 (void **)&ring->ring_mem);
282 if (ret) {
283 ring->ring_size = 0;
284 return ret;
285 }
286
287 return 0;
288}
289
290int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
291{
292 int ret = 0;
293 unsigned int psp_ring_reg = 0;
294 struct psp_ring *ring = &psp->km_ring;
295 struct amdgpu_device *adev = psp->adev;
296
297
298 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
299 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
300
301 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
302 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
303
304 psp_ring_reg = ring->ring_size;
305 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
306
307 psp_ring_reg = ring_type;
308 psp_ring_reg = psp_ring_reg << 16;
309 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
310
311
312 mdelay(20);
313
314
315 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
316 0x80000000, 0x8000FFFF, false);
317
318 return ret;
319}
320
321int psp_v3_1_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
322{
323 int ret = 0;
324 struct psp_ring *ring;
325 unsigned int psp_ring_reg = 0;
326 struct amdgpu_device *adev = psp->adev;
327
328 ring = &psp->km_ring;
329
330
331 psp_ring_reg = 3 << 16;
332 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
333
334
335 mdelay(20);
336
337
338 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
339 0x80000000, 0x80000000, false);
340
341 return ret;
342}
343
344int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
345{
346 int ret = 0;
347 struct psp_ring *ring = &psp->km_ring;
348 struct amdgpu_device *adev = psp->adev;
349
350 ret = psp_v3_1_ring_stop(psp, ring_type);
351 if (ret)
352 DRM_ERROR("Fail to stop psp ring\n");
353
354 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
355 &ring->ring_mem_mc_addr,
356 (void **)&ring->ring_mem);
357
358 return ret;
359}
360
361int psp_v3_1_cmd_submit(struct psp_context *psp,
362 struct amdgpu_firmware_info *ucode,
363 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
364 int index)
365{
366 unsigned int psp_write_ptr_reg = 0;
367 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
368 struct psp_ring *ring = &psp->km_ring;
369 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
370 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
371 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
372 struct amdgpu_device *adev = psp->adev;
373 uint32_t ring_size_dw = ring->ring_size / 4;
374 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
375
376
377 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
378
379
380
381
382 if ((psp_write_ptr_reg % ring_size_dw) == 0)
383 write_frame = ring_buffer_start;
384 else
385 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
386
387 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
388 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
389 ring_buffer_start, ring_buffer_end, write_frame);
390 DRM_ERROR("write_frame is pointing to address out of bounds\n");
391 return -EINVAL;
392 }
393
394
395 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
396
397
398 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
399 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
400 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
401 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
402 write_frame->fence_value = index;
403
404
405 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
406 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
407
408 return 0;
409}
410
411static int
412psp_v3_1_sram_map(struct amdgpu_device *adev,
413 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
414 unsigned int *sram_data_reg_offset,
415 enum AMDGPU_UCODE_ID ucode_id)
416{
417 int ret = 0;
418
419 switch(ucode_id) {
420
421#if 0
422 case AMDGPU_UCODE_ID_SMC:
423 *sram_offset = 0;
424 *sram_addr_reg_offset = 0;
425 *sram_data_reg_offset = 0;
426 break;
427#endif
428
429 case AMDGPU_UCODE_ID_CP_CE:
430 *sram_offset = 0x0;
431 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
432 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
433 break;
434
435 case AMDGPU_UCODE_ID_CP_PFP:
436 *sram_offset = 0x0;
437 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
438 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
439 break;
440
441 case AMDGPU_UCODE_ID_CP_ME:
442 *sram_offset = 0x0;
443 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
444 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
445 break;
446
447 case AMDGPU_UCODE_ID_CP_MEC1:
448 *sram_offset = 0x10000;
449 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
450 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
451 break;
452
453 case AMDGPU_UCODE_ID_CP_MEC2:
454 *sram_offset = 0x10000;
455 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
456 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
457 break;
458
459 case AMDGPU_UCODE_ID_RLC_G:
460 *sram_offset = 0x2000;
461 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
462 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
463 break;
464
465 case AMDGPU_UCODE_ID_SDMA0:
466 *sram_offset = 0x0;
467 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
468 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
469 break;
470
471
472#if 0
473 case AMDGPU_UCODE_ID_SDMA1:
474 *sram_offset = ;
475 *sram_addr_reg_offset = ;
476 break;
477
478 case AMDGPU_UCODE_ID_UVD:
479 *sram_offset = ;
480 *sram_addr_reg_offset = ;
481 break;
482
483 case AMDGPU_UCODE_ID_VCE:
484 *sram_offset = ;
485 *sram_addr_reg_offset = ;
486 break;
487#endif
488
489 case AMDGPU_UCODE_ID_MAXIMUM:
490 default:
491 ret = -EINVAL;
492 break;
493 }
494
495 return ret;
496}
497
498bool psp_v3_1_compare_sram_data(struct psp_context *psp,
499 struct amdgpu_firmware_info *ucode,
500 enum AMDGPU_UCODE_ID ucode_type)
501{
502 int err = 0;
503 unsigned int fw_sram_reg_val = 0;
504 unsigned int fw_sram_addr_reg_offset = 0;
505 unsigned int fw_sram_data_reg_offset = 0;
506 unsigned int ucode_size;
507 uint32_t *ucode_mem = NULL;
508 struct amdgpu_device *adev = psp->adev;
509
510 err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
511 &fw_sram_data_reg_offset, ucode_type);
512 if (err)
513 return false;
514
515 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
516
517 ucode_size = ucode->ucode_size;
518 ucode_mem = (uint32_t *)ucode->kaddr;
519 while (ucode_size) {
520 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
521
522 if (*ucode_mem != fw_sram_reg_val)
523 return false;
524
525 ucode_mem++;
526
527 ucode_size -= 4;
528 }
529
530 return true;
531}
532
533bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
534{
535 struct amdgpu_device *adev = psp->adev;
536 uint32_t reg;
537
538 reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000;
539 WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg);
540 reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2);
541 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
542}
543
544int psp_v3_1_mode1_reset(struct psp_context *psp)
545{
546 int ret;
547 uint32_t offset;
548 struct amdgpu_device *adev = psp->adev;
549
550 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
551
552 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
553
554 if (ret) {
555 DRM_INFO("psp is not working correctly before mode1 reset!\n");
556 return -EINVAL;
557 }
558
559
560 WREG32(offset, 0x70000);
561
562 mdelay(1000);
563
564 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
565
566 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
567
568 if (ret) {
569 DRM_INFO("psp mode 1 reset failed!\n");
570 return -EINVAL;
571 }
572
573 DRM_INFO("psp mode1 reset succeed \n");
574
575 return 0;
576}
577
