LXR linux/drivers/gpu/drm/amd/display/dc/dcn10/dcn10

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 *  and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DC_TIMING_GENERATOR_DCN10_H__
  27#define __DC_TIMING_GENERATOR_DCN10_H__
  28
  29#include "timing_generator.h"
  30
  31#define DCN10TG_FROM_TG(tg)\
  32        container_of(tg, struct optc, base)
  33
  34#define TG_COMMON_REG_LIST_DCN(inst) \
  35        SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
  36        SRI(OTG_VUPDATE_PARAM, OTG, inst),\
  37        SRI(OTG_VREADY_PARAM, OTG, inst),\
  38        SRI(OTG_BLANK_CONTROL, OTG, inst),\
  39        SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
  40        SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
  41        SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
  42        SRI(OTG_H_TOTAL, OTG, inst),\
  43        SRI(OTG_H_BLANK_START_END, OTG, inst),\
  44        SRI(OTG_H_SYNC_A, OTG, inst),\
  45        SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
  46        SRI(OTG_H_TIMING_CNTL, OTG, inst),\
  47        SRI(OTG_V_TOTAL, OTG, inst),\
  48        SRI(OTG_V_BLANK_START_END, OTG, inst),\
  49        SRI(OTG_V_SYNC_A, OTG, inst),\
  50        SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
  51        SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
  52        SRI(OTG_CONTROL, OTG, inst),\
  53        SRI(OTG_STEREO_CONTROL, OTG, inst),\
  54        SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
  55        SRI(OTG_STEREO_STATUS, OTG, inst),\
  56        SRI(OTG_V_TOTAL_MAX, OTG, inst),\
  57        SRI(OTG_V_TOTAL_MIN, OTG, inst),\
  58        SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
  59        SRI(OTG_TRIGA_CNTL, OTG, inst),\
  60        SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
  61        SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
  62        SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
  63        SRI(OTG_STATUS, OTG, inst),\
  64        SRI(OTG_STATUS_POSITION, OTG, inst),\
  65        SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
  66        SRI(OTG_BLACK_COLOR, OTG, inst),\
  67        SRI(OTG_CLOCK_CONTROL, OTG, inst),\
  68        SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
  69        SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
  70        SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
  71        SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
  72        SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
  73        SRI(CONTROL, VTG, inst),\
  74        SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
  75        SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
  76        SRI(OTG_GSL_CONTROL, OTG, inst)
  77
  78#define TG_COMMON_REG_LIST_DCN1_0(inst) \
  79        TG_COMMON_REG_LIST_DCN(inst),\
  80        SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
  81        SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
  82        SRI(OTG_TEST_PATTERN_COLOR, OTG, inst)
  83
  84
  85struct dcn_optc_registers {
  86        uint32_t OTG_VERT_SYNC_CONTROL;
  87        uint32_t OTG_MASTER_UPDATE_MODE;
  88        uint32_t OTG_GSL_CONTROL;
  89        uint32_t OTG_VSTARTUP_PARAM;
  90        uint32_t OTG_VUPDATE_PARAM;
  91        uint32_t OTG_VREADY_PARAM;
  92        uint32_t OTG_BLANK_CONTROL;
  93        uint32_t OTG_MASTER_UPDATE_LOCK;
  94        uint32_t OTG_GLOBAL_CONTROL0;
  95        uint32_t OTG_DOUBLE_BUFFER_CONTROL;
  96        uint32_t OTG_H_TOTAL;
  97        uint32_t OTG_H_BLANK_START_END;
  98        uint32_t OTG_H_SYNC_A;
  99        uint32_t OTG_H_SYNC_A_CNTL;
 100        uint32_t OTG_H_TIMING_CNTL;
 101        uint32_t OTG_V_TOTAL;
 102        uint32_t OTG_V_BLANK_START_END;
 103        uint32_t OTG_V_SYNC_A;
 104        uint32_t OTG_V_SYNC_A_CNTL;
 105        uint32_t OTG_INTERLACE_CONTROL;
 106        uint32_t OTG_CONTROL;
 107        uint32_t OTG_STEREO_CONTROL;
 108        uint32_t OTG_3D_STRUCTURE_CONTROL;
 109        uint32_t OTG_STEREO_STATUS;
 110        uint32_t OTG_V_TOTAL_MAX;
 111        uint32_t OTG_V_TOTAL_MIN;
 112        uint32_t OTG_V_TOTAL_CONTROL;
 113        uint32_t OTG_TRIGA_CNTL;
 114        uint32_t OTG_FORCE_COUNT_NOW_CNTL;
 115        uint32_t OTG_STATIC_SCREEN_CONTROL;
 116        uint32_t OTG_STATUS_FRAME_COUNT;
 117        uint32_t OTG_STATUS;
 118        uint32_t OTG_STATUS_POSITION;
 119        uint32_t OTG_NOM_VERT_POSITION;
 120        uint32_t OTG_BLACK_COLOR;
 121        uint32_t OTG_TEST_PATTERN_PARAMETERS;
 122        uint32_t OTG_TEST_PATTERN_CONTROL;
 123        uint32_t OTG_TEST_PATTERN_COLOR;
 124        uint32_t OTG_CLOCK_CONTROL;
 125        uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
 126        uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
 127        uint32_t OPTC_INPUT_CLOCK_CONTROL;
 128        uint32_t OPTC_DATA_SOURCE_SELECT;
 129        uint32_t OPTC_INPUT_GLOBAL_CONTROL;
 130        uint32_t CONTROL;
 131        uint32_t OTG_GSL_WINDOW_X;
 132        uint32_t OTG_GSL_WINDOW_Y;
 133        uint32_t OTG_VUPDATE_KEEPOUT;
 134        uint32_t OTG_DSC_START_POSITION;
 135};
 136
 137#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
 138        SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
 139        SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
 140        SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
 141        SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
 142        SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
 143        SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
 144        SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
 145        SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
 146        SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
 147        SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
 148        SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
 149        SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
 150        SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
 151        SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
 152        SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
 153        SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
 154        SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
 155        SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
 156        SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
 157        SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
 158        SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
 159        SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
 160        SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
 161        SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
 162        SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
 163        SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\
 164        SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
 165        SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
 166        SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
 167        SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
 168        SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
 169        SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
 170        SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
 171        SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
 172        SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
 173        SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
 174        SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
 175        SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
 176        SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
 177        SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
 178        SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
 179        SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
 180        SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
 181        SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
 182        SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
 183        SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
 184        SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
 185        SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
 186        SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
 187        SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
 188        SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
 189        SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
 190        SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
 191        SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
 192        SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
 193        SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
 194        SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
 195        SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
 196        SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
 197        SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
 198        SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
 199        SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
 200        SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
 201        SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
 202        SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
 203        SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
 204        SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
 205        SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
 206        SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
 207        SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
 208        SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
 209        SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
 210        SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
 211        SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
 212        SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
 213        SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
 214        SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
 215        SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
 216        SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
 217        SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
 218        SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
 219        SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
 220        SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\
 221        SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
 222        SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
 223        SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
 224        SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
 225        SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
 226        SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh)
 227
 228
 229#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
 230        TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
 231        SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
 232        SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
 233        SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
 234        SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
 235        SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
 236        SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
 237        SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
 238        SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
 239        SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
 240        SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
 241        SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
 242        SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh)
 243
 244#define TG_REG_FIELD_LIST(type) \
 245        type VSTARTUP_START;\
 246        type VUPDATE_OFFSET;\
 247        type VUPDATE_WIDTH;\
 248        type VREADY_OFFSET;\
 249        type OTG_BLANK_DATA_EN;\
 250        type OTG_BLANK_DE_MODE;\
 251        type OTG_CURRENT_BLANK_STATE;\
 252        type OTG_MASTER_UPDATE_LOCK;\
 253        type UPDATE_LOCK_STATUS;\
 254        type OTG_UPDATE_PENDING;\
 255        type OTG_MASTER_UPDATE_LOCK_SEL;\
 256        type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\
 257        type OTG_H_TOTAL;\
 258        type OTG_H_BLANK_START;\
 259        type OTG_H_BLANK_END;\
 260        type OTG_H_SYNC_A_START;\
 261        type OTG_H_SYNC_A_END;\
 262        type OTG_H_SYNC_A_POL;\
 263        type OTG_H_TIMING_DIV_BY2;\
 264        type OTG_V_TOTAL;\
 265        type OTG_V_BLANK_START;\
 266        type OTG_V_BLANK_END;\
 267        type OTG_V_SYNC_A_START;\
 268        type OTG_V_SYNC_A_END;\
 269        type OTG_V_SYNC_A_POL;\
 270        type OTG_INTERLACE_ENABLE;\
 271        type OTG_MASTER_EN;\
 272        type OTG_START_POINT_CNTL;\
 273        type OTG_DISABLE_POINT_CNTL;\
 274        type OTG_FIELD_NUMBER_CNTL;\
 275        type OTG_STEREO_EN;\
 276        type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\
 277        type OTG_STEREO_SYNC_OUTPUT_POLARITY;\
 278        type OTG_STEREO_EYE_FLAG_POLARITY;\
 279        type OTG_STEREO_CURRENT_EYE;\
 280        type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\
 281        type OTG_3D_STRUCTURE_EN;\
 282        type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
 283        type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
 284        type OTG_V_TOTAL_MAX;\
 285        type OTG_V_TOTAL_MIN;\
 286        type OTG_V_TOTAL_MIN_SEL;\
 287        type OTG_V_TOTAL_MAX_SEL;\
 288        type OTG_FORCE_LOCK_ON_EVENT;\
 289        type OTG_SET_V_TOTAL_MIN_MASK_EN;\
 290        type OTG_SET_V_TOTAL_MIN_MASK;\
 291        type OTG_FORCE_COUNT_NOW_CLEAR;\
 292        type OTG_FORCE_COUNT_NOW_MODE;\
 293        type OTG_FORCE_COUNT_NOW_OCCURRED;\
 294        type OTG_TRIGA_SOURCE_SELECT;\
 295        type OTG_TRIGA_SOURCE_PIPE_SELECT;\
 296        type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\
 297        type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\
 298        type OTG_STATIC_SCREEN_EVENT_MASK;\
 299        type OTG_STATIC_SCREEN_FRAME_COUNT;\
 300        type OTG_FRAME_COUNT;\
 301        type OTG_V_BLANK;\
 302        type OTG_V_ACTIVE_DISP;\
 303        type OTG_HORZ_COUNT;\
 304        type OTG_VERT_COUNT;\
 305        type OTG_VERT_COUNT_NOM;\
 306        type OTG_BLACK_COLOR_B_CB;\
 307        type OTG_BLACK_COLOR_G_Y;\
 308        type OTG_BLACK_COLOR_R_CR;\
 309        type OTG_TEST_PATTERN_INC0;\
 310        type OTG_TEST_PATTERN_INC1;\
 311        type OTG_TEST_PATTERN_VRES;\
 312        type OTG_TEST_PATTERN_HRES;\
 313        type OTG_TEST_PATTERN_RAMP0_OFFSET;\
 314        type OTG_TEST_PATTERN_EN;\
 315        type OTG_TEST_PATTERN_MODE;\
 316        type OTG_TEST_PATTERN_DYNAMIC_RANGE;\
 317        type OTG_TEST_PATTERN_COLOR_FORMAT;\
 318        type OTG_TEST_PATTERN_MASK;\
 319        type OTG_TEST_PATTERN_DATA;\
 320        type OTG_BUSY;\
 321        type OTG_CLOCK_EN;\
 322        type OTG_CLOCK_ON;\
 323        type OTG_CLOCK_GATE_DIS;\
 324        type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
 325        type OTG_VERTICAL_INTERRUPT2_LINE_START;\
 326        type OPTC_INPUT_CLK_EN;\
 327        type OPTC_INPUT_CLK_ON;\
 328        type OPTC_INPUT_CLK_GATE_DIS;\
 329        type OPTC_SRC_SEL;\
 330        type OPTC_SEG0_SRC_SEL;\
 331        type OPTC_UNDERFLOW_OCCURRED_STATUS;\
 332        type OPTC_UNDERFLOW_CLEAR;\
 333        type VTG0_ENABLE;\
 334        type VTG0_FP2;\
 335        type VTG0_VCOUNT_INIT;\
 336        type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\
 337        type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\
 338        type OTG_AUTO_FORCE_VSYNC_MODE;\
 339        type MASTER_UPDATE_INTERLACED_MODE;\
 340        type OTG_GSL0_EN;\
 341        type OTG_GSL1_EN;\
 342        type OTG_GSL2_EN;\
 343        type OTG_GSL_MASTER_EN;\
 344        type OTG_GSL_FORCE_DELAY;\
 345        type OTG_GSL_CHECK_ALL_FIELDS;\
 346        type OTG_GSL_WINDOW_START_X;\
 347        type OTG_GSL_WINDOW_END_X;\
 348        type OTG_GSL_WINDOW_START_Y;\
 349        type OTG_GSL_WINDOW_END_Y;\
 350        type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\
 351        type OTG_GSL_MASTER_MODE;\
 352        type OTG_MASTER_UPDATE_LOCK_GSL_EN;\
 353        type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\
 354        type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\
 355        type OTG_DSC_START_POSITION_X;\
 356        type OTG_DSC_START_POSITION_LINE_NUM;\
 357        type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;
 358
 359
 360struct dcn_optc_shift {
 361        TG_REG_FIELD_LIST(uint8_t)
 362};
 363
 364struct dcn_optc_mask {
 365        TG_REG_FIELD_LIST(uint32_t)
 366};
 367
 368struct optc {
 369        struct timing_generator base;
 370
 371        const struct dcn_optc_registers *tg_regs;
 372        const struct dcn_optc_shift *tg_shift;
 373        const struct dcn_optc_mask *tg_mask;
 374
 375        enum controller_id controller_id;
 376
 377        uint32_t max_h_total;
 378        uint32_t max_v_total;
 379
 380        uint32_t min_h_blank;
 381
 382        uint32_t min_h_sync_width;
 383        uint32_t min_v_sync_width;
 384        uint32_t min_v_blank;
 385        uint32_t min_v_blank_interlace;
 386};
 387
 388void dcn10_timing_generator_init(struct optc *optc);
 389
 390struct dcn_otg_state {
 391        uint32_t v_blank_start;
 392        uint32_t v_blank_end;
 393        uint32_t v_sync_a_pol;
 394        uint32_t v_total;
 395        uint32_t v_total_max;
 396        uint32_t v_total_min;
 397        uint32_t v_sync_a_start;
 398        uint32_t v_sync_a_end;
 399        uint32_t h_blank_start;
 400        uint32_t h_blank_end;
 401        uint32_t h_sync_a_start;
 402        uint32_t h_sync_a_end;
 403        uint32_t h_sync_a_pol;
 404        uint32_t h_total;
 405        uint32_t underflow_occurred_status;
 406        uint32_t otg_enabled;
 407};
 408
 409void optc1_read_otg_state(struct optc *optc1,
 410                struct dcn_otg_state *s);
 411
 412bool optc1_validate_timing(
 413        struct timing_generator *optc,
 414        const struct dc_crtc_timing *timing);
 415
 416void optc1_program_timing(
 417        struct timing_generator *optc,
 418        const struct dc_crtc_timing *dc_crtc_timing,
 419        bool use_vbios);
 420
 421void optc1_program_global_sync(
 422                struct timing_generator *optc);
 423
 424bool optc1_disable_crtc(struct timing_generator *optc);
 425
 426bool optc1_is_counter_moving(struct timing_generator *optc);
 427
 428void optc1_get_position(struct timing_generator *optc,
 429                struct crtc_position *position);
 430
 431uint32_t optc1_get_vblank_counter(struct timing_generator *optc);
 432
 433void optc1_get_crtc_scanoutpos(
 434        struct timing_generator *optc,
 435        uint32_t *v_blank_start,
 436        uint32_t *v_blank_end,
 437        uint32_t *h_position,
 438        uint32_t *v_position);
 439
 440void optc1_set_early_control(
 441        struct timing_generator *optc,
 442        uint32_t early_cntl);
 443
 444void optc1_wait_for_state(struct timing_generator *optc,
 445                enum crtc_state state);
 446
 447void optc1_set_blank(struct timing_generator *optc,
 448                bool enable_blanking);
 449
 450bool optc1_is_blanked(struct timing_generator *optc);
 451
 452void optc1_program_blank_color(
 453                struct timing_generator *optc,
 454                const struct tg_color *black_color);
 455
 456bool optc1_did_triggered_reset_occur(
 457        struct timing_generator *optc);
 458
 459void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst);
 460
 461void optc1_disable_reset_trigger(struct timing_generator *optc);
 462
 463void optc1_lock(struct timing_generator *optc);
 464
 465void optc1_unlock(struct timing_generator *optc);
 466
 467void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);
 468
 469void optc1_set_drr(
 470        struct timing_generator *optc,
 471        const struct drr_params *params);
 472
 473void optc1_set_static_screen_control(
 474        struct timing_generator *optc,
 475        uint32_t value);
 476
 477void optc1_program_stereo(struct timing_generator *optc,
 478        const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
 479
 480bool optc1_is_stereo_left_eye(struct timing_generator *optc);
 481
 482#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
 483