1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#ifndef _CZ_HWMGR_H_
25#define _CZ_HWMGR_H_
26
27#include "cgs_common.h"
28#include "ppatomctrl.h"
29
30#define CZ_NUM_NBPSTATES 4
31#define CZ_NUM_NBPMEMORYCLOCK 2
32#define MAX_DISPLAY_CLOCK_LEVEL 8
33#define CZ_AT_DFLT 30
34#define CZ_MAX_HARDWARE_POWERLEVELS 8
35#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
36#define CZ_MIN_DEEP_SLEEP_SCLK 800
37
38
39#define DEVICE_ID_CZ_9870 0x9870
40#define DEVICE_ID_CZ_9874 0x9874
41#define DEVICE_ID_CZ_9875 0x9875
42#define DEVICE_ID_CZ_9876 0x9876
43#define DEVICE_ID_CZ_9877 0x9877
44
45#define PHMCZ_WRITE_SMC_REGISTER(device, reg, value) \
46 cgs_write_ind_register(device, CGS_IND_REG__SMC, ix##reg, value)
47
48struct cz_dpm_entry {
49 uint32_t soft_min_clk;
50 uint32_t hard_min_clk;
51 uint32_t soft_max_clk;
52 uint32_t hard_max_clk;
53};
54
55struct cz_sys_info {
56 uint32_t bootup_uma_clock;
57 uint32_t bootup_engine_clock;
58 uint32_t dentist_vco_freq;
59 uint32_t nb_dpm_enable;
60 uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK];
61 uint32_t nbp_n_clock[CZ_NUM_NBPSTATES];
62 uint16_t nbp_voltage_index[CZ_NUM_NBPSTATES];
63 uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL];
64 uint16_t bootup_nb_voltage_index;
65 uint8_t htc_tmp_lmt;
66 uint8_t htc_hyst_lmt;
67 uint32_t system_config;
68 uint32_t uma_channel_number;
69};
70
71#define MAX_DISPLAYPHY_IDS 0x8
72#define DISPLAYPHY_LANEMASK 0xF
73#define UNKNOWN_TRANSMITTER_PHY_ID (-1)
74
75#define DISPLAYPHY_PHYID_SHIFT 24
76#define DISPLAYPHY_LANESELECT_SHIFT 16
77
78#define DISPLAYPHY_RX_SELECT 0x1
79#define DISPLAYPHY_TX_SELECT 0x2
80#define DISPLAYPHY_CORE_SELECT 0x4
81
82#define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \
83 (((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \
84 ((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \
85 ((rx) ? DISPLAYPHY_RX_SELECT : 0) | \
86 ((tx) ? DISPLAYPHY_TX_SELECT : 0) | \
87 ((core) ? DISPLAYPHY_CORE_SELECT : 0))
88
89struct cz_display_phy_info_entry {
90 uint8_t phy_present;
91 uint8_t active_lane_mapping;
92 uint8_t display_config_type;
93 uint8_t active_number_of_lanes;
94};
95
96#define CZ_MAX_DISPLAYPHY_IDS 10
97
98struct cz_display_phy_info {
99 bool display_phy_access_initialized;
100 struct cz_display_phy_info_entry entries[CZ_MAX_DISPLAYPHY_IDS];
101};
102
103struct cz_power_level {
104 uint32_t engineClock;
105 uint8_t vddcIndex;
106 uint8_t dsDividerIndex;
107 uint8_t ssDividerIndex;
108 uint8_t allowGnbSlow;
109 uint8_t forceNBPstate;
110 uint8_t display_wm;
111 uint8_t vce_wm;
112 uint8_t numSIMDToPowerDown;
113 uint8_t hysteresis_up;
114 uint8_t rsv[3];
115};
116
117struct cz_uvd_clocks {
118 uint32_t vclk;
119 uint32_t dclk;
120 uint32_t vclk_low_divider;
121 uint32_t vclk_high_divider;
122 uint32_t dclk_low_divider;
123 uint32_t dclk_high_divider;
124};
125
126enum cz_pstate_previous_action {
127 DO_NOTHING = 1,
128 FORCE_HIGH,
129 CANCEL_FORCE_HIGH
130};
131
132struct pp_disable_nb_ps_flags {
133 union {
134 struct {
135 uint32_t entry : 1;
136 uint32_t display : 1;
137 uint32_t driver: 1;
138 uint32_t vce : 1;
139 uint32_t uvd : 1;
140 uint32_t acp : 1;
141 uint32_t reserved: 26;
142 } bits;
143 uint32_t u32All;
144 };
145};
146
147struct cz_power_state {
148 unsigned int magic;
149 uint32_t level;
150 struct cz_uvd_clocks uvd_clocks;
151 uint32_t evclk;
152 uint32_t ecclk;
153 uint32_t samclk;
154 uint32_t acpclk;
155 bool need_dfs_bypass;
156 uint32_t nbps_flags;
157 uint32_t bapm_flags;
158 uint8_t dpm_0_pg_nb_ps_low;
159 uint8_t dpm_0_pg_nb_ps_high;
160 uint8_t dpm_x_nb_ps_low;
161 uint8_t dpm_x_nb_ps_high;
162 enum cz_pstate_previous_action action;
163 struct cz_power_level levels[CZ_MAX_HARDWARE_POWERLEVELS];
164 struct pp_disable_nb_ps_flags disable_nb_ps_flag;
165};
166
167#define DPMFlags_SCLK_Enabled 0x00000001
168#define DPMFlags_UVD_Enabled 0x00000002
169#define DPMFlags_VCE_Enabled 0x00000004
170#define DPMFlags_ACP_Enabled 0x00000008
171#define DPMFlags_ForceHighestValid 0x40000000
172#define DPMFlags_Debug 0x80000000
173
174#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001
175#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000
176#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000
177#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000
178
179struct cc6_settings {
180 bool cc6_setting_changed;
181 bool nb_pstate_switch_disable;
182 bool cpu_cc6_disable;
183 bool cpu_pstate_disable;
184 uint32_t cpu_pstate_separation_time;
185};
186
187struct cz_hwmgr {
188 uint32_t activity_target[CZ_MAX_HARDWARE_POWERLEVELS];
189 uint32_t dpm_interval;
190
191 uint32_t voltage_drop_threshold;
192
193 uint32_t voting_rights_clients;
194
195 uint32_t disable_driver_thermal_policy;
196
197 uint32_t static_screen_threshold;
198
199 uint32_t gfx_power_gating_threshold;
200
201 uint32_t activity_hysteresis;
202 uint32_t bootup_sclk_divider;
203 uint32_t gfx_ramp_step;
204 uint32_t gfx_ramp_delay;
205
206 uint32_t thermal_auto_throttling_treshold;
207
208 struct cz_sys_info sys_info;
209
210 struct cz_power_level boot_power_level;
211 struct cz_power_state *cz_current_ps;
212 struct cz_power_state *cz_requested_ps;
213
214 uint32_t mgcg_cgtt_local0;
215 uint32_t mgcg_cgtt_local1;
216
217 uint32_t tdr_clock;
218
219 uint32_t ddi_power_gating_disabled;
220 uint32_t disable_gfx_power_gating_in_uvd;
221 uint32_t disable_nb_ps3_in_battery;
222
223 uint32_t lock_nb_ps_in_uvd_play_back;
224
225 struct cz_display_phy_info display_phy_info;
226 uint32_t vce_slow_sclk_threshold;
227 uint32_t dce_slow_sclk_threshold;
228 uint32_t min_sclk_did;
229
230 bool disp_clk_bypass;
231 bool disp_clk_bypass_pending;
232 uint32_t bapm_enabled;
233 uint32_t clock_slow_down_freq;
234 uint32_t skip_clock_slow_down;
235 uint32_t enable_nb_ps_policy;
236 uint32_t voltage_drop_in_dce_power_gating;
237 uint32_t uvd_dpm_interval;
238 uint32_t override_dynamic_mgpg;
239 uint32_t lclk_deep_enabled;
240
241 uint32_t uvd_performance;
242
243 bool video_start;
244 bool battery_state;
245 uint32_t lowest_valid;
246 uint32_t highest_valid;
247 uint32_t high_voltage_threshold;
248 uint32_t is_nb_dpm_enabled;
249 struct cc6_settings cc6_settings;
250 uint32_t is_voltage_island_enabled;
251
252 bool pgacpinit;
253
254 uint8_t disp_config;
255
256
257 uint32_t power_containment_features;
258 bool cac_enabled;
259 bool disable_uvd_power_tune_feature;
260 bool enable_ba_pm_feature;
261 bool enable_tdc_limit_feature;
262
263 uint32_t sram_end;
264 uint32_t dpm_table_start;
265 uint32_t soft_regs_start;
266
267 uint8_t uvd_level_count;
268 uint8_t vce_level_count;
269
270 uint8_t acp_level_count;
271 uint8_t samu_level_count;
272 uint32_t fps_high_threshold;
273 uint32_t fps_low_threshold;
274
275 uint32_t dpm_flags;
276 struct cz_dpm_entry sclk_dpm;
277 struct cz_dpm_entry uvd_dpm;
278 struct cz_dpm_entry vce_dpm;
279 struct cz_dpm_entry acp_dpm;
280
281 uint8_t uvd_boot_level;
282 uint8_t vce_boot_level;
283 uint8_t acp_boot_level;
284 uint8_t samu_boot_level;
285 uint8_t uvd_interval;
286 uint8_t vce_interval;
287 uint8_t acp_interval;
288 uint8_t samu_interval;
289
290 uint8_t graphics_interval;
291 uint8_t graphics_therm_throttle_enable;
292 uint8_t graphics_voltage_change_enable;
293
294 uint8_t graphics_clk_slow_enable;
295 uint8_t graphics_clk_slow_divider;
296
297 uint32_t display_cac;
298 uint32_t low_sclk_interrupt_threshold;
299
300 uint32_t dram_log_addr_h;
301 uint32_t dram_log_addr_l;
302 uint32_t dram_log_phy_addr_h;
303 uint32_t dram_log_phy_addr_l;
304 uint32_t dram_log_buff_size;
305
306 bool uvd_power_gated;
307 bool vce_power_gated;
308 bool samu_power_gated;
309 bool acp_power_gated;
310 bool acp_power_up_no_dsp;
311 uint32_t active_process_mask;
312
313 uint32_t max_sclk_level;
314 uint32_t num_of_clk_entries;
315};
316
317struct pp_hwmgr;
318
319int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr);
320int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr);
321int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr);
322int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr);
323int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
324int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr);
325#endif
326
