LXR linux/drivers/gpu/drm/i915/intel

   1/*
   2 * Copyright © 2016 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21 * SOFTWARE.
  22 */
  23
  24/*
  25 * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away
  26 * the VBT from the rest of the driver. Add the parsed, clean data to struct
  27 * intel_vbt_data within struct drm_i915_private.
  28 */
  29
  30#ifndef _INTEL_BIOS_H_
  31#define _INTEL_BIOS_H_
  32
  33enum intel_backlight_type {
  34        INTEL_BACKLIGHT_PMIC,
  35        INTEL_BACKLIGHT_LPSS,
  36        INTEL_BACKLIGHT_DISPLAY_DDI,
  37        INTEL_BACKLIGHT_DSI_DCS,
  38        INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
  39};
  40
  41struct edp_power_seq {
  42        u16 t1_t3;
  43        u16 t8;
  44        u16 t9;
  45        u16 t10;
  46        u16 t11_t12;
  47} __packed;
  48
  49/*
  50 * MIPI Sequence Block definitions
  51 *
  52 * Note the VBT spec has AssertReset / DeassertReset swapped from their
  53 * usual naming, we use the proper names here to avoid confusion when
  54 * reading the code.
  55 */
  56enum mipi_seq {
  57        MIPI_SEQ_END = 0,
  58        MIPI_SEQ_DEASSERT_RESET,        /* Spec says MipiAssertResetPin */
  59        MIPI_SEQ_INIT_OTP,
  60        MIPI_SEQ_DISPLAY_ON,
  61        MIPI_SEQ_DISPLAY_OFF,
  62        MIPI_SEQ_ASSERT_RESET,          /* Spec says MipiDeassertResetPin */
  63        MIPI_SEQ_BACKLIGHT_ON,          /* sequence block v2+ */
  64        MIPI_SEQ_BACKLIGHT_OFF,         /* sequence block v2+ */
  65        MIPI_SEQ_TEAR_ON,               /* sequence block v2+ */
  66        MIPI_SEQ_TEAR_OFF,              /* sequence block v3+ */
  67        MIPI_SEQ_POWER_ON,              /* sequence block v3+ */
  68        MIPI_SEQ_POWER_OFF,             /* sequence block v3+ */
  69        MIPI_SEQ_MAX
  70};
  71
  72enum mipi_seq_element {
  73        MIPI_SEQ_ELEM_END = 0,
  74        MIPI_SEQ_ELEM_SEND_PKT,
  75        MIPI_SEQ_ELEM_DELAY,
  76        MIPI_SEQ_ELEM_GPIO,
  77        MIPI_SEQ_ELEM_I2C,              /* sequence block v2+ */
  78        MIPI_SEQ_ELEM_SPI,              /* sequence block v3+ */
  79        MIPI_SEQ_ELEM_PMIC,             /* sequence block v3+ */
  80        MIPI_SEQ_ELEM_MAX
  81};
  82
  83#define MIPI_DSI_UNDEFINED_PANEL_ID     0
  84#define MIPI_DSI_GENERIC_PANEL_ID       1
  85
  86struct mipi_config {
  87        u16 panel_id;
  88
  89        /* General Params */
  90        u32 enable_dithering:1;
  91        u32 rsvd1:1;
  92        u32 is_bridge:1;
  93
  94        u32 panel_arch_type:2;
  95        u32 is_cmd_mode:1;
  96
  97#define NON_BURST_SYNC_PULSE    0x1
  98#define NON_BURST_SYNC_EVENTS   0x2
  99#define BURST_MODE              0x3
 100        u32 video_transfer_mode:2;
 101
 102        u32 cabc_supported:1;
 103#define PPS_BLC_PMIC   0
 104#define PPS_BLC_SOC    1
 105        u32 pwm_blc:1;
 106
 107        /* Bit 13:10 */
 108#define PIXEL_FORMAT_RGB565                     0x1
 109#define PIXEL_FORMAT_RGB666                     0x2
 110#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED      0x3
 111#define PIXEL_FORMAT_RGB888                     0x4
 112        u32 videomode_color_format:4;
 113
 114        /* Bit 15:14 */
 115#define ENABLE_ROTATION_0       0x0
 116#define ENABLE_ROTATION_90      0x1
 117#define ENABLE_ROTATION_180     0x2
 118#define ENABLE_ROTATION_270     0x3
 119        u32 rotation:2;
 120        u32 bta_enabled:1;
 121        u32 rsvd2:15;
 122
 123        /* 2 byte Port Description */
 124#define DUAL_LINK_NOT_SUPPORTED 0
 125#define DUAL_LINK_FRONT_BACK    1
 126#define DUAL_LINK_PIXEL_ALT     2
 127        u16 dual_link:2;
 128        u16 lane_cnt:2;
 129        u16 pixel_overlap:3;
 130        u16 rgb_flip:1;
 131#define DL_DCS_PORT_A                   0x00
 132#define DL_DCS_PORT_C                   0x01
 133#define DL_DCS_PORT_A_AND_C             0x02
 134        u16 dl_dcs_cabc_ports:2;
 135        u16 dl_dcs_backlight_ports:2;
 136        u16 rsvd3:4;
 137
 138        u16 rsvd4;
 139
 140        u8 rsvd5;
 141        u32 target_burst_mode_freq;
 142        u32 dsi_ddr_clk;
 143        u32 bridge_ref_clk;
 144
 145#define  BYTE_CLK_SEL_20MHZ             0
 146#define  BYTE_CLK_SEL_10MHZ             1
 147#define  BYTE_CLK_SEL_5MHZ              2
 148        u8 byte_clk_sel:2;
 149
 150        u8 rsvd6:6;
 151
 152        /* DPHY Flags */
 153        u16 dphy_param_valid:1;
 154        u16 eot_pkt_disabled:1;
 155        u16 enable_clk_stop:1;
 156        u16 rsvd7:13;
 157
 158        u32 hs_tx_timeout;
 159        u32 lp_rx_timeout;
 160        u32 turn_around_timeout;
 161        u32 device_reset_timer;
 162        u32 master_init_timer;
 163        u32 dbi_bw_timer;
 164        u32 lp_byte_clk_val;
 165
 166        /*  4 byte Dphy Params */
 167        u32 prepare_cnt:6;
 168        u32 rsvd8:2;
 169        u32 clk_zero_cnt:8;
 170        u32 trail_cnt:5;
 171        u32 rsvd9:3;
 172        u32 exit_zero_cnt:6;
 173        u32 rsvd10:2;
 174
 175        u32 clk_lane_switch_cnt;
 176        u32 hl_switch_cnt;
 177
 178        u32 rsvd11[6];
 179
 180        /* timings based on dphy spec */
 181        u8 tclk_miss;
 182        u8 tclk_post;
 183        u8 rsvd12;
 184        u8 tclk_pre;
 185        u8 tclk_prepare;
 186        u8 tclk_settle;
 187        u8 tclk_term_enable;
 188        u8 tclk_trail;
 189        u16 tclk_prepare_clkzero;
 190        u8 rsvd13;
 191        u8 td_term_enable;
 192        u8 teot;
 193        u8 ths_exit;
 194        u8 ths_prepare;
 195        u16 ths_prepare_hszero;
 196        u8 rsvd14;
 197        u8 ths_settle;
 198        u8 ths_skip;
 199        u8 ths_trail;
 200        u8 tinit;
 201        u8 tlpx;
 202        u8 rsvd15[3];
 203
 204        /* GPIOs */
 205        u8 panel_enable;
 206        u8 bl_enable;
 207        u8 pwm_enable;
 208        u8 reset_r_n;
 209        u8 pwr_down_r;
 210        u8 stdby_r_n;
 211
 212} __packed;
 213
 214/* all delays have a unit of 100us */
 215struct mipi_pps_data {
 216        u16 panel_on_delay;
 217        u16 bl_enable_delay;
 218        u16 bl_disable_delay;
 219        u16 panel_off_delay;
 220        u16 panel_power_cycle_delay;
 221} __packed;
 222
 223#endif /* _INTEL_BIOS_H_ */
 224