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18#include <drm/drm_crtc.h>
19#include <drm/drm_crtc_helper.h>
20#include <drm/drm_flip_work.h>
21#include <drm/drm_mode.h>
22
23#include "mdp4_kms.h"
24
25struct mdp4_crtc {
26 struct drm_crtc base;
27 char name[8];
28 int id;
29 int ovlp;
30 enum mdp4_dma dma;
31 bool enabled;
32
33
34 int mixer;
35
36 struct {
37 spinlock_t lock;
38 bool stale;
39 uint32_t width, height;
40 uint32_t x, y;
41
42
43 uint32_t next_iova;
44 struct drm_gem_object *next_bo;
45
46
47 struct drm_gem_object *scanout_bo;
48 } cursor;
49
50
51
52 struct drm_pending_vblank_event *event;
53
54
55
56
57 u32 flushed_mask;
58
59#define PENDING_CURSOR 0x1
60#define PENDING_FLIP 0x2
61 atomic_t pending;
62
63
64 struct drm_flip_work unref_cursor_work;
65
66 struct mdp_irq vblank;
67 struct mdp_irq err;
68};
69#define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
70
71static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
72{
73 struct msm_drm_private *priv = crtc->dev->dev_private;
74 return to_mdp4_kms(to_mdp_kms(priv->kms));
75}
76
77static void request_pending(struct drm_crtc *crtc, uint32_t pending)
78{
79 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
80
81 atomic_or(pending, &mdp4_crtc->pending);
82 mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
83}
84
85static void crtc_flush(struct drm_crtc *crtc)
86{
87 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
88 struct mdp4_kms *mdp4_kms = get_kms(crtc);
89 struct drm_plane *plane;
90 uint32_t flush = 0;
91
92 drm_atomic_crtc_for_each_plane(plane, crtc) {
93 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
94 flush |= pipe2flush(pipe_id);
95 }
96
97 flush |= ovlp2flush(mdp4_crtc->ovlp);
98
99 DBG("%s: flush=%08x", mdp4_crtc->name, flush);
100
101 mdp4_crtc->flushed_mask = flush;
102
103 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
104}
105
106
107static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
108{
109 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
110 struct drm_device *dev = crtc->dev;
111 struct drm_pending_vblank_event *event;
112 unsigned long flags;
113
114 spin_lock_irqsave(&dev->event_lock, flags);
115 event = mdp4_crtc->event;
116 if (event) {
117 mdp4_crtc->event = NULL;
118 DBG("%s: send event: %p", mdp4_crtc->name, event);
119 drm_crtc_send_vblank_event(crtc, event);
120 }
121 spin_unlock_irqrestore(&dev->event_lock, flags);
122}
123
124static void unref_cursor_worker(struct drm_flip_work *work, void *val)
125{
126 struct mdp4_crtc *mdp4_crtc =
127 container_of(work, struct mdp4_crtc, unref_cursor_work);
128 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
129 struct msm_kms *kms = &mdp4_kms->base.base;
130
131 msm_gem_put_iova(val, kms->aspace);
132 drm_gem_object_unreference_unlocked(val);
133}
134
135static void mdp4_crtc_destroy(struct drm_crtc *crtc)
136{
137 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
138
139 drm_crtc_cleanup(crtc);
140 drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
141
142 kfree(mdp4_crtc);
143}
144
145
146static const int idxs[] = {
147 [VG1] = 1,
148 [VG2] = 2,
149 [RGB1] = 0,
150 [RGB2] = 0,
151 [RGB3] = 0,
152 [VG3] = 3,
153 [VG4] = 4,
154
155};
156
157
158
159
160
161
162static void setup_mixer(struct mdp4_kms *mdp4_kms)
163{
164 struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
165 struct drm_crtc *crtc;
166 uint32_t mixer_cfg = 0;
167 static const enum mdp_mixer_stage_id stages[] = {
168 STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
169 };
170
171 list_for_each_entry(crtc, &config->crtc_list, head) {
172 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
173 struct drm_plane *plane;
174
175 drm_atomic_crtc_for_each_plane(plane, crtc) {
176 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
177 int idx = idxs[pipe_id];
178 mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
179 pipe_id, stages[idx]);
180 }
181 }
182
183 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
184}
185
186static void blend_setup(struct drm_crtc *crtc)
187{
188 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
189 struct mdp4_kms *mdp4_kms = get_kms(crtc);
190 struct drm_plane *plane;
191 int i, ovlp = mdp4_crtc->ovlp;
192 bool alpha[4]= { false, false, false, false };
193
194 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
195 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
196 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
197 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
198
199 drm_atomic_crtc_for_each_plane(plane, crtc) {
200 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
201 int idx = idxs[pipe_id];
202 if (idx > 0) {
203 const struct mdp_format *format =
204 to_mdp_format(msm_framebuffer_format(plane->fb));
205 alpha[idx-1] = format->alpha_enable;
206 }
207 }
208
209 for (i = 0; i < 4; i++) {
210 uint32_t op;
211
212 if (alpha[i]) {
213 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
214 MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
215 MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
216 } else {
217 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
218 MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
219 }
220
221 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
222 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
223 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
224 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
225 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
226 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
227 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
228 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
229 }
230
231 setup_mixer(mdp4_kms);
232}
233
234static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
235{
236 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
237 struct mdp4_kms *mdp4_kms = get_kms(crtc);
238 enum mdp4_dma dma = mdp4_crtc->dma;
239 int ovlp = mdp4_crtc->ovlp;
240 struct drm_display_mode *mode;
241
242 if (WARN_ON(!crtc->state))
243 return;
244
245 mode = &crtc->state->adjusted_mode;
246
247 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
248 mdp4_crtc->name, mode->base.id, mode->name,
249 mode->vrefresh, mode->clock,
250 mode->hdisplay, mode->hsync_start,
251 mode->hsync_end, mode->htotal,
252 mode->vdisplay, mode->vsync_start,
253 mode->vsync_end, mode->vtotal,
254 mode->type, mode->flags);
255
256 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
257 MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
258 MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
259
260
261 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
262 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
263 mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
264 MDP4_DMA_DST_SIZE_WIDTH(0) |
265 MDP4_DMA_DST_SIZE_HEIGHT(0));
266
267 mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
268 mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
269 MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
270 MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
271 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
272
273 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
274
275 if (dma == DMA_E) {
276 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
277 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
278 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
279 }
280}
281
282static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc,
283 struct drm_crtc_state *old_state)
284{
285 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
286 struct mdp4_kms *mdp4_kms = get_kms(crtc);
287
288 DBG("%s", mdp4_crtc->name);
289
290 if (WARN_ON(!mdp4_crtc->enabled))
291 return;
292
293
294 drm_crtc_vblank_off(crtc);
295
296 mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
297 mdp4_disable(mdp4_kms);
298
299 mdp4_crtc->enabled = false;
300}
301
302static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc,
303 struct drm_crtc_state *old_state)
304{
305 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
306 struct mdp4_kms *mdp4_kms = get_kms(crtc);
307
308 DBG("%s", mdp4_crtc->name);
309
310 if (WARN_ON(mdp4_crtc->enabled))
311 return;
312
313 mdp4_enable(mdp4_kms);
314
315
316 drm_crtc_vblank_on(crtc);
317
318 mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
319
320 crtc_flush(crtc);
321
322 mdp4_crtc->enabled = true;
323}
324
325static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
326 struct drm_crtc_state *state)
327{
328 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
329 DBG("%s: check", mdp4_crtc->name);
330
331 return 0;
332}
333
334static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc,
335 struct drm_crtc_state *old_crtc_state)
336{
337 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
338 DBG("%s: begin", mdp4_crtc->name);
339}
340
341static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
342 struct drm_crtc_state *old_crtc_state)
343{
344 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
345 struct drm_device *dev = crtc->dev;
346 unsigned long flags;
347
348 DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
349
350 WARN_ON(mdp4_crtc->event);
351
352 spin_lock_irqsave(&dev->event_lock, flags);
353 mdp4_crtc->event = crtc->state->event;
354 spin_unlock_irqrestore(&dev->event_lock, flags);
355
356 blend_setup(crtc);
357 crtc_flush(crtc);
358 request_pending(crtc, PENDING_FLIP);
359}
360
361#define CURSOR_WIDTH 64
362#define CURSOR_HEIGHT 64
363
364
365
366
367
368
369static void update_cursor(struct drm_crtc *crtc)
370{
371 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
372 struct mdp4_kms *mdp4_kms = get_kms(crtc);
373 struct msm_kms *kms = &mdp4_kms->base.base;
374 enum mdp4_dma dma = mdp4_crtc->dma;
375 unsigned long flags;
376
377 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
378 if (mdp4_crtc->cursor.stale) {
379 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
380 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
381 uint64_t iova = mdp4_crtc->cursor.next_iova;
382
383 if (next_bo) {
384
385 drm_gem_object_reference(next_bo);
386 msm_gem_get_iova(next_bo, kms->aspace, &iova);
387
388
389 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
390 MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
391 MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
392 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
393 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
394 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
395 MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
396 } else {
397
398 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
399 mdp4_kms->blank_cursor_iova);
400 }
401
402
403 if (prev_bo)
404 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
405
406 mdp4_crtc->cursor.scanout_bo = next_bo;
407 mdp4_crtc->cursor.stale = false;
408 }
409
410 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
411 MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
412 MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
413
414 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
415}
416
417static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
418 struct drm_file *file_priv, uint32_t handle,
419 uint32_t width, uint32_t height)
420{
421 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
422 struct mdp4_kms *mdp4_kms = get_kms(crtc);
423 struct msm_kms *kms = &mdp4_kms->base.base;
424 struct drm_device *dev = crtc->dev;
425 struct drm_gem_object *cursor_bo, *old_bo;
426 unsigned long flags;
427 uint64_t iova;
428 int ret;
429
430 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
431 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
432 return -EINVAL;
433 }
434
435 if (handle) {
436 cursor_bo = drm_gem_object_lookup(file_priv, handle);
437 if (!cursor_bo)
438 return -ENOENT;
439 } else {
440 cursor_bo = NULL;
441 }
442
443 if (cursor_bo) {
444 ret = msm_gem_get_iova(cursor_bo, kms->aspace, &iova);
445 if (ret)
446 goto fail;
447 } else {
448 iova = 0;
449 }
450
451 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
452 old_bo = mdp4_crtc->cursor.next_bo;
453 mdp4_crtc->cursor.next_bo = cursor_bo;
454 mdp4_crtc->cursor.next_iova = iova;
455 mdp4_crtc->cursor.width = width;
456 mdp4_crtc->cursor.height = height;
457 mdp4_crtc->cursor.stale = true;
458 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
459
460 if (old_bo) {
461
462 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
463 }
464
465 request_pending(crtc, PENDING_CURSOR);
466
467 return 0;
468
469fail:
470 drm_gem_object_unreference_unlocked(cursor_bo);
471 return ret;
472}
473
474static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
475{
476 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
477 unsigned long flags;
478
479 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
480 mdp4_crtc->cursor.x = x;
481 mdp4_crtc->cursor.y = y;
482 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
483
484 crtc_flush(crtc);
485 request_pending(crtc, PENDING_CURSOR);
486
487 return 0;
488}
489
490static const struct drm_crtc_funcs mdp4_crtc_funcs = {
491 .set_config = drm_atomic_helper_set_config,
492 .destroy = mdp4_crtc_destroy,
493 .page_flip = drm_atomic_helper_page_flip,
494 .cursor_set = mdp4_crtc_cursor_set,
495 .cursor_move = mdp4_crtc_cursor_move,
496 .reset = drm_atomic_helper_crtc_reset,
497 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
498 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
499};
500
501static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
502 .mode_set_nofb = mdp4_crtc_mode_set_nofb,
503 .atomic_check = mdp4_crtc_atomic_check,
504 .atomic_begin = mdp4_crtc_atomic_begin,
505 .atomic_flush = mdp4_crtc_atomic_flush,
506 .atomic_enable = mdp4_crtc_atomic_enable,
507 .atomic_disable = mdp4_crtc_atomic_disable,
508};
509
510static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
511{
512 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
513 struct drm_crtc *crtc = &mdp4_crtc->base;
514 struct msm_drm_private *priv = crtc->dev->dev_private;
515 unsigned pending;
516
517 mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
518
519 pending = atomic_xchg(&mdp4_crtc->pending, 0);
520
521 if (pending & PENDING_FLIP) {
522 complete_flip(crtc, NULL);
523 }
524
525 if (pending & PENDING_CURSOR) {
526 update_cursor(crtc);
527 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
528 }
529}
530
531static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
532{
533 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
534 struct drm_crtc *crtc = &mdp4_crtc->base;
535 DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
536 crtc_flush(crtc);
537}
538
539static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc)
540{
541 struct drm_device *dev = crtc->dev;
542 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
543 struct mdp4_kms *mdp4_kms = get_kms(crtc);
544 int ret;
545
546 ret = drm_crtc_vblank_get(crtc);
547 if (ret)
548 return;
549
550 ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
551 !(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) &
552 mdp4_crtc->flushed_mask),
553 msecs_to_jiffies(50));
554 if (ret <= 0)
555 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id);
556
557 mdp4_crtc->flushed_mask = 0;
558
559 drm_crtc_vblank_put(crtc);
560}
561
562uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
563{
564 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
565 return mdp4_crtc->vblank.irqmask;
566}
567
568
569void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
570{
571 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
572 struct mdp4_kms *mdp4_kms = get_kms(crtc);
573
574 mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
575}
576
577
578void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
579{
580 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
581 struct mdp4_kms *mdp4_kms = get_kms(crtc);
582 uint32_t intf_sel;
583
584 intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
585
586 switch (mdp4_crtc->dma) {
587 case DMA_P:
588 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
589 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
590 break;
591 case DMA_S:
592 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
593 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
594 break;
595 case DMA_E:
596 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
597 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
598 break;
599 }
600
601 if (intf == INTF_DSI_VIDEO) {
602 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
603 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
604 } else if (intf == INTF_DSI_CMD) {
605 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
606 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
607 }
608
609 mdp4_crtc->mixer = mixer;
610
611 blend_setup(crtc);
612
613 DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
614
615 mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
616}
617
618void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc)
619{
620
621
622
623
624 mdp4_crtc_wait_for_flush_done(crtc);
625}
626
627static const char *dma_names[] = {
628 "DMA_P", "DMA_S", "DMA_E",
629};
630
631
632struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
633 struct drm_plane *plane, int id, int ovlp_id,
634 enum mdp4_dma dma_id)
635{
636 struct drm_crtc *crtc = NULL;
637 struct mdp4_crtc *mdp4_crtc;
638
639 mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
640 if (!mdp4_crtc)
641 return ERR_PTR(-ENOMEM);
642
643 crtc = &mdp4_crtc->base;
644
645 mdp4_crtc->id = id;
646
647 mdp4_crtc->ovlp = ovlp_id;
648 mdp4_crtc->dma = dma_id;
649
650 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
651 mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
652
653 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
654 mdp4_crtc->err.irq = mdp4_crtc_err_irq;
655
656 snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
657 dma_names[dma_id], ovlp_id);
658
659 spin_lock_init(&mdp4_crtc->cursor.lock);
660
661 drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
662 "unref cursor", unref_cursor_worker);
663
664 drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs,
665 NULL);
666 drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
667 plane->crtc = crtc;
668
669 return crtc;
670}
671