linux/drivers/gpu/drm/nouveau/dispnv04/dfp.c
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   1/*
   2 * Copyright 2003 NVIDIA, Corporation
   3 * Copyright 2006 Dave Airlie
   4 * Copyright 2007 Maarten Maathuis
   5 * Copyright 2007-2009 Stuart Bennett
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a
   8 * copy of this software and associated documentation files (the "Software"),
   9 * to deal in the Software without restriction, including without limitation
  10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11 * and/or sell copies of the Software, and to permit persons to whom the
  12 * Software is furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice (including the next
  15 * paragraph) shall be included in all copies or substantial portions of the
  16 * Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24 * DEALINGS IN THE SOFTWARE.
  25 */
  26
  27#include <drm/drmP.h>
  28#include <drm/drm_crtc_helper.h>
  29
  30#include "nouveau_drv.h"
  31#include "nouveau_reg.h"
  32#include "nouveau_encoder.h"
  33#include "nouveau_connector.h"
  34#include "nouveau_crtc.h"
  35#include "hw.h"
  36#include "nvreg.h"
  37
  38#include <drm/i2c/sil164.h>
  39
  40#include <subdev/i2c.h>
  41
  42#define FP_TG_CONTROL_ON  (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |        \
  43                           NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |         \
  44                           NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
  45#define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE |    \
  46                           NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE |     \
  47                           NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
  48
  49static inline bool is_fpc_off(uint32_t fpc)
  50{
  51        return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
  52                        FP_TG_CONTROL_OFF);
  53}
  54
  55int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent)
  56{
  57        /* special case of nv_read_tmds to find crtc associated with an output.
  58         * this does not give a correct answer for off-chip dvi, but there's no
  59         * use for such an answer anyway
  60         */
  61        int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
  62
  63        NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
  64        NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
  65        return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
  66}
  67
  68void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
  69                        int head, bool dl)
  70{
  71        /* The BIOS scripts don't do this for us, sadly
  72         * Luckily we do know the values ;-)
  73         *
  74         * head < 0 indicates we wish to force a setting with the overrideval
  75         * (for VT restore etc.)
  76         */
  77
  78        int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
  79        uint8_t tmds04 = 0x80;
  80
  81        if (head != ramdac)
  82                tmds04 = 0x88;
  83
  84        if (dcbent->type == DCB_OUTPUT_LVDS)
  85                tmds04 |= 0x01;
  86
  87        nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
  88
  89        if (dl) /* dual link */
  90                nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
  91}
  92
  93void nv04_dfp_disable(struct drm_device *dev, int head)
  94{
  95        struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
  96
  97        if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
  98            FP_TG_CONTROL_ON) {
  99                /* digital remnants must be cleaned before new crtc
 100                 * values programmed.  delay is time for the vga stuff
 101                 * to realise it's in control again
 102                 */
 103                NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
 104                              FP_TG_CONTROL_OFF);
 105                msleep(50);
 106        }
 107        /* don't inadvertently turn it on when state written later */
 108        crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
 109        crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=
 110                ~NV_CIO_CRE_LCD_ROUTE_MASK;
 111}
 112
 113void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
 114{
 115        struct drm_device *dev = encoder->dev;
 116        struct drm_crtc *crtc;
 117        struct nouveau_crtc *nv_crtc;
 118        uint32_t *fpc;
 119
 120        if (mode == DRM_MODE_DPMS_ON) {
 121                nv_crtc = nouveau_crtc(encoder->crtc);
 122                fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
 123
 124                if (is_fpc_off(*fpc)) {
 125                        /* using saved value is ok, as (is_digital && dpms_on &&
 126                         * fp_control==OFF) is (at present) *only* true when
 127                         * fpc's most recent change was by below "off" code
 128                         */
 129                        *fpc = nv_crtc->dpms_saved_fp_control;
 130                }
 131
 132                nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
 133                NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
 134        } else {
 135                list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 136                        nv_crtc = nouveau_crtc(crtc);
 137                        fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
 138
 139                        nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
 140                        if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
 141                                nv_crtc->dpms_saved_fp_control = *fpc;
 142                                /* cut the FP output */
 143                                *fpc &= ~FP_TG_CONTROL_ON;
 144                                *fpc |= FP_TG_CONTROL_OFF;
 145                                NVWriteRAMDAC(dev, nv_crtc->index,
 146                                              NV_PRAMDAC_FP_TG_CONTROL, *fpc);
 147                        }
 148                }
 149        }
 150}
 151
 152static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
 153{
 154        struct drm_device *dev = encoder->dev;
 155        struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
 156        struct drm_encoder *slave;
 157
 158        if (dcb->type != DCB_OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
 159                return NULL;
 160
 161        /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
 162         * TMDS transmitters at the same I2C address, in the same I2C
 163         * bus. This can still work because in that case one of them is
 164         * always hard-wired to a reasonable configuration using straps,
 165         * and the other one needs to be programmed.
 166         *
 167         * I don't think there's a way to know which is which, even the
 168         * blob programs the one exposed via I2C for *both* heads, so
 169         * let's do the same.
 170         */
 171        list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
 172                struct dcb_output *slave_dcb = nouveau_encoder(slave)->dcb;
 173
 174                if (slave_dcb->type == DCB_OUTPUT_TMDS && get_slave_funcs(slave) &&
 175                    slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
 176                        return slave;
 177        }
 178
 179        return NULL;
 180}
 181
 182static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
 183                                const struct drm_display_mode *mode,
 184                                struct drm_display_mode *adjusted_mode)
 185{
 186        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 187        struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
 188
 189        if (!nv_connector->native_mode ||
 190            nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
 191            mode->hdisplay > nv_connector->native_mode->hdisplay ||
 192            mode->vdisplay > nv_connector->native_mode->vdisplay) {
 193                nv_encoder->mode = *adjusted_mode;
 194
 195        } else {
 196                nv_encoder->mode = *nv_connector->native_mode;
 197                adjusted_mode->clock = nv_connector->native_mode->clock;
 198        }
 199
 200        return true;
 201}
 202
 203static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
 204                                     struct nouveau_encoder *nv_encoder, int head)
 205{
 206        struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
 207        uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000;
 208
 209        if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
 210                return;
 211
 212        /* SEL_CLK is only used on the primary ramdac
 213         * It toggles spread spectrum PLL output and sets the bindings of PLLs
 214         * to heads on digital outputs
 215         */
 216        if (head)
 217                state->sel_clk |= bits1618;
 218        else
 219                state->sel_clk &= ~bits1618;
 220
 221        /* nv30:
 222         *      bit 0           NVClk spread spectrum on/off
 223         *      bit 2           MemClk spread spectrum on/off
 224         *      bit 4           PixClk1 spread spectrum on/off toggle
 225         *      bit 6           PixClk2 spread spectrum on/off toggle
 226         *
 227         * nv40 (observations from bios behaviour and mmio traces):
 228         *      bits 4&6        as for nv30
 229         *      bits 5&7        head dependent as for bits 4&6, but do not appear with 4&6;
 230         *                      maybe a different spread mode
 231         *      bits 8&10       seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
 232         *      The logic behind turning spread spectrum on/off in the first place,
 233         *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
 234         *      entry has the necessary info)
 235         */
 236        if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
 237                int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
 238
 239                state->sel_clk &= ~0xf0;
 240                state->sel_clk |= (head ? 0x40 : 0x10) << shift;
 241        }
 242}
 243
 244static void nv04_dfp_prepare(struct drm_encoder *encoder)
 245{
 246        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 247        const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 248        struct drm_device *dev = encoder->dev;
 249        int head = nouveau_crtc(encoder->crtc)->index;
 250        struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
 251        uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
 252        uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
 253
 254        helper->dpms(encoder, DRM_MODE_DPMS_OFF);
 255
 256        nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
 257
 258        *cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3;
 259
 260        if (nv_two_heads(dev)) {
 261                if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
 262                        *cr_lcd |= head ? 0x0 : 0x8;
 263                else {
 264                        *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
 265                        if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
 266                                *cr_lcd |= 0x30;
 267                        if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
 268                                /* avoid being connected to both crtcs */
 269                                *cr_lcd_oth &= ~0x30;
 270                                NVWriteVgaCrtc(dev, head ^ 1,
 271                                               NV_CIO_CRE_LCD__INDEX,
 272                                               *cr_lcd_oth);
 273                        }
 274                }
 275        }
 276}
 277
 278
 279static void nv04_dfp_mode_set(struct drm_encoder *encoder,
 280                              struct drm_display_mode *mode,
 281                              struct drm_display_mode *adjusted_mode)
 282{
 283        struct drm_device *dev = encoder->dev;
 284        struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
 285        struct nouveau_drm *drm = nouveau_drm(dev);
 286        struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 287        struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
 288        struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
 289        struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
 290        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 291        struct drm_display_mode *output_mode = &nv_encoder->mode;
 292        struct drm_connector *connector = &nv_connector->base;
 293        const struct drm_framebuffer *fb = encoder->crtc->primary->fb;
 294        uint32_t mode_ratio, panel_ratio;
 295
 296        NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index);
 297        drm_mode_debug_printmodeline(output_mode);
 298
 299        /* Initialize the FP registers in this CRTC. */
 300        regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
 301        regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
 302        if (!nv_gf4_disp_arch(dev) ||
 303            (output_mode->hsync_start - output_mode->hdisplay) >=
 304                                        drm->vbios.digital_min_front_porch)
 305                regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
 306        else
 307                regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1;
 308        regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
 309        regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
 310        regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
 311        regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
 312
 313        regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
 314        regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
 315        regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
 316        regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
 317        regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
 318        regp->fp_vert_regs[FP_VALID_START] = 0;
 319        regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
 320
 321        /* bit26: a bit seen on some g7x, no as yet discernable purpose */
 322        regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
 323                           (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
 324        /* Deal with vsync/hsync polarity */
 325        /* LVDS screens do set this, but modes with +ve syncs are very rare */
 326        if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
 327                regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
 328        if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
 329                regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
 330        /* panel scaling first, as native would get set otherwise */
 331        if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
 332            nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER)        /* panel handles it */
 333                regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
 334        else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
 335                 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
 336                regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
 337        else /* gpu needs to scale */
 338                regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
 339        if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
 340                regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
 341        if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
 342            output_mode->clock > 165000)
 343                regp->fp_control |= (2 << 24);
 344        if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
 345                bool duallink = false, dummy;
 346                if (nv_connector->edid &&
 347                    nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
 348                        duallink = (((u8 *)nv_connector->edid)[121] == 2);
 349                } else {
 350                        nouveau_bios_parse_lvds_table(dev, output_mode->clock,
 351                                                      &duallink, &dummy);
 352                }
 353
 354                if (duallink)
 355                        regp->fp_control |= (8 << 28);
 356        } else
 357        if (output_mode->clock > 165000)
 358                regp->fp_control |= (8 << 28);
 359
 360        regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
 361                           NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
 362                           NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
 363                           NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
 364                           NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
 365                           NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
 366                           NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
 367
 368        /* We want automatic scaling */
 369        regp->fp_debug_1 = 0;
 370        /* This can override HTOTAL and VTOTAL */
 371        regp->fp_debug_2 = 0;
 372
 373        /* Use 20.12 fixed point format to avoid floats */
 374        mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
 375        panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
 376        /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
 377         * get treated the same as SCALE_FULLSCREEN */
 378        if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
 379            mode_ratio != panel_ratio) {
 380                uint32_t diff, scale;
 381                bool divide_by_2 = nv_gf4_disp_arch(dev);
 382
 383                if (mode_ratio < panel_ratio) {
 384                        /* vertical needs to expand to glass size (automatic)
 385                         * horizontal needs to be scaled at vertical scale factor
 386                         * to maintain aspect */
 387
 388                        scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
 389                        regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
 390                                           XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
 391
 392                        /* restrict area of screen used, horizontally */
 393                        diff = output_mode->hdisplay -
 394                               output_mode->vdisplay * mode_ratio / (1 << 12);
 395                        regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
 396                        regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
 397                }
 398
 399                if (mode_ratio > panel_ratio) {
 400                        /* horizontal needs to expand to glass size (automatic)
 401                         * vertical needs to be scaled at horizontal scale factor
 402                         * to maintain aspect */
 403
 404                        scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
 405                        regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
 406                                           XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
 407
 408                        /* restrict area of screen used, vertically */
 409                        diff = output_mode->vdisplay -
 410                               (1 << 12) * output_mode->hdisplay / mode_ratio;
 411                        regp->fp_vert_regs[FP_VALID_START] += diff / 2;
 412                        regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
 413                }
 414        }
 415
 416        /* Output property. */
 417        if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
 418            (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
 419             fb->format->depth > connector->display_info.bpc * 3)) {
 420                if (drm->client.device.info.chipset == 0x11)
 421                        regp->dither = savep->dither | 0x00010000;
 422                else {
 423                        int i;
 424                        regp->dither = savep->dither | 0x00000001;
 425                        for (i = 0; i < 3; i++) {
 426                                regp->dither_regs[i] = 0xe4e4e4e4;
 427                                regp->dither_regs[i + 3] = 0x44444444;
 428                        }
 429                }
 430        } else {
 431                if (drm->client.device.info.chipset != 0x11) {
 432                        /* reset them */
 433                        int i;
 434                        for (i = 0; i < 3; i++) {
 435                                regp->dither_regs[i] = savep->dither_regs[i];
 436                                regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
 437                        }
 438                }
 439                regp->dither = savep->dither;
 440        }
 441
 442        regp->fp_margin_color = 0;
 443}
 444
 445static void nv04_dfp_commit(struct drm_encoder *encoder)
 446{
 447        struct drm_device *dev = encoder->dev;
 448        struct nouveau_drm *drm = nouveau_drm(dev);
 449        const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 450        struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 451        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 452        struct dcb_output *dcbe = nv_encoder->dcb;
 453        int head = nouveau_crtc(encoder->crtc)->index;
 454        struct drm_encoder *slave_encoder;
 455
 456        if (dcbe->type == DCB_OUTPUT_TMDS)
 457                run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
 458        else if (dcbe->type == DCB_OUTPUT_LVDS)
 459                call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
 460
 461        /* update fp_control state for any changes made by scripts,
 462         * so correct value is written at DPMS on */
 463        nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
 464                NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
 465
 466        /* This could use refinement for flatpanels, but it should work this way */
 467        if (drm->client.device.info.chipset < 0x44)
 468                NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
 469        else
 470                NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
 471
 472        /* Init external transmitters */
 473        slave_encoder = get_tmds_slave(encoder);
 474        if (slave_encoder)
 475                get_slave_funcs(slave_encoder)->mode_set(
 476                        slave_encoder, &nv_encoder->mode, &nv_encoder->mode);
 477
 478        helper->dpms(encoder, DRM_MODE_DPMS_ON);
 479
 480        NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n",
 481                 nouveau_encoder_connector_get(nv_encoder)->base.name,
 482                 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 483}
 484
 485static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
 486{
 487#ifdef __powerpc__
 488        struct drm_device *dev = encoder->dev;
 489        struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
 490
 491        /* BIOS scripts usually take care of the backlight, thanks
 492         * Apple for your consistency.
 493         */
 494        if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 ||
 495            dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) {
 496                if (mode == DRM_MODE_DPMS_ON) {
 497                        nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
 498                        nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
 499                } else {
 500                        nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
 501                        nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 0);
 502                }
 503        }
 504#endif
 505}
 506
 507static inline bool is_powersaving_dpms(int mode)
 508{
 509        return mode != DRM_MODE_DPMS_ON && mode != NV_DPMS_CLEARED;
 510}
 511
 512static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
 513{
 514        struct drm_device *dev = encoder->dev;
 515        struct drm_crtc *crtc = encoder->crtc;
 516        struct nouveau_drm *drm = nouveau_drm(dev);
 517        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 518        bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
 519
 520        if (nv_encoder->last_dpms == mode)
 521                return;
 522        nv_encoder->last_dpms = mode;
 523
 524        NV_DEBUG(drm, "Setting dpms mode %d on lvds encoder (output %d)\n",
 525                 mode, nv_encoder->dcb->index);
 526
 527        if (was_powersaving && is_powersaving_dpms(mode))
 528                return;
 529
 530        if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
 531                /* when removing an output, crtc may not be set, but PANEL_OFF
 532                 * must still be run
 533                 */
 534                int head = crtc ? nouveau_crtc(crtc)->index :
 535                           nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
 536
 537                if (mode == DRM_MODE_DPMS_ON) {
 538                        call_lvds_script(dev, nv_encoder->dcb, head,
 539                                         LVDS_PANEL_ON, nv_encoder->mode.clock);
 540                } else
 541                        /* pxclk of 0 is fine for PANEL_OFF, and for a
 542                         * disconnected LVDS encoder there is no native_mode
 543                         */
 544                        call_lvds_script(dev, nv_encoder->dcb, head,
 545                                         LVDS_PANEL_OFF, 0);
 546        }
 547
 548        nv04_dfp_update_backlight(encoder, mode);
 549        nv04_dfp_update_fp_control(encoder, mode);
 550
 551        if (mode == DRM_MODE_DPMS_ON)
 552                nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
 553        else {
 554                nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
 555                nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
 556        }
 557        NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
 558}
 559
 560static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
 561{
 562        struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 563        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 564
 565        if (nv_encoder->last_dpms == mode)
 566                return;
 567        nv_encoder->last_dpms = mode;
 568
 569        NV_DEBUG(drm, "Setting dpms mode %d on tmds encoder (output %d)\n",
 570                 mode, nv_encoder->dcb->index);
 571
 572        nv04_dfp_update_backlight(encoder, mode);
 573        nv04_dfp_update_fp_control(encoder, mode);
 574}
 575
 576static void nv04_dfp_save(struct drm_encoder *encoder)
 577{
 578        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 579        struct drm_device *dev = encoder->dev;
 580
 581        if (nv_two_heads(dev))
 582                nv_encoder->restore.head =
 583                        nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
 584}
 585
 586static void nv04_dfp_restore(struct drm_encoder *encoder)
 587{
 588        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 589        struct drm_device *dev = encoder->dev;
 590        int head = nv_encoder->restore.head;
 591
 592        if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
 593                struct nouveau_connector *connector =
 594                        nouveau_encoder_connector_get(nv_encoder);
 595
 596                if (connector && connector->native_mode)
 597                        call_lvds_script(dev, nv_encoder->dcb, head,
 598                                         LVDS_PANEL_ON,
 599                                         connector->native_mode->clock);
 600
 601        } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) {
 602                int clock = nouveau_hw_pllvals_to_clk
 603                                        (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
 604
 605                run_tmds_table(dev, nv_encoder->dcb, head, clock);
 606        }
 607
 608        nv_encoder->last_dpms = NV_DPMS_CLEARED;
 609}
 610
 611static void nv04_dfp_destroy(struct drm_encoder *encoder)
 612{
 613        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 614
 615        if (get_slave_funcs(encoder))
 616                get_slave_funcs(encoder)->destroy(encoder);
 617
 618        drm_encoder_cleanup(encoder);
 619        kfree(nv_encoder);
 620}
 621
 622static void nv04_tmds_slave_init(struct drm_encoder *encoder)
 623{
 624        struct drm_device *dev = encoder->dev;
 625        struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
 626        struct nouveau_drm *drm = nouveau_drm(dev);
 627        struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 628        struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_PRI);
 629        struct nvkm_i2c_bus_probe info[] = {
 630                {
 631                    {
 632                        .type = "sil164",
 633                        .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
 634                        .platform_data = &(struct sil164_encoder_params) {
 635                            SIL164_INPUT_EDGE_RISING
 636                         }
 637                    }, 0
 638                },
 639                { }
 640        };
 641        int type;
 642
 643        if (!nv_gf4_disp_arch(dev) || !bus || get_tmds_slave(encoder))
 644                return;
 645
 646        type = nvkm_i2c_bus_probe(bus, "TMDS transmitter", info, NULL, NULL);
 647        if (type < 0)
 648                return;
 649
 650        drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
 651                             &bus->i2c, &info[type].dev);
 652}
 653
 654static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
 655        .dpms = nv04_lvds_dpms,
 656        .mode_fixup = nv04_dfp_mode_fixup,
 657        .prepare = nv04_dfp_prepare,
 658        .commit = nv04_dfp_commit,
 659        .mode_set = nv04_dfp_mode_set,
 660        .detect = NULL,
 661};
 662
 663static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
 664        .dpms = nv04_tmds_dpms,
 665        .mode_fixup = nv04_dfp_mode_fixup,
 666        .prepare = nv04_dfp_prepare,
 667        .commit = nv04_dfp_commit,
 668        .mode_set = nv04_dfp_mode_set,
 669        .detect = NULL,
 670};
 671
 672static const struct drm_encoder_funcs nv04_dfp_funcs = {
 673        .destroy = nv04_dfp_destroy,
 674};
 675
 676int
 677nv04_dfp_create(struct drm_connector *connector, struct dcb_output *entry)
 678{
 679        const struct drm_encoder_helper_funcs *helper;
 680        struct nouveau_encoder *nv_encoder = NULL;
 681        struct drm_encoder *encoder;
 682        int type;
 683
 684        switch (entry->type) {
 685        case DCB_OUTPUT_TMDS:
 686                type = DRM_MODE_ENCODER_TMDS;
 687                helper = &nv04_tmds_helper_funcs;
 688                break;
 689        case DCB_OUTPUT_LVDS:
 690                type = DRM_MODE_ENCODER_LVDS;
 691                helper = &nv04_lvds_helper_funcs;
 692                break;
 693        default:
 694                return -EINVAL;
 695        }
 696
 697        nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 698        if (!nv_encoder)
 699                return -ENOMEM;
 700
 701        nv_encoder->enc_save = nv04_dfp_save;
 702        nv_encoder->enc_restore = nv04_dfp_restore;
 703
 704        encoder = to_drm_encoder(nv_encoder);
 705
 706        nv_encoder->dcb = entry;
 707        nv_encoder->or = ffs(entry->or) - 1;
 708
 709        drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type, NULL);
 710        drm_encoder_helper_add(encoder, helper);
 711
 712        encoder->possible_crtcs = entry->heads;
 713        encoder->possible_clones = 0;
 714
 715        if (entry->type == DCB_OUTPUT_TMDS &&
 716            entry->location != DCB_LOC_ON_CHIP)
 717                nv04_tmds_slave_init(encoder);
 718
 719        drm_mode_connector_attach_encoder(connector, encoder);
 720        return 0;
 721}
 722