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24#include "gf100.h"
25#include "ctxgf100.h"
26
27#include <nvif/class.h>
28
29
30
31
32
33void
34gp100_gr_init_rop_active_fbps(struct gf100_gr *gr)
35{
36 struct nvkm_device *device = gr->base.engine.subdev.device;
37
38 const u32 fbp_count = nvkm_rd32(device, 0x12006c) & 0x0000000f;
39 nvkm_mask(device, 0x408850, 0x0000000f, fbp_count);
40 nvkm_mask(device, 0x408958, 0x0000000f, fbp_count);
41}
42
43void
44gp100_gr_init_num_active_ltcs(struct gf100_gr *gr)
45{
46 struct nvkm_device *device = gr->base.engine.subdev.device;
47
48 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
49 nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
50}
51
52int
53gp100_gr_init(struct gf100_gr *gr)
54{
55 struct nvkm_device *device = gr->base.engine.subdev.device;
56 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
57 u32 data[TPC_MAX / 8] = {};
58 u8 tpcnr[GPC_MAX];
59 int gpc, tpc, rop;
60 int i;
61
62 gr->func->init_gpc_mmu(gr);
63
64 gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
65
66 nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
67
68 memset(data, 0x00, sizeof(data));
69 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
70 for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
71 do {
72 gpc = (gpc + 1) % gr->gpc_nr;
73 } while (!tpcnr[gpc]);
74 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
75
76 data[i / 8] |= tpc << ((i % 8) * 4);
77 }
78
79 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
80 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
81 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
82 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
83
84 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
85 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
86 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
87 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
88 gr->tpc_total);
89 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
90 }
91
92 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
93 gr->func->init_num_active_ltcs(gr);
94
95 gr->func->init_rop_active_fbps(gr);
96 if (gr->func->init_swdx_pes_mask)
97 gr->func->init_swdx_pes_mask(gr);
98
99 nvkm_wr32(device, 0x400500, 0x00010001);
100 nvkm_wr32(device, 0x400100, 0xffffffff);
101 nvkm_wr32(device, 0x40013c, 0xffffffff);
102 nvkm_wr32(device, 0x400124, 0x00000002);
103 nvkm_wr32(device, 0x409c24, 0x000f0002);
104 nvkm_wr32(device, 0x405848, 0xc0000000);
105 nvkm_mask(device, 0x40584c, 0x00000000, 0x00000001);
106 nvkm_wr32(device, 0x404000, 0xc0000000);
107 nvkm_wr32(device, 0x404600, 0xc0000000);
108 nvkm_wr32(device, 0x408030, 0xc0000000);
109 nvkm_wr32(device, 0x404490, 0xc0000000);
110 nvkm_wr32(device, 0x406018, 0xc0000000);
111 nvkm_wr32(device, 0x407020, 0x40000000);
112 nvkm_wr32(device, 0x405840, 0xc0000000);
113 nvkm_wr32(device, 0x405844, 0x00ffffff);
114 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
115
116 nvkm_mask(device, 0x419c9c, 0x00010000, 0x00010000);
117 nvkm_mask(device, 0x419c9c, 0x00020000, 0x00020000);
118
119 gr->func->init_ppc_exceptions(gr);
120
121 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
122 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
123 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
124 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
125 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
126 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
127 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
128 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
129 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
130 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
131 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
132 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
133 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
134 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105);
135 }
136 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
137 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
138 }
139
140 for (rop = 0; rop < gr->rop_nr; rop++) {
141 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
142 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
143 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
144 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
145 }
146
147 nvkm_wr32(device, 0x400108, 0xffffffff);
148 nvkm_wr32(device, 0x400138, 0xffffffff);
149 nvkm_wr32(device, 0x400118, 0xffffffff);
150 nvkm_wr32(device, 0x400130, 0xffffffff);
151 nvkm_wr32(device, 0x40011c, 0xffffffff);
152 nvkm_wr32(device, 0x400134, 0xffffffff);
153
154 gf100_gr_zbc_init(gr);
155
156 return gf100_gr_init_ctxctl(gr);
157}
158
159static const struct gf100_gr_func
160gp100_gr = {
161 .init = gp100_gr_init,
162 .init_gpc_mmu = gm200_gr_init_gpc_mmu,
163 .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
164 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
165 .init_num_active_ltcs = gp100_gr_init_num_active_ltcs,
166 .rops = gm200_gr_rops,
167 .ppc_nr = 2,
168 .grctx = &gp100_grctx,
169 .sclass = {
170 { -1, -1, FERMI_TWOD_A },
171 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
172 { -1, -1, PASCAL_A, &gf100_fermi },
173 { -1, -1, PASCAL_COMPUTE_A },
174 {}
175 }
176};
177
178int
179gp100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
180{
181 return gm200_gr_new_(&gp100_gr, device, index, pgr);
182}
183